RegisterAddresss and RegisterValue: Removed the implicit conversions.
RegisterAddress: Changed member name from address_ to value_ and method as well to value().
RegisterValue: Also added | operator to be able to concatenate with uint32_t. Same in python bindings (but could not find the tests to modify
* shorter SHM names on macOS
* fix segfault on macOS when string is empty
* apple version of read exe path
* ifdef for linux specific API
* fixed test for shm and udp socket
* updated release notes
* add patternstart command for CTB, block end of execution udp packets if pattern was started by patternstart command
* update docs
* Dhanya's comments
* more Dhanya comments
* refactored
* fixed tests for startpatttern, also clkfrequency not properly used in server
* xilinx: fixed setfrequency, tick clock (with sync clock), clkfrequency set from getfrequency to get the exact value
* xilinx freq in kHz, updated default values and prints
---------
Co-authored-by: Martin Mueller <martin.mueller@psi.ch>
Co-authored-by: Dhanya Thattil <dhanya.thattil@psi.ch>
* update ctb regDefs, included fill level of adc, transceiver and DBit fifos, added enable registers for cont. readout
* fix fifo fill level range bug
* updated ctb RegDefs, increased size of fifo fill level register
* added register to read the firmware git hash
* ctb: added altchip_id read register
* start with unification of pattern machinery for xctb, ctb, mythen
* udate addrs for d-server internal matterhorn startup
* update xctb reg defs
* move pattern loopdef start
* added zero trimbits to matterhorn config
* Revert "added zero trimbits to matterhorn config"
This reverts commit 7c347badd5.
* added adjustable clocks on Xilinx-CTB
* added support for fractional dividers of runclk
* XCTB: make frequencies adjustable from python gui
* update docs
* added support for patternstart command to XCTB
* XCTB: map pattern_ram directly into memory, removed rw strobe
* refactor Mythen pattern control addresses
* test altera ctb with common addresses, removed ifdefs
* change ordering of regdefs
* updated python help for dbitclk, adcclk and runclk (khz)
* xilinx: moved the wait for firmware to measure the actual frequency to the server side and removed it in the pyctbgui side
* will not be anymore in developer branch
* make format (exception RegisterDefs.h), rewrite XILINX PLL to have less consstants in the code
* bug: mixing && for &
---------
Co-authored-by: Martin Mueller <martin.mueller@psi.ch>
Co-authored-by: Dhanya Thattil <dhanya.thattil@psi.ch>
- fix acquire fail in tests (adcreg test)
- roi tests fail after overlapping invalid test and acquire after
- print udp dest mac in server properly
- fixed udp dst list get (server was not sending entry proper size to match proper struct size in client)
- updated server binaries and updated hard links in serverBin
- added documentation regarding gui: zmqport and zmqip in terms of gui, rx_zmqstream
- removed print - probably ended there for debuggung
---------
Co-authored-by: Alice <alice.mazzoleni@psi.ch>
* added a 'isValid' member in shared memory (also updated shm version) with default true, any access to shared memory() checks also for validity. any free will set this to false and then unmap shm. Any access to shm will then check validity in python.
* fixed tests for shm
* added tests in python as well
---------
Co-authored-by: Alice <alice.mazzoleni@psi.ch>
readout speed added to json and h5 master files.
Also fixed master file inconsistencies
Sserver binaries
- update server binaries because readoutspeed needs to be sent to receiver with rx_hostname command
API
- added const to Detector class set/getburstmode
Python
- updated python bindings (burstmode const and roi arguments)
Cmd generation
- added pragma once in Caller.in.h as Caller is included in test files
m3: num channels due to #counters < 3
* workaround for m3 for messed up num channels (client always assumes all counters enabled and adds them to num channels), fix for hdf5
g2: exptime master file inconsistency
- exptime didnt match because of round of when setting burst mode (sets to a different clk divider)
- so updating actual time for all timers (exptime, period, subexptime etc, ) in Module class, get timer values from detector when setting it and then send to receiver to write in master file
ctb image size incorrect:
- write actual size into master file and not the reserved size (digital reduces depending on dbit list and dbit offset)
- added a calculate ctb image size free function in generalData.h that is used there as well as for the tests.
master file inconsistencies
- refactored master attributes writing using templates
- names changed to keep it consistent between json and hdf5 master file (Version, Pixels, Exposure Times, GateDelays, Acquisition Period, etc.)
- datatypes changed to keep it simple where possible: imageSize, dynamicRange, tengiga, quad, readnrows, analog, analogsamples, digital, digitalsamples, dbitreorder, dbitoffset, transceivermask, transeiver, transceiversamples, countermask, gates =>int
- replacing "toString" with arrays, objects etc for eg for scan, rois, etc.
- json header always written (empty dataset or empty brackets)
- hdf5 needs const char* so have to convert strings to it, but taking care that strings exist prior to push_back
- master attributes (redundant string literals->error prone
tests for master file
- suppressed deprecated functions in rapidjson warnings just for the tests
- added slsREceiverSoftware/src to allow access to receiver_defs.h to test binary/hdf5 version
- refactored acquire tests by moving all the acquire tests from individual detector type files to a single one=test-Caller-acquire.cpp
- set some default settings (loadBasicSettings) for a basic acquire at load config part for the test_simulator python scripts. so minimum number of settings for detector to be set for any acquire tests.
- added tests to test master files for json and hdf5= test-Caller-master-attributes.cpp
- added option to add '-m' markers for tests using test_simulator python script
