mirror of
https://github.com/slsdetectorgroup/slsDetectorPackage.git
synced 2025-04-26 00:00:02 +02:00
Added: embedded classes for Eiger
git-svn-id: file:///afs/psi.ch/project/sls_det_software/svn/slsDetectorSoftware@661 951219d9-93cf-4727-9268-0efd64621fa3
This commit is contained in:
johnson_i
parent
57d65fd59c
commit
fd9d627412
27
slsDetectorSoftware/eigerDetectorServer/Commands.txt
Normal file
27
slsDetectorSoftware/eigerDetectorServer/Commands.txt
Normal file
@ -0,0 +1,27 @@
|
||||
|
||||
Internal setup:
|
||||
setdac
|
||||
trimbits
|
||||
rate correction tau
|
||||
high voltage
|
||||
|
||||
|
||||
Setup:
|
||||
photon energy
|
||||
dynamic range (4,8,16,32)
|
||||
number of images
|
||||
exposure time
|
||||
exposure period
|
||||
readout speed(full speed, 1/2 speed, 1/4 or super slow)
|
||||
readout mode (parallel, non-parallel or super safe)
|
||||
trigger mode (internal,external start of series, external start of acquisitions, external window)
|
||||
trigger polarity (pos/neg)
|
||||
external gating (on, pos/neg)
|
||||
|
||||
|
||||
Acquisition:
|
||||
start acquisition
|
||||
stop acquisition
|
||||
acquisition in progress
|
||||
wait until daq is finished
|
||||
|
||||
999
slsDetectorSoftware/eigerDetectorServer/Eiger.cxx
Normal file
999
slsDetectorSoftware/eigerDetectorServer/Eiger.cxx
Normal file
@ -0,0 +1,999 @@
|
||||
|
||||
/**
|
||||
* @author Ian Johnson
|
||||
* @version 1.0
|
||||
*/
|
||||
|
||||
|
||||
#include <stdlib.h>
|
||||
#include <math.h>
|
||||
|
||||
#include <iostream>
|
||||
#include <fstream>
|
||||
#include <iomanip>
|
||||
#include <sstream>
|
||||
|
||||
|
||||
#include "EigerRegisterDefs.h"
|
||||
#include "Eiger.h"
|
||||
|
||||
using namespace std;
|
||||
|
||||
//GetDAQStatusRegister(512,current_mode_bits_from_fpga)){
|
||||
|
||||
const unsigned int Module::ndacs = 16;
|
||||
const string Module::dac_names[16] = {"SvP","Vtr","Vrf","Vrs","SvN","Vtgstv","Vcmp_ll","Vcmp_lr","cal","Vcmp_rl","rxb_rb","rxb_lb","Vcmp_rr","Vcp","Vcn","Vis"};
|
||||
|
||||
|
||||
Module::Module(unsigned int number, unsigned int address_top){
|
||||
module_number = number;
|
||||
top_address_valid = 1;
|
||||
top_left_address = 0x100 | (0xff & address_top);
|
||||
top_right_address = 0x200 | (0xff & address_top);
|
||||
bottom_address_valid = 0;
|
||||
bottom_left_address = 0;
|
||||
bottom_right_address = 0;
|
||||
|
||||
high_voltage = -1;
|
||||
top_dac = new float [ndacs];
|
||||
bottom_dac = new float [ndacs];
|
||||
for(unsigned int i=0;i<ndacs;i++) top_dac[i] = top_address_valid ? -1:0;
|
||||
for(unsigned int i=0;i<ndacs;i++) bottom_dac[i] = bottom_address_valid ? -1:0;
|
||||
}
|
||||
|
||||
Module::Module(unsigned int number, unsigned int address_top, unsigned int address_bottom){
|
||||
module_number = number;
|
||||
top_address_valid = 1;
|
||||
top_left_address = 0x100 | (0xff & address_top);
|
||||
top_right_address = 0x200 | (0xff & address_top);
|
||||
bottom_address_valid = 1;
|
||||
bottom_left_address = 0x100 | (0xff & address_bottom);
|
||||
bottom_right_address = 0x200 | (0xff & address_bottom);
|
||||
|
||||
high_voltage = -1;
|
||||
|
||||
for(unsigned int i=0;i<4;i++) idelay_top[i]=idelay_bottom[i]=0;
|
||||
|
||||
top_dac = new float [ndacs];
|
||||
bottom_dac = new float [ndacs];
|
||||
for(unsigned int i=0;i<ndacs;i++) top_dac[i] = top_address_valid ? -1:0;
|
||||
for(unsigned int i=0;i<ndacs;i++) bottom_dac[i] = bottom_address_valid ? -1:0;
|
||||
}
|
||||
|
||||
|
||||
Module::~Module(){
|
||||
delete [] top_dac;
|
||||
delete [] bottom_dac;
|
||||
}
|
||||
|
||||
|
||||
Eiger::Eiger(){
|
||||
|
||||
staticBits=acquireNReadoutMode=triggerMode=externalEnableMode=subFrameMode=0;
|
||||
|
||||
trimbit_size=263680;
|
||||
last_downloaded_trimbits = new unsigned char [trimbit_size];
|
||||
|
||||
Init();
|
||||
}
|
||||
|
||||
Eiger::~Eiger(){
|
||||
delete[] last_downloaded_trimbits;
|
||||
for(unsigned int i=0;i<modules.size();i++) delete modules[i];
|
||||
modules.clear();
|
||||
}
|
||||
|
||||
bool Eiger::Init(){
|
||||
|
||||
AddModule(0,0xfff); //global send
|
||||
|
||||
cout<<endl<<"Default Settings:"<<endl;
|
||||
nimages = 1;
|
||||
exposure_time_in_sec = 1;
|
||||
exposure_period_in_sec = 0;
|
||||
SetTestModeVariable(0);
|
||||
//SetPhotonEnergyCalibrationParameters(-5.8381e-5,1.838515,5.09948e-7,-4.32390e-11,1.32527e-15);
|
||||
//SetRateCorrection(0); //deactivate rate correction
|
||||
SetDynamicRange(16);
|
||||
SetPhotonEnergy(8000);
|
||||
SetReadoutMode();
|
||||
SetReadoutSpeed();
|
||||
SetTriggerMode();
|
||||
SetExternalEnableMode();
|
||||
cout<<endl<<endl;
|
||||
|
||||
|
||||
ReadSetUpFileToAddModules("setup.txt");
|
||||
cout<<"Setting detector defaults:"<<endl;
|
||||
ReadSetUpFile(0,"setup.txt"); //send defaults to all
|
||||
for(unsigned int i=1;i<modules.size();i++){
|
||||
char st[2000];
|
||||
sprintf(st,"setup_mod%04d.txt",modules[i]->GetModuleNumber());
|
||||
ReadSetUpFile(modules[i]->GetModuleNumber(),st);
|
||||
}
|
||||
CheckSetup();
|
||||
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
||||
bool Eiger::ReadSetUpFileToAddModules(string file_name){
|
||||
static ifstream infile;
|
||||
static string line;
|
||||
static char cmd_st[2000];
|
||||
static int value_i[3];
|
||||
|
||||
infile.open(file_name.c_str(),ios::in);
|
||||
if(!infile.is_open()) return 0;
|
||||
|
||||
cout<<endl;
|
||||
cout<<"Setting up detector:"<<endl;
|
||||
while(std::getline(infile,line)){
|
||||
if(line.length()<1) continue;
|
||||
istringstream iss(line);
|
||||
iss>>cmd_st;
|
||||
if(!strcmp("add_module",cmd_st)){
|
||||
if(!(iss>>value_i[0]>>value_i[1]>>value_i[2])){
|
||||
cout<<"Error adding module from "<<file_name<<"."<<endl;
|
||||
exit(0);
|
||||
}
|
||||
if(!AddModule(value_i[0],value_i[1],value_i[2])){
|
||||
cout<<"Error adding module, parameter was assigned twice in setup file: "<<file_name<<endl;
|
||||
exit(0);
|
||||
}
|
||||
}else if(!strcmp("add_half_module",cmd_st)){
|
||||
if(!(iss>>value_i[0]>>value_i[1])){
|
||||
cout<<"Error adding half module from "<<file_name<<"."<<endl;
|
||||
exit(0);
|
||||
}
|
||||
if(!AddModule(value_i[0],value_i[1])){
|
||||
cout<<"Error adding module, parameter was assigned twice in setup file: "<<file_name<<endl;
|
||||
exit(0);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
infile.close();
|
||||
PrintModuleList();
|
||||
unsigned int nfebs = 0;
|
||||
unsigned int* feb_list = new unsigned int [modules.size()*4];
|
||||
for(unsigned int i=1;i<modules.size();i++){
|
||||
if(modules[i]->TopAddressIsValid()){
|
||||
feb_list[nfebs++] = modules[i]->GetTopRightAddress();
|
||||
feb_list[nfebs++] = modules[i]->GetTopLeftAddress();
|
||||
}
|
||||
if(modules[i]->BottomAddressIsValid()){
|
||||
feb_list[nfebs++] = modules[i]->GetBottomRightAddress();
|
||||
feb_list[nfebs++] = modules[i]->GetBottomLeftAddress();
|
||||
}
|
||||
}
|
||||
|
||||
SendCompleteFebList(nfebs,feb_list);
|
||||
delete [] feb_list;
|
||||
|
||||
cout<<endl;
|
||||
|
||||
return CheckCommunication();
|
||||
}
|
||||
|
||||
void Eiger::PrintModuleList(){
|
||||
cout<<"\tModule list:"<<endl;
|
||||
for(unsigned int i=0;i<modules.size();i++){
|
||||
if(i==0) cout<<"\t\t"<<i<<") All modules: ";
|
||||
else if(i==1) cout<<"\t\t"<<i<<") Master module : ";
|
||||
else cout<<"\t\t"<<i<<") module : ";
|
||||
cout<<modules[i]->GetModuleNumber()<<" ";
|
||||
if(modules[i]->TopAddressIsValid()) cout<<hex<<modules[i]->GetTopBaseAddress()<<" (top) "<<dec;
|
||||
if(modules[i]->BottomAddressIsValid()) cout<<hex<<modules[i]->GetBottomBaseAddress()<<" (bottom)"<<dec;
|
||||
cout<<endl;
|
||||
}
|
||||
}
|
||||
|
||||
bool Eiger::GetModuleIndex(unsigned int module_number, unsigned int& module_index){
|
||||
for(unsigned int i=0;i<modules.size();i++){
|
||||
if(modules[i]->GetModuleNumber()==module_number){
|
||||
module_index=i;
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
bool Eiger::CheckModuleAddresses(unsigned int top_address, unsigned int bottom_address){
|
||||
bool found_t = 0;
|
||||
bool found_b = 0;
|
||||
for(unsigned int i=0;i<modules.size();i++){
|
||||
if(top_address!=0 && (top_address==modules[i]->GetTopBaseAddress() || top_address==modules[i]->GetBottomBaseAddress())) found_t=1;
|
||||
if(bottom_address!=0 && (bottom_address==modules[i]->GetTopBaseAddress() || bottom_address==modules[i]->GetBottomBaseAddress())) found_b=1;
|
||||
}
|
||||
|
||||
if(top_address==bottom_address) cout<<"\tWarning: top and bottom address are the same "<<top_address<<"."<<endl;
|
||||
if(found_t) cout<<"\tWarning: top address "<< top_address<<" already used."<<endl;
|
||||
if(found_b) cout<<"\tWarning: bottom address "<< bottom_address<<" already used."<<endl;
|
||||
|
||||
return !(top_address==bottom_address||found_t||found_b);
|
||||
}
|
||||
|
||||
bool Eiger::AddModule(unsigned int module_number, unsigned int top_address){
|
||||
return AddModule(module_number,top_address,0,1);
|
||||
}
|
||||
bool Eiger::AddModule(unsigned int module_number, unsigned int top_address, unsigned int bottom_address, bool half_module){ //bot_address 0 for half module
|
||||
bool parameters_ok = 1;
|
||||
unsigned int pre_module_index = 0;
|
||||
if(GetModuleIndex(module_number,pre_module_index)){
|
||||
cout<<"\tRemoving previous assignment of module number "<<module_number<<"."<<endl;
|
||||
delete modules[pre_module_index];
|
||||
modules.erase(modules.begin()+pre_module_index);
|
||||
parameters_ok = 0;
|
||||
}
|
||||
parameters_ok&&CheckModuleAddresses(top_address,bottom_address);
|
||||
|
||||
if(half_module){
|
||||
cout<<"\tAdding half module number "<<module_number<<" with base address: "<<top_address<<endl;
|
||||
modules.push_back(new Module(module_number,top_address));
|
||||
}else{
|
||||
cout<<"\tAdding full module number "<<module_number<<" with top and bottom base addresses: "<<top_address<<" "<<bottom_address<<endl;
|
||||
modules.push_back(new Module(module_number,top_address,bottom_address));
|
||||
}
|
||||
|
||||
|
||||
return parameters_ok;
|
||||
}
|
||||
|
||||
|
||||
bool Eiger::ReadSetUpFile(unsigned int module_num, string file_name){
|
||||
static ifstream infile;
|
||||
static string line;
|
||||
static char cmd_st[2000];
|
||||
static int value_i[3];
|
||||
static float value_f;
|
||||
|
||||
infile.open(file_name.c_str(),ios::in);
|
||||
if(!infile.is_open()){
|
||||
cout<<"Warning setup file not found: "<<file_name<<"."<<endl;
|
||||
return 0;
|
||||
}
|
||||
|
||||
while(std::getline(infile,line)){
|
||||
if(line.length()<1) continue;
|
||||
istringstream iss(line);
|
||||
iss>>cmd_st;
|
||||
|
||||
if(cmd_st[0]=='#'||!strcmp("add_module",cmd_st)||!strcmp("add_half_module",cmd_st)){ ;// cout<<"do nothing "<<cmd_st<<" "<<value_st<<endl;
|
||||
|
||||
}else if(!strcmp("iodelay",cmd_st)){
|
||||
if(!(iss>>value_i[0])) cout<<"Error reading iodelay from "<<file_name<<"."<<endl;
|
||||
SetIDelays(module_num,value_i[0]);
|
||||
}else if(!strcmp("high_voltage",cmd_st)){
|
||||
iss>>value_f;
|
||||
SetHighVoltage(module_num,value_f);
|
||||
}else if(!strcmp("photon_energy",cmd_st)){
|
||||
iss>>value_f;
|
||||
SetPhotonEnergy(value_f);
|
||||
}else if(!strcmp("dynamic_range",cmd_st)){
|
||||
iss>>value_i[0];
|
||||
SetDynamicRange(value_i[0]);
|
||||
}else if(!strcmp("readout_speed",cmd_st)){
|
||||
iss>>value_i[0];
|
||||
SetReadoutSpeed(value_i[0]);
|
||||
}else if(!strcmp("readout_mode",cmd_st)){
|
||||
iss>>value_i[0];
|
||||
SetReadoutMode(value_i[0]);
|
||||
}else{
|
||||
iss>>value_f;
|
||||
if(module_num>0) sprintf(cmd_st,"mod%d::%s",module_num,cmd_st);
|
||||
if(!SetDAC(cmd_st,value_f)) cout<<"error in string: "<<cmd_st<<endl;
|
||||
}
|
||||
// cout<<cmd_st<<" "<<value_st<<endl;
|
||||
}
|
||||
infile.close();
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
||||
bool Eiger::CheckSetup(){
|
||||
bool ok = 1;
|
||||
|
||||
for(unsigned int i=0;i<modules.size();i++){
|
||||
for(unsigned int j=0;j<4;j++){
|
||||
if(modules[i]->GetTopIDelay(j)<0){
|
||||
cout<<"Warning: module "<<modules[i]->GetModuleNumber()<<"'s idelay top number "<<j<<"not set."<<endl;
|
||||
ok=0;
|
||||
}
|
||||
if(modules[i]->GetBottomIDelay(j)<0){
|
||||
cout<<"Warning: module "<<modules[i]->GetModuleNumber()<<"'s idelay bottom number "<<j<<"not set."<<endl;
|
||||
ok=0;
|
||||
}
|
||||
}
|
||||
if(modules[i]->GetHighVoltage()<0){
|
||||
cout<<"Warning: module "<<modules[i]->GetModuleNumber()<<"'s high voltage not set."<<endl;
|
||||
ok=0;
|
||||
}
|
||||
for(unsigned int j=0;j<Module::ndacs;j++){
|
||||
if(modules[i]->GetTopDACVoltage(j)<0){
|
||||
cout<<"Warning: module "<<modules[i]->GetModuleNumber()<<"'s top \""<<Module::dac_names[i]<<"\" dac is not set."<<endl;
|
||||
ok=0;
|
||||
}
|
||||
if(modules[i]->GetBottomDACVoltage(j)<0){
|
||||
cout<<"Warning: module "<<modules[i]->GetModuleNumber()<<"'s bottom \""<<Module::dac_names[i]<<"\" dac is not set."<<endl;
|
||||
ok=0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return ok;
|
||||
}
|
||||
|
||||
bool Eiger::SetPhotonEnergy(unsigned int full_energy_eV){
|
||||
photon_energy_eV = full_energy_eV;
|
||||
cout<<"Setting photon energy to: "<<photon_energy_eV<<" eV"<<endl;
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
bool Eiger::SetIDelays(unsigned int module_num, unsigned int ndelay_units){
|
||||
return SetIDelays(module_num,0,ndelay_units)&&SetIDelays(module_num,1,ndelay_units)&&SetIDelays(module_num,2,ndelay_units)&&SetIDelays(module_num,3,ndelay_units);
|
||||
}
|
||||
|
||||
bool Eiger::SetIDelays(unsigned int module_num, unsigned int chip_pos, unsigned int ndelay_units){ //chip_pos 0=ll,1=lr,0=rl,1=rr
|
||||
//currently set same for top and bottom
|
||||
if(chip_pos>3){
|
||||
cout<<"Error SetIDelay chip_pos "<<chip_pos<<" doesn't exist."<<endl;
|
||||
return 0;
|
||||
}
|
||||
|
||||
unsigned int module_index=0;
|
||||
if(!GetModuleIndex(module_num,module_index)){
|
||||
cout<<"Error could not set i delay module number "<<module_num<<" invalid."<<endl;
|
||||
return 0;
|
||||
}
|
||||
|
||||
bool ok = 1;
|
||||
if(chip_pos/2==0){ //left fpga
|
||||
if(modules[module_index]->TopAddressIsValid()){
|
||||
if(SendIDelays(modules[module_index]->GetTopLeftAddress(),chip_pos%2==0,0xffffffff,ndelay_units)){
|
||||
if(module_index!=0) modules[module_index]->SetTopIDelay(chip_pos,ndelay_units);
|
||||
else for(unsigned int i=0;i<modules.size();i++) modules[i]->SetTopIDelay(chip_pos,ndelay_units);
|
||||
}else{
|
||||
cout<<"Error could not set idelay module number "<<module_num<<" (top_left)."<<endl;
|
||||
ok=0;
|
||||
}
|
||||
}
|
||||
if(modules[module_index]->BottomAddressIsValid()){
|
||||
if(SendIDelays(modules[module_index]->GetBottomLeftAddress(),chip_pos%2==0,0xffffffff,ndelay_units)){
|
||||
if(module_index!=0) modules[module_index]->SetBottomIDelay(chip_pos,ndelay_units);
|
||||
else for(unsigned int i=0;i<modules.size();i++) modules[i]->SetBottomIDelay(chip_pos,ndelay_units);
|
||||
}else{
|
||||
cout<<"Error could not set idelay module number "<<module_num<<" (bottom_left)."<<endl;
|
||||
ok=0;
|
||||
}
|
||||
}
|
||||
}else{
|
||||
if(modules[module_index]->TopAddressIsValid()){
|
||||
if(SendIDelays(modules[module_index]->GetTopRightAddress(),chip_pos%2==0,0xffffffff,ndelay_units)){
|
||||
if(module_index!=0) modules[module_index]->SetTopIDelay(chip_pos,ndelay_units);
|
||||
else for(unsigned int i=0;i<modules.size();i++) modules[i]->SetTopIDelay(chip_pos,ndelay_units);
|
||||
}else{
|
||||
cout<<"Error could not set idelay module number "<<module_num<<" (top_right)."<<endl;
|
||||
ok=0;
|
||||
}
|
||||
}
|
||||
if(modules[module_index]->BottomAddressIsValid()){
|
||||
if(SendIDelays(modules[module_index]->GetBottomRightAddress(),chip_pos%2==0,0xffffffff,ndelay_units)){
|
||||
if(module_index!=0) modules[module_index]->SetBottomIDelay(chip_pos,ndelay_units);
|
||||
else for(unsigned int i=0;i<modules.size();i++) modules[i]->SetBottomIDelay(chip_pos,ndelay_units);
|
||||
}else{
|
||||
cout<<"Error could not set idelay module number "<<module_num<<" (bottom_right)."<<endl;
|
||||
ok=0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return ok;
|
||||
}
|
||||
|
||||
|
||||
bool Eiger::SendIDelays(unsigned int dst_num, bool chip_lr, unsigned int channels, unsigned int ndelay_units){
|
||||
// cout<<"sending idelay :"<<dst_num<<" (lr-"<<chip_lr<<") to "<<ndelay_units<<endl;
|
||||
|
||||
if(ndelay_units>0x3ff) ndelay_units=0x3ff;
|
||||
// this is global
|
||||
unsigned int delay_data_valid_nclks = 15 - ((ndelay_units&0x3c0)>>6); //data valid delay upto 15 clks
|
||||
ndelay_units &= 0x3f; //up to 64 delay units
|
||||
// ndelay_unit |= 0x40; //and one bit for a full clock delay for the enabled pixels is zero for now
|
||||
|
||||
unsigned int set_left_delay_channels = chip_lr ? channels:0;
|
||||
unsigned int set_right_delay_channels = chip_lr ? 0:channels;
|
||||
|
||||
cout<<"\tSetting delays of ";
|
||||
if(set_left_delay_channels!=0) cout<<"left chips of dst_num "<<dst_num;
|
||||
else if(set_right_delay_channels!=0) cout<<"right chips of dst_num "<<dst_num;
|
||||
// else if(dst_num<0&&set_right_delay_channels!=0) cout<<"right chips";
|
||||
// else if(set_left_delay_channels!=0) cout<<"chip "<<dst_num;
|
||||
// else if(set_right_delay_channels!=0) cout<<"chip "<<dst_num;
|
||||
cout<<", tracks 0x"<<hex<<channels<<dec<<" to: "<<(((15-delay_data_valid_nclks)<<6)|ndelay_units)<<", "<<delay_data_valid_nclks<<" clks and "<<ndelay_units<<" units."<<endl;
|
||||
|
||||
if(!WriteRegister(dst_num,CHIP_DATA_OUT_DELAY_REG2, 1<<31 | delay_data_valid_nclks<<16 | ndelay_units) || //the 1<<31 time enables the setting of the data valid delays
|
||||
!WriteRegister(dst_num,CHIP_DATA_OUT_DELAY_REG3,set_left_delay_channels) ||
|
||||
!WriteRegister(dst_num,CHIP_DATA_OUT_DELAY_REG4,set_right_delay_channels) ||
|
||||
!WriteRegister(dst_num,CHIP_DATA_OUT_DELAY_REG_CTRL,CHIP_DATA_OUT_DELAY_SET,1,1)){
|
||||
cout<<"Warning: could not SetChipDataInputDelays(...)."<<endl;
|
||||
return 0;
|
||||
}
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
/*float Eiger::GetIDelays(){
|
||||
return idelay;
|
||||
}
|
||||
*/
|
||||
|
||||
bool Eiger::VoltageToDAC(float value, unsigned int& digital,unsigned int nsteps,float vmin,float vmax){
|
||||
if(value<vmin||value>vmax) return 0;
|
||||
digital = int(((value-vmin)/(vmax-vmin))*(nsteps-1) + 0.5);
|
||||
return 1;
|
||||
}
|
||||
|
||||
float Eiger::DACToVoltage(unsigned int digital,unsigned int nsteps,float vmin,float vmax){
|
||||
return vmin+(vmax-vmin)*digital/(nsteps-1);
|
||||
}
|
||||
|
||||
|
||||
bool Eiger::SetHighVoltage(unsigned int module_num,float value){
|
||||
unsigned int module_index=0;
|
||||
if(!GetModuleIndex(module_num,module_index)||!modules[module_index]->TopAddressIsValid()){
|
||||
cout<<"Error could not set high voltage module number "<<module_num<<" invalid."<<endl;
|
||||
return 0;
|
||||
}
|
||||
|
||||
if(!SendHighVoltage(modules[module_index]->GetTopRightAddress(),value)) return 0;
|
||||
|
||||
if(module_index!=0) modules[module_index]->SetHighVoltage(value);
|
||||
else for(unsigned int i=0;i<modules.size();i++) modules[i]->SetHighVoltage(value);
|
||||
|
||||
cout<<"\tHigh voltage of dst "<<modules[module_index]->GetTopRightAddress()<<" set to "<<modules[module_index]->GetHighVoltage()<<"."<<endl;
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
||||
bool Eiger::SendHighVoltage(unsigned int dst_num,float& value){
|
||||
// cout<<"sending high voltage to dst_num "<<dst_num<<"."<<endl;
|
||||
|
||||
static const unsigned int nsteps = 256;
|
||||
static const float vmin=0;
|
||||
static const float vmax=300;
|
||||
|
||||
unsigned int b = 0;
|
||||
if(!VoltageToDAC(value,b,nsteps,vmin,vmax)){
|
||||
cout<<"Waring: SetHighVoltage bad value, "<<value<<". The range is 0 to 300 V."<<endl;
|
||||
return 0;
|
||||
}
|
||||
|
||||
unsigned int r = 0x20000000 | (b&0xff);
|
||||
if(!WriteRegister(dst_num,0,r)){
|
||||
cout<<"Warning: trouble setting high voltage for dst_num "<<dst_num<<"."<<endl;
|
||||
return 0;
|
||||
}
|
||||
|
||||
value = DACToVoltage(b,nsteps,vmin,vmax);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
bool Eiger::SetDAC(string dac_str, float value){
|
||||
|
||||
string local_s = dac_str;
|
||||
unsigned int module_index = 0;
|
||||
|
||||
size_t p1 = local_s.find("mod");
|
||||
size_t p2 = local_s.find("::");
|
||||
if(p1!=string::npos&&p2!=string::npos&&(p1+3)<p2){
|
||||
unsigned int number = atoi((local_s.substr(p1+3,p2-3)).c_str());
|
||||
if(!GetModuleIndex(number,module_index)){
|
||||
cout<<"Error in dac_name \""<<dac_str<<"\", module number "<<number<<" not in list."<<endl;
|
||||
return 0;
|
||||
}
|
||||
local_s = local_s.substr(p2+2);
|
||||
}
|
||||
|
||||
bool top = 1;
|
||||
bool bottom = 1;
|
||||
if((p1 = local_s.find("top::"))!=string::npos){
|
||||
local_s = local_s.substr(p1+5);
|
||||
bottom=0;
|
||||
}else if((p1 = local_s.find("bottom::"))!=string::npos){
|
||||
local_s = local_s.substr(p1+8);
|
||||
top=0;
|
||||
}
|
||||
|
||||
unsigned int dac_ch = 0;
|
||||
if(!GetDACNumber(local_s,dac_ch)) return 0;
|
||||
|
||||
if(top&&modules[module_index]->TopAddressIsValid()){
|
||||
float v = value;
|
||||
if(!SendDACValue(modules[module_index]->GetTopRightAddress(),dac_ch,v)) return 0;
|
||||
if(module_index!=0) modules[module_index]->SetTopDACVoltage(dac_ch,v);
|
||||
else for(unsigned int i=0;i<modules.size();i++) modules[i]->SetTopDACVoltage(dac_ch,v);
|
||||
|
||||
}
|
||||
if(bottom&&modules[module_index]->BottomAddressIsValid()){
|
||||
float v = value;
|
||||
if(!SendDACValue(modules[module_index]->GetBottomRightAddress(),dac_ch,v)) return 0;
|
||||
if(module_index!=0) modules[module_index]->SetBottomDACVoltage(dac_ch,v);
|
||||
else for(unsigned int i=0;i<modules.size();i++) modules[i]->SetBottomDACVoltage(dac_ch,v);
|
||||
}
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
bool Eiger::GetDAC(std::string s, float& ret_value){
|
||||
cout<<"Function Eiger::GetDAC need to be finished....."<<endl;
|
||||
ret_value=1.2;
|
||||
return 1;
|
||||
}
|
||||
|
||||
bool Eiger::GetDACNumber(string s, unsigned int& n){
|
||||
for(unsigned int i=0;i<Module::ndacs;i++){
|
||||
if(!strcmp(Module::dac_names[i].c_str(),s.c_str())){
|
||||
n=i;
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
bool Eiger::SendDACValue(unsigned int dst_num, unsigned int ch, float& value){
|
||||
|
||||
static unsigned int nsteps = 4096; //12 bit dac
|
||||
static float vmin = 0;
|
||||
static float vmax = 2;
|
||||
|
||||
if(ch<0||ch>15){
|
||||
cout<<"Warning invalid ch for SetDAC."<<endl;
|
||||
return 0;
|
||||
}
|
||||
|
||||
//if(voltage<0) return PowerDownDAC(socket_num,ch);
|
||||
|
||||
unsigned int b = 0;
|
||||
if(!VoltageToDAC(value,b,nsteps,vmin,vmax)){
|
||||
cout<<"Waring: SetDac bad value, "<<value<<". The range is 0 to 2 V."<<endl;
|
||||
return 0;
|
||||
}
|
||||
|
||||
unsigned int dac_ic = (ch<8) ? 1:2;
|
||||
unsigned int dac_ch = ch%8;
|
||||
unsigned int r = dac_ic<<30 | 3<<16 | dac_ch<<12 | (b&0xfff); //3 write and power up
|
||||
|
||||
|
||||
if(!WriteRegister(dst_num,0,r,1,0)){
|
||||
cout<<"Warning: trouble setting dac "<<ch<<" voltage."<<endl;
|
||||
return 0;
|
||||
}
|
||||
|
||||
value=DACToVoltage(b,nsteps,vmin,vmax);
|
||||
|
||||
cout<<"\tDac number"<<ch<<" ("<<Module::dac_names[ch]<<") of dst "<<dst_num<<" set to "<<value<<"."<<endl;
|
||||
return 1;
|
||||
}
|
||||
|
||||
/*
|
||||
float Eiger::GetDAC(string s){
|
||||
static unsigned int n;
|
||||
if(!GetDACNumber(s,n)) return 0;
|
||||
|
||||
return dac[n];
|
||||
}
|
||||
*/
|
||||
|
||||
bool Eiger::SetTrimbits(unsigned char *trimbits){
|
||||
|
||||
if(!Reset()) cout<<"Warning could not reset DAQ."<<endl;
|
||||
|
||||
for(int l_r=0;l_r<2;l_r++){
|
||||
unsigned int disable_chip_mask = l_r ? DAQ_CS_BAR_LEFT : DAQ_CS_BAR_RIGHT;
|
||||
|
||||
if(!(WriteRegister(0xfff,DAQ_REG_STATIC_BITS,disable_chip_mask|DAQ_STATIC_BIT_PROGRAM|DAQ_STATIC_BIT_M8)&&SetCommandRegister(DAQ_SET_STATIC_BIT)&&StartDAQOnlyNWaitForFinish())){
|
||||
cout<<"Could not select chips"<<endl;
|
||||
return 0;
|
||||
}
|
||||
|
||||
for(int row_set=0;row_set<16;row_set++){ //16 rows at a time
|
||||
if(row_set==0){
|
||||
if(!SetCommandRegister(DAQ_RESET_COMPLETELY|DAQ_SEND_A_TOKEN_IN|DAQ_LOAD_16ROWS_OF_TRIMBITS)){
|
||||
cout<<"Warning: Could not SetCommandRegister for loading trim bits."<<endl;
|
||||
return 0;
|
||||
}
|
||||
}else{
|
||||
if(!SetCommandRegister(DAQ_LOAD_16ROWS_OF_TRIMBITS)){
|
||||
cout<<"Warning: Could not SetCommandRegister for loading trim bits."<<endl;
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
static unsigned int trimbits_to_load_l[1024];
|
||||
static unsigned int trimbits_to_load_r[1024];
|
||||
for(int row=0;row<16;row++){
|
||||
int offset = 2*32*row; //2 lower upper offset, and 32 per row
|
||||
for(int sc=0;sc<32;sc++){ //shift_in element number 0-31, ie super column
|
||||
int super_column_start_position_l = 1030*row + l_r *258 + sc*8; //256 per row, 8 per super column
|
||||
int super_column_start_position_r = 1030*row + 516 + l_r *258 + sc*8; //256 per row, 8 per super column
|
||||
int chip_sc = 31 - sc; //also flipped
|
||||
trimbits_to_load_l[offset+chip_sc] = 0;
|
||||
trimbits_to_load_r[offset+chip_sc] = 0;
|
||||
for(int i=0;i<8;i++){ //pixel number
|
||||
trimbits_to_load_l[offset+chip_sc] |= ( 0x7 & trimbits[263679 - (row_set*16480+super_column_start_position_l+i)])<<((7-i)*4);//low
|
||||
trimbits_to_load_l[offset+chip_sc+32] |= ((0x38 & trimbits[263679 - (row_set*16480+super_column_start_position_l+i)])>>3)<<((7-i)*4);//upper
|
||||
trimbits_to_load_r[offset+chip_sc] |= ( 0x7 & trimbits[263679 - (row_set*16480+super_column_start_position_r+i)])<<((7-i)*4);//low
|
||||
trimbits_to_load_r[offset+chip_sc+32] |= ((0x38 & trimbits[263679 - (row_set*16480+super_column_start_position_r+i)])>>3)<<((7-i)*4);//upper
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if(!WriteMemory(0,0,0,1024,trimbits_to_load_r)||!WriteMemory(1,0,0,1024,trimbits_to_load_l)||!StartDAQOnlyNWaitForFinish()) return 0;
|
||||
}
|
||||
}
|
||||
|
||||
memcpy(last_downloaded_trimbits,trimbits,trimbit_size*sizeof(unsigned char));
|
||||
|
||||
return SetStaticBits(); //send the static bits
|
||||
}
|
||||
|
||||
|
||||
unsigned char* Eiger::GetTrimbits(){
|
||||
return last_downloaded_trimbits;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
bool Eiger::SetCommandRegister(unsigned int cmd){
|
||||
// if(fifo_enabled){
|
||||
// return WriteRegister(-1,DAQ_REG_CHIP_CMDS,cmd | DAQ_FIFO_ENABLE);
|
||||
// }
|
||||
return WriteRegister(0xfff,DAQ_REG_CHIP_CMDS,cmd);
|
||||
}
|
||||
|
||||
|
||||
bool Eiger::GetDAQStatusRegister(int socket_num, unsigned int &ret_status){
|
||||
|
||||
if(!ReadRegister(socket_num,DAQ_REG_STATUS,ret_status)){
|
||||
cout<<"Error: reading status register."<<endl;
|
||||
return 0;
|
||||
}
|
||||
|
||||
ret_status = (0x00FF0000 & ret_status) >> 16;
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
||||
bool Eiger::StartDAQOnlyNWaitForFinish(int sleep_time_us){
|
||||
if(!WriteRegister(0xfff,DAQ_REG_CTRL,0)||!WriteRegister(0xfff,DAQ_REG_CTRL,DAQ_CTRL_START)){
|
||||
cout<<"Warning: could not start."<<endl;
|
||||
return 0;
|
||||
}
|
||||
|
||||
return WaitForFinishedFlag(sleep_time_us);
|
||||
}
|
||||
|
||||
bool Eiger::WaitForFinishedFlag(int sleep_time_us){
|
||||
bool is_running = AcquisitionInProgress();
|
||||
while(is_running){
|
||||
usleep(sleep_time_us);
|
||||
is_running = AcquisitionInProgress();
|
||||
}
|
||||
if(is_running!=0){
|
||||
cout<<endl<<endl<<"Warning WaitForFinishedFlag comunication problem.."<<endl<<endl;
|
||||
return 0; //communication problem
|
||||
}
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
bool Eiger::AcquisitionInProgress(){
|
||||
unsigned int status_reg_r=0,status_reg_l=0;
|
||||
if(!(GetDAQStatusRegister(512,status_reg_r)&&GetDAQStatusRegister(256,status_reg_l))){
|
||||
cout<<"Waring trouble reading status register."<<endl;
|
||||
return -1;
|
||||
}
|
||||
|
||||
return (status_reg_r|status_reg_l)&DAQ_STATUS_DAQ_RUNNING;
|
||||
}
|
||||
|
||||
|
||||
bool Eiger::Reset(){
|
||||
if(!WriteRegister(0xfff,DAQ_REG_CTRL,0) || !WriteRegister(0xfff,DAQ_REG_CTRL,DAQ_CTRL_RESET) || !WriteRegister(0xfff,DAQ_REG_CTRL,0)){
|
||||
cout<<"Warning: Could not reset daq, no response from board."<<endl;
|
||||
return 0;
|
||||
}
|
||||
|
||||
return WaitForFinishedFlag();
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
bool Eiger::SetStaticBits(){
|
||||
//program=1,m4=2,m8=4,test=8,rotest=16,cs_bar_left=32,cs_bar_right=64
|
||||
if(!WriteRegister(0xfff,DAQ_REG_STATIC_BITS,staticBits) || !SetCommandRegister(DAQ_SET_STATIC_BIT) || !StartDAQOnlyNWaitForFinish()){
|
||||
cout<<"Warning: Could not set static bits"<<endl;
|
||||
return 0;
|
||||
}
|
||||
|
||||
return 1;
|
||||
}
|
||||
bool Eiger::SetStaticBits(unsigned int the_static_bits){
|
||||
staticBits = the_static_bits;
|
||||
return SetStaticBits();
|
||||
}
|
||||
|
||||
bool Eiger::SetTestModeVariable(bool on){
|
||||
if(on) staticBits |= DAQ_STATIC_BIT_CHIP_TEST; //setting test bit to high
|
||||
else staticBits &= (~DAQ_STATIC_BIT_CHIP_TEST); //setting test bit to low
|
||||
return 1;
|
||||
}
|
||||
|
||||
bool Eiger::GetTestModeVariable(){
|
||||
return staticBits&DAQ_STATIC_BIT_CHIP_TEST;
|
||||
}
|
||||
|
||||
bool Eiger::SetDynamicRange(unsigned int four_eight_sixteen_or_thirtytwo){
|
||||
static unsigned int everything_but_bit_mode = DAQ_STATIC_BIT_PROGRAM|DAQ_STATIC_BIT_CHIP_TEST|DAQ_STATIC_BIT_ROTEST;
|
||||
if(four_eight_sixteen_or_thirtytwo==4){
|
||||
staticBits = DAQ_STATIC_BIT_M4 | (staticBits&everything_but_bit_mode); //leave test bits in currernt state
|
||||
subFrameMode &= ~DAQ_NEXPOSURERS_ACTIVATE_AUTO_SUBIMAGING;
|
||||
}else if(four_eight_sixteen_or_thirtytwo==8){
|
||||
staticBits = DAQ_STATIC_BIT_M8 | (staticBits&everything_but_bit_mode);
|
||||
subFrameMode &= ~DAQ_NEXPOSURERS_ACTIVATE_AUTO_SUBIMAGING;
|
||||
}else if(four_eight_sixteen_or_thirtytwo==16){
|
||||
staticBits = DAQ_STATIC_BIT_M12 | (staticBits&everything_but_bit_mode);
|
||||
subFrameMode &= ~DAQ_NEXPOSURERS_ACTIVATE_AUTO_SUBIMAGING;
|
||||
}else if(four_eight_sixteen_or_thirtytwo==32){
|
||||
staticBits = DAQ_STATIC_BIT_M12 | (staticBits&everything_but_bit_mode);
|
||||
subFrameMode |= DAQ_NEXPOSURERS_ACTIVATE_AUTO_SUBIMAGING;
|
||||
}else{
|
||||
cout<<"Warning: dynamic range ("<<four_eight_sixteen_or_thirtytwo<<") not valid, not setting bit mode."<<endl;
|
||||
cout<<"Set dynamic range int must equal 4,8 16, or 32."<<endl;
|
||||
return 0;
|
||||
}
|
||||
|
||||
cout<<"Dynamic range set to: "<<four_eight_sixteen_or_thirtytwo<<endl;
|
||||
return 1;
|
||||
}
|
||||
|
||||
unsigned int Eiger::GetDynamicRange(){
|
||||
if(subFrameMode|DAQ_NEXPOSURERS_ACTIVATE_AUTO_SUBIMAGING) return 32;
|
||||
else if(DAQ_STATIC_BIT_M4&staticBits) return 4;
|
||||
else if(DAQ_STATIC_BIT_M8&staticBits) return 8;
|
||||
|
||||
return 16;
|
||||
}
|
||||
|
||||
bool Eiger::SetReadoutSpeed(unsigned int readout_speed){ //0->full,1->half,2->quarter or 3->super_slow
|
||||
acquireNReadoutMode &= (~DAQ_CHIP_CONTROLLER_SUPER_SLOW_SPEED);
|
||||
if(readout_speed==1){
|
||||
acquireNReadoutMode |= DAQ_CHIP_CONTROLLER_HALF_SPEED;
|
||||
cout<<"Everything at half speed, ie. reading with 50 MHz main clk (half speed) ...."<<endl;
|
||||
}else if(readout_speed==2){
|
||||
acquireNReadoutMode |= DAQ_CHIP_CONTROLLER_QUARTER_SPEED;
|
||||
cout<<"Everything at quarter speed, ie. reading with 25 MHz main clk (quarter speed) ...."<<endl;
|
||||
}else if(readout_speed==3){
|
||||
acquireNReadoutMode |= DAQ_CHIP_CONTROLLER_SUPER_SLOW_SPEED;
|
||||
cout<<"Everything at super slow speed, ie. reading with ~0.200 MHz main clk (super slow speed) ...."<<endl;
|
||||
}else{
|
||||
if(readout_speed){
|
||||
cout<<"Warning readout speed "<<readout_speed<<") unknown, defaulting to full speed."<<endl;
|
||||
cout<<"Everything at full speed, ie. reading with 100 MHz main clk (full speed) ...."<<endl;
|
||||
return 0;
|
||||
}
|
||||
cout<<"Everything at full speed, ie. reading with 100 MHz main clk (full speed) ...."<<endl;
|
||||
}
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
bool Eiger::SetReadoutMode(unsigned int readout_mode){ //0->parallel,1->non-parallel,2-> safe_mode
|
||||
acquireNReadoutMode &= (~DAQ_NEXPOSURERS_PARALLEL_MODE);
|
||||
if(readout_mode==1){
|
||||
acquireNReadoutMode |= DAQ_NEXPOSURERS_NORMAL_NONPARALLEL_MODE;
|
||||
cout<<"Readout mode set to normal non-parallel readout mode ... "<<endl;
|
||||
}else if(readout_mode==2){
|
||||
acquireNReadoutMode |= DAQ_NEXPOSURERS_SAFEST_MODE_ROW_CLK_BEFORE_MODE;
|
||||
cout<<"Readout mode set to safest mode, row clk before main clk readout sequence .... "<<endl;
|
||||
}else{
|
||||
acquireNReadoutMode |= DAQ_NEXPOSURERS_PARALLEL_MODE;
|
||||
if(readout_mode){
|
||||
cout<<"Warning readout mode "<<readout_mode<<") unknown, defaulting to full speed."<<endl;
|
||||
cout<<"Readout mode set to parrallel acquire/read mode .... "<<endl;
|
||||
return 0;
|
||||
}
|
||||
cout<<"Readout mode set to parrallel acquire/read mode .... "<<endl;
|
||||
}
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
bool Eiger::SetTriggerMode(unsigned int trigger_mode,bool polarity){
|
||||
//"00"-> internal exposure time and period,
|
||||
//"01"-> external acquistion start and internal exposure time and period,
|
||||
//"10"-> external start trigger and internal exposure time,
|
||||
//"11"-> external triggered start and stop of exposures
|
||||
triggerMode = (~DAQ_NEXPOSURERS_EXTERNAL_IMAGE_START_AND_STOP);
|
||||
|
||||
if(trigger_mode == 1){
|
||||
triggerMode = DAQ_NEXPOSURERS_EXTERNAL_ACQUISITION_START;
|
||||
cout<<"Trigger mode: external start of acquisition sequence, internal exposure length and period."<<endl;
|
||||
}else if(trigger_mode == 2){
|
||||
triggerMode = DAQ_NEXPOSURERS_EXTERNAL_IMAGE_START;
|
||||
cout<<"Trigger mode: external image start, internal exposure time."<<endl;
|
||||
}else if(trigger_mode == 3){
|
||||
triggerMode = DAQ_NEXPOSURERS_EXTERNAL_IMAGE_START_AND_STOP;
|
||||
cout<<"Trigger mode: externally controlled, external image window (start and stop)."<<endl;
|
||||
}else{
|
||||
triggerMode = DAQ_NEXPOSURERS_INTERNAL_ACQUISITION;
|
||||
if(trigger_mode) cout<<"Warning trigger "<<trigger_mode<<") unknown, defaulting to internal triggering."<<endl;
|
||||
|
||||
cout<<"Trigger mode: acquisition internally controlled exposure length and period."<<endl;
|
||||
return trigger_mode==0;
|
||||
}
|
||||
|
||||
if(polarity){
|
||||
triggerMode |= DAQ_NEXPOSURERS_EXTERNAL_TRIGGER_POLARITY;
|
||||
cout<<"External trigger polarity set to positive."<<endl;
|
||||
}else{
|
||||
triggerMode &= (~DAQ_NEXPOSURERS_EXTERNAL_TRIGGER_POLARITY);
|
||||
cout<<"External trigger polarity set to negitive."<<endl;
|
||||
}
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
||||
bool Eiger::SetExternalEnableMode(bool use_external_enable, bool polarity){
|
||||
if(use_external_enable){
|
||||
externalEnableMode |= DAQ_NEXPOSURERS_EXTERNAL_ENABLING;
|
||||
cout<<"External enabling enabled, ";
|
||||
if(polarity){
|
||||
externalEnableMode |= DAQ_NEXPOSURERS_EXTERNAL_ENABLING_POLARITY;
|
||||
cout<<", polarity set to positive."<<endl;
|
||||
}else{
|
||||
externalEnableMode &= (~DAQ_NEXPOSURERS_EXTERNAL_ENABLING_POLARITY);
|
||||
cout<<", polarity set to negative."<<endl;
|
||||
}
|
||||
}else{
|
||||
externalEnableMode &= (~DAQ_NEXPOSURERS_EXTERNAL_ENABLING);
|
||||
cout<<"External enabling disabled."<<endl;
|
||||
}
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
bool Eiger::SetNImages(unsigned int n_images){
|
||||
if(!nimages){
|
||||
cout<<"Warning nimages must be greater than zero."<<nimages<<endl;
|
||||
return 0;
|
||||
}
|
||||
|
||||
nimages = n_images;
|
||||
cout<<"Number of images set to: "<<nimages<<endl;
|
||||
return 1;
|
||||
}
|
||||
unsigned int Eiger::GetNImages(){return nimages;}
|
||||
|
||||
bool Eiger::SetExposureTime(float the_exposure_time_in_sec){
|
||||
exposure_time_in_sec = the_exposure_time_in_sec;
|
||||
cout<<"Exposure time set to: "<<exposure_time_in_sec<<endl;
|
||||
return 1;
|
||||
}
|
||||
float Eiger::GetExposureTime(){return exposure_time_in_sec;}
|
||||
|
||||
bool Eiger::SetExposurePeriod(float the_exposure_period_in_sec){
|
||||
exposure_period_in_sec = the_exposure_period_in_sec;
|
||||
cout<<"Exposure period set to: "<<exposure_period_in_sec<<endl;
|
||||
return 1;
|
||||
}
|
||||
float Eiger::GetExposurePeriod(){return exposure_period_in_sec;}
|
||||
|
||||
unsigned int Eiger::ConvertTimeToRegister(float time_in_sec){
|
||||
float n_clk_cycles = round(time_in_sec/10e-9); //200 MHz ctb clk or 100 MHz feb clk
|
||||
|
||||
unsigned int decoded_time;
|
||||
if(n_clk_cycles>(pow(2,29)-1)*pow(10,7)){
|
||||
float max_time = 10e-9*(pow(2,28)-1)*pow(10,7);
|
||||
cout<<"Warning: time exceeds ("<<time_in_sec<<") maximum exposure time of "<<max_time<<" sec."<<endl;
|
||||
cout<<"\t Setting to maximum "<<max_time<<" us."<<endl;
|
||||
decoded_time = 0xffffffff;
|
||||
}else{
|
||||
int power_of_ten = 0;
|
||||
while(n_clk_cycles>pow(2,29)-1){ power_of_ten++; n_clk_cycles = round(n_clk_cycles/10.0);}
|
||||
decoded_time = int(n_clk_cycles)<<3 | int(power_of_ten);
|
||||
}
|
||||
|
||||
return decoded_time;
|
||||
}
|
||||
|
||||
|
||||
bool Eiger::ResetDataStream(){
|
||||
//for(int i=0;i<10;i++) cout<<"Warning need to think about reseting data stream ...."<<endl;
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
||||
bool Eiger::ResetChipCompletely(){
|
||||
if(!SetCommandRegister(DAQ_RESET_COMPLETELY) || !StartDAQOnlyNWaitForFinish()){
|
||||
cout<<"Warning: could not ResetChipCompletely()."<<endl;
|
||||
return 0;
|
||||
}
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
||||
void Eiger::PrintAcquisitionSetup(){
|
||||
cout<<"Should print Acquisition here ..."<<endl;
|
||||
}
|
||||
|
||||
bool Eiger::StartAcquisition(){
|
||||
|
||||
static unsigned int reg_nums[20];
|
||||
static unsigned int reg_vals[20];
|
||||
|
||||
PrintAcquisitionSetup();
|
||||
|
||||
if(!Reset()||!ResetDataStream()){
|
||||
cout<<"Trouble reseting daq or data stream..."<<endl;
|
||||
return 0;
|
||||
}
|
||||
|
||||
if(!SetStaticBits(staticBits&(DAQ_STATIC_BIT_M4|DAQ_STATIC_BIT_M8))){
|
||||
cout<<"Trouble setting static bits ..."<<endl;
|
||||
return 0;
|
||||
}
|
||||
|
||||
if(!ResetChipCompletely()){
|
||||
cout<<"Trouble resetting chips ..."<<endl;
|
||||
return 0;
|
||||
}
|
||||
|
||||
reg_nums[0]=DAQ_REG_CTRL;
|
||||
reg_vals[0]=0;
|
||||
reg_nums[1]=DAQ_REG_NEXPOSURES;
|
||||
reg_vals[1]=nimages;
|
||||
reg_nums[2]=DAQ_REG_EXPOSURE_TIMER;
|
||||
reg_vals[2]=ConvertTimeToRegister(exposure_time_in_sec);
|
||||
reg_nums[3]=DAQ_REG_EXPOSURE_REPEAT_TIMER;
|
||||
reg_vals[3]=ConvertTimeToRegister(exposure_period_in_sec);
|
||||
reg_nums[4]=DAQ_REG_CHIP_CMDS;
|
||||
reg_vals[4]=(acquireNReadoutMode|triggerMode|externalEnableMode|subFrameMode);
|
||||
for(int i=5;i<19;i++){
|
||||
reg_nums[i]=DAQ_REG_CTRL;
|
||||
reg_vals[i]=0;
|
||||
}
|
||||
reg_nums[19]=DAQ_REG_CTRL;
|
||||
reg_vals[19]=ACQ_CTRL_START;
|
||||
|
||||
if(!WriteRegisters(0xfff,20,reg_nums,reg_vals)){
|
||||
cout<<"Trouble starting acquisition...."<<endl;
|
||||
return 0;
|
||||
}
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
bool Eiger::StopAcquisition(){
|
||||
return Reset();
|
||||
}
|
||||
|
||||
// bool PulsePixelNMove(int npulses, bool inc_x_pos=0, bool inc_y_pos=0);
|
||||
// int PulsePixel(int x, int y, int npulses);
|
||||
// int PulseChip(int npulses=1);
|
||||
|
||||
|
||||
|
||||
|
||||
174
slsDetectorSoftware/eigerDetectorServer/Eiger.h
Normal file
174
slsDetectorSoftware/eigerDetectorServer/Eiger.h
Normal file
@ -0,0 +1,174 @@
|
||||
|
||||
/**
|
||||
* @author Ian Johnson
|
||||
* @version 1.0
|
||||
*/
|
||||
|
||||
|
||||
#ifndef EIGER_H
|
||||
#define EIGER_H
|
||||
|
||||
#include <string.h>
|
||||
#include <vector>
|
||||
|
||||
#include "Feb.h"
|
||||
|
||||
|
||||
class Module{
|
||||
|
||||
private:
|
||||
unsigned int module_number;
|
||||
bool top_address_valid;
|
||||
unsigned int top_left_address;
|
||||
unsigned int top_right_address;
|
||||
bool bottom_address_valid;
|
||||
unsigned int bottom_left_address;
|
||||
unsigned int bottom_right_address;
|
||||
|
||||
unsigned int idelay_top[4]; //ll,lr,rl,ll
|
||||
unsigned int idelay_bottom[4]; //ll,lr,rl,ll
|
||||
float high_voltage;
|
||||
float* top_dac;
|
||||
float* bottom_dac;
|
||||
|
||||
public:
|
||||
Module(unsigned int number, unsigned int address_top); //for half module()
|
||||
Module(unsigned int number, unsigned int address_top, unsigned int address_bottom);
|
||||
~Module();
|
||||
|
||||
static const unsigned int ndacs;
|
||||
static const std::string dac_names[16];
|
||||
|
||||
unsigned int GetModuleNumber() {return module_number;}
|
||||
bool TopAddressIsValid() {return top_address_valid;}
|
||||
unsigned int GetTopBaseAddress() {return (top_left_address&0xff);}
|
||||
unsigned int GetTopLeftAddress() {return top_left_address;}
|
||||
unsigned int GetTopRightAddress() {return top_right_address;}
|
||||
unsigned int GetBottomBaseAddress() {return (bottom_left_address&0xff);}
|
||||
bool BottomAddressIsValid() {return bottom_address_valid;}
|
||||
unsigned int GetBottomLeftAddress() {return bottom_left_address;}
|
||||
unsigned int GetBottomRightAddress() {return bottom_right_address;}
|
||||
|
||||
unsigned int SetTopIDelay(unsigned int chip,unsigned int value) { return TopAddressIsValid() &&chip<4 ? (idelay_top[chip]=value) : 0;} //chip 0=ll,1=lr,0=rl,1=rr
|
||||
unsigned int GetTopIDelay(unsigned int chip) { return chip<4 ? idelay_top[chip] : 0;} //chip 0=ll,1=lr,0=rl,1=rr
|
||||
unsigned int SetBottomIDelay(unsigned int chip,unsigned int value) { return BottomAddressIsValid() &&chip<4 ? (idelay_bottom[chip]=value) : 0;} //chip 0=ll,1=lr,0=rl,1=rr
|
||||
unsigned int GetBottomIDelay(unsigned int chip) { return chip<4 ? idelay_bottom[chip] : 0;} //chip 0=ll,1=lr,0=rl,1=rr
|
||||
|
||||
float SetHighVoltage(float value) { return TopAddressIsValid() ? (high_voltage=value) : -1;}
|
||||
float GetHighVoltage() { return high_voltage;}
|
||||
|
||||
float SetTopDACVoltage(unsigned int i, float value) { return (i<ndacs && TopAddressIsValid()) ? (top_dac[i]=value) : -1;}
|
||||
float GetTopDACVoltage(unsigned int i) { return (i<ndacs) ? top_dac[i]:-1;}
|
||||
float SetBottomDACVoltage(unsigned int i, float value) { return (i<ndacs && BottomAddressIsValid()) ? (bottom_dac[i]=value) : -1;}
|
||||
float GetBottomDACVoltage(unsigned int i) { return (i<ndacs) ? bottom_dac[i]:-1;}
|
||||
|
||||
};
|
||||
|
||||
|
||||
|
||||
class Eiger:private Feb{
|
||||
|
||||
private:
|
||||
|
||||
std::vector<Module*> modules;
|
||||
|
||||
unsigned int staticBits; //program=1,m4=2,m8=4,test=8,rotest=16,cs_bar_left=32,cs_bar_right=64
|
||||
unsigned int acquireNReadoutMode; //safe or parallel, half or full speed
|
||||
unsigned int triggerMode; //internal timer, external start, external window, signal polarity (external trigger and enable)
|
||||
unsigned int externalEnableMode; //external enabling engaged and it's polarity
|
||||
unsigned int subFrameMode;
|
||||
|
||||
unsigned int photon_energy_eV;
|
||||
|
||||
unsigned int nimages;
|
||||
float exposure_time_in_sec;
|
||||
float exposure_period_in_sec;
|
||||
|
||||
unsigned int trimbit_size;
|
||||
unsigned char* last_downloaded_trimbits;
|
||||
|
||||
void PrintModuleList();
|
||||
bool GetModuleIndex(unsigned int module_number, unsigned int& module_index);
|
||||
bool CheckModuleAddresses(unsigned int top_address, unsigned int bottom_address);
|
||||
bool AddModule(unsigned int module_number, unsigned int top_address);
|
||||
bool AddModule(unsigned int module_number, unsigned int top_address, unsigned int bottom_address, bool half_module=0);
|
||||
|
||||
bool GetDACNumber(std::string s, unsigned int& n);
|
||||
bool SendDACValue(unsigned int dst_num, unsigned int ch, float& value);
|
||||
bool VoltageToDAC(float value, unsigned int& digital, unsigned int nsteps, float vmin, float vmax);
|
||||
float DACToVoltage(unsigned int digital,unsigned int nsteps,float vmin,float vmax);
|
||||
|
||||
bool SendHighVoltage(unsigned int module_index, float& value);
|
||||
|
||||
bool SendIDelays(unsigned int dst_num, bool chip_lr, unsigned int channels, unsigned int ndelay_units);
|
||||
|
||||
bool SetStaticBits();
|
||||
bool SetStaticBits(unsigned int the_static_bits);
|
||||
|
||||
unsigned int ConvertTimeToRegister(float time_in_sec);
|
||||
|
||||
bool SetCommandRegister(unsigned int cmd);
|
||||
bool GetDAQStatusRegister(int socket_num, unsigned int &ret_status);
|
||||
bool StartDAQOnlyNWaitForFinish(int sleep_time_us=5000);
|
||||
bool ResetDataStream();
|
||||
|
||||
bool ResetChipCompletely();
|
||||
|
||||
public:
|
||||
Eiger();
|
||||
virtual ~Eiger();
|
||||
|
||||
bool Init();
|
||||
bool ReadSetUpFileToAddModules(std::string file_name);
|
||||
bool ReadSetUpFile(unsigned int module_num, std::string file_name);
|
||||
bool CheckSetup();
|
||||
|
||||
//bool SetHighVoltage(float value);
|
||||
bool SetHighVoltage(unsigned int module_num,float value);
|
||||
|
||||
bool SetPhotonEnergy(unsigned int full_energy_meV);
|
||||
unsigned int GetPhotonEnergy(){return photon_energy_eV;}
|
||||
|
||||
bool SetIDelays(unsigned int module_num, unsigned int ndelay_units);
|
||||
bool SetIDelays(unsigned int module_num, unsigned int chip_pos, unsigned int ndelay_units);
|
||||
|
||||
bool SetDAC(std::string s, float value);
|
||||
bool GetDAC(std::string s, float& ret_value);
|
||||
|
||||
bool SetTrimbits(unsigned char* trimbits);
|
||||
unsigned char* GetTrimbits();
|
||||
|
||||
|
||||
|
||||
bool Reset();
|
||||
bool StartAcquisition();
|
||||
bool StopAcquisition();
|
||||
bool AcquisitionInProgress();
|
||||
bool WaitForFinishedFlag(int sleep_time_us=5000);
|
||||
|
||||
//functions for setting up exposure
|
||||
void PrintAcquisitionSetup();
|
||||
bool SetNImages(unsigned int n_images);
|
||||
unsigned int GetNImages();
|
||||
bool SetExposureTime(float the_exposure_time_in_sec);
|
||||
float GetExposureTime();
|
||||
bool SetExposurePeriod(float the_exposure_period_in_sec);
|
||||
float GetExposurePeriod();
|
||||
bool SetDynamicRange(unsigned int four_eight_sixteen_or_thirtytwo);
|
||||
unsigned int GetDynamicRange();
|
||||
bool SetReadoutSpeed(unsigned int readout_speed=0); //0->full,1->half,2->quarter or 3->super_slow
|
||||
bool SetReadoutMode(unsigned int readout_mode=0); //0->parallel,1->non-parallel,2-> safe_mode
|
||||
bool SetTriggerMode(unsigned int trigger_mode=0, bool polarity=1);
|
||||
bool SetExternalEnableMode(bool use_external_enable=0, bool polarity=1);
|
||||
|
||||
|
||||
//functions for testing
|
||||
bool SetTestModeVariable(bool on=1);
|
||||
bool GetTestModeVariable();
|
||||
|
||||
bool FebTest(){return Feb::Test();}
|
||||
|
||||
};
|
||||
|
||||
|
||||
#endif
|
||||
111
slsDetectorSoftware/eigerDetectorServer/EigerRegisterDefs.h
Normal file
111
slsDetectorSoftware/eigerDetectorServer/EigerRegisterDefs.h
Normal file
@ -0,0 +1,111 @@
|
||||
|
||||
/**
|
||||
* @author Ian Johnson
|
||||
* @version 1.0
|
||||
*/
|
||||
|
||||
|
||||
//daq register definitions
|
||||
#define DAQ_REG_CTRL 1
|
||||
#define DAQ_REG_CHIP_CMDS 2
|
||||
#define DAQ_REG_STATIC_BITS 3
|
||||
#define DAQ_REG_CLK_ROW_CLK_NTIMES 3
|
||||
#define DAQ_REG_SHIFT_IN_32 3
|
||||
#define DAQ_REG_READOUT_NROWS 3
|
||||
#define DAQ_REG_SEND_N_TESTPULSES 3
|
||||
|
||||
#define DAQ_REG_NEXPOSURES 3
|
||||
#define DAQ_REG_EXPOSURE_TIMER 4 // == (31 downto 3) * 10^(2 downto 0)
|
||||
#define DAQ_REG_EXPOSURE_REPEAT_TIMER 5 // == (31 downto 3) * 10^(2 downto 0)
|
||||
#define DAQ_REG_STATUS 6 //also pg and fifo status register
|
||||
|
||||
#define DAQ_CTRL_RESET 0x80000000
|
||||
#define DAQ_CTRL_START 0x40000000
|
||||
#define ACQ_CTRL_START 0x50000000 //this is 0x10000000 (acq) | 0x40000000 (daq)
|
||||
#define DAQ_CTRL_STOP 0x00000000
|
||||
|
||||
//direct chip commands to the DAQ_REG_CHIP_CMDS register
|
||||
#define DAQ_SET_STATIC_BIT 0x00000001
|
||||
#define DAQ_RESET_COMPLETELY 0x0000000E
|
||||
#define DAQ_RESET_PERIPHERY 0x00000002
|
||||
#define DAQ_RESET_PIXEL_COUNTERS 0x00000004
|
||||
#define DAQ_RESET_COLUMN_SELECT 0x00000008
|
||||
|
||||
#define DAQ_STORE_IMAGE 0x00000010
|
||||
#define DAQ_RELEASE_IMAGE_STORE 0x00000020
|
||||
|
||||
#define DAQ_SEND_A_TOKEN_IN 0x00000040
|
||||
#define DAQ_CLK_ROW_CLK_NTIMES 0x00000080
|
||||
#define DAQ_SERIALIN_SHIFT_IN_32 0x00000100
|
||||
#define DAQ_LOAD_16ROWS_OF_TRIMBITS 0x00000200
|
||||
|
||||
#define DAQ_IGNORE_INITIAL_CRAP 0x00000400 //crap before readout
|
||||
#define DAQ_READOUT_NROWS 0x00000800
|
||||
#define DAQ_CLKOUT_LAST_4_BITS_AND_RETURN_TO_START 0x00001000 //last 4 bit of data in the last frame
|
||||
|
||||
#define DAQ_RELEASE_IMAGE_STORE_AFTER_READOUT 0x00002000
|
||||
#define DAQ_RESET_PIXEL_COUNTERS_AFTER_READOUT 0x00004000
|
||||
|
||||
#define DAQ_CLK_ROW_CLK_TO_SELECT_NEXT_ROW 0x00008000
|
||||
#define DAQ_CLK_MAIN_CLK_TO_SELECT_NEXT_PIXEL 0x00010000
|
||||
#define DAQ_SEND_N_TEST_PULSES 0x00020000
|
||||
|
||||
#define DAQ_CHIP_CONTROLLER_HALF_SPEED 0x00040000 //everything at 100 MHz (50MHz ddr readout)
|
||||
#define DAQ_CHIP_CONTROLLER_QUARTER_SPEED 0x00080000 //everything at 50 MHz (25MHz ddr readout)
|
||||
#define DAQ_CHIP_CONTROLLER_SUPER_SLOW_SPEED 0x000c0000 //everything at ~200 kHz (200 kHz MHz ddr readout)
|
||||
|
||||
#define DAQ_FIFO_ENABLE 0x00100000
|
||||
|
||||
//direct chip commands to the DAQ_REG_CHIP_CMDS register
|
||||
#define DAQ_NEXPOSURERS_SAFEST_MODE_ROW_CLK_BEFORE_MODE 0x00200000 //row clk is before main clk readout sequence
|
||||
#define DAQ_NEXPOSURERS_NORMAL_NONPARALLEL_MODE 0x00400000 //expose ->readout ->expose -> ..., with store is always closed
|
||||
#define DAQ_NEXPOSURERS_PARALLEL_MODE 0x00600000 //parallel acquire/read mode
|
||||
|
||||
//DAQ_NEXPOSURERS_READOUT_COMPLETE_IMAGES is old now hard-wired in the firmware that every image comes with a header
|
||||
//#define DAQ_NEXPOSURERS_READOUT_COMPLETE_IMAGES 0x00800000 //DAQ_IGNORE_INITIAL_CRAP and DAQ_CLKOUT_LAST_4_BITS_AND_RETURN_TO_START
|
||||
|
||||
#define DAQ_NEXPOSURERS_EXTERNAL_ENABLING 0x01000000
|
||||
#define DAQ_NEXPOSURERS_EXTERNAL_ENABLING_POLARITY 0x02000000
|
||||
#define DAQ_NEXPOSURERS_EXTERNAL_TRIGGER_POLARITY 0x04000000
|
||||
|
||||
#define DAQ_NEXPOSURERS_INTERNAL_ACQUISITION 0x00000000 //internally controlled
|
||||
#define DAQ_NEXPOSURERS_EXTERNAL_ACQUISITION_START 0x08000000 //external acquisition start
|
||||
#define DAQ_NEXPOSURERS_EXTERNAL_IMAGE_START 0x10000000 //external image start
|
||||
#define DAQ_NEXPOSURERS_EXTERNAL_IMAGE_START_AND_STOP 0x18000000 //externally controlly, external image start and stop
|
||||
|
||||
#define DAQ_NEXPOSURERS_ACTIVATE_AUTO_SUBIMAGING 0x20000000
|
||||
#define DAQ_NEXPOSURERS_ACTIVATE_RATE_CORRECTION 0x40000000
|
||||
|
||||
//#define DAQ_MASTER_HALF_MODULE 0x80000000 currently not used
|
||||
|
||||
|
||||
//chips static bits
|
||||
#define DAQ_STATIC_BIT_PROGRAM 0x00000001
|
||||
#define DAQ_STATIC_BIT_M4 0x00000002 //these are the status bits, not bit mode
|
||||
#define DAQ_STATIC_BIT_M8 0x00000004 //these are the status bits, not bit mode
|
||||
#define DAQ_STATIC_BIT_M12 0x00000000 //these are the status bits, not bit mode, ie. "00" is 12 bit mode
|
||||
#define DAQ_STATIC_BIT_CHIP_TEST 0x00000008
|
||||
#define DAQ_STATIC_BIT_ROTEST 0x00000010
|
||||
#define DAQ_CS_BAR_LEFT 0x00000020
|
||||
#define DAQ_CS_BAR_RIGHT 0x00000040
|
||||
|
||||
|
||||
//status flags
|
||||
#define DAQ_STATUS_DAQ_RUNNING 0x01
|
||||
#define DAQ_DATA_COLLISION_ERROR 0x02
|
||||
|
||||
#define DAQ_STATUS_CURRENT_M4 0x04
|
||||
#define DAQ_STATUS_CURRENT_M8 0x08
|
||||
#define DAQ_STATUS_CURRENT_M12 0x00 //in 12 bit mode both are cleared
|
||||
#define DAQ_STATUS_CURRENT_TESTMODE 0x10
|
||||
#define DAQ_STATUS_TOKEN_OUT 0x20
|
||||
#define DAQ_STATUS_SERIAL_OUT 0x40
|
||||
#define DAQ_STATUS_PIXELS_ARE_ENABLED 0x80
|
||||
|
||||
|
||||
//data delay registers
|
||||
#define CHIP_DATA_OUT_DELAY_REG_CTRL 1
|
||||
#define CHIP_DATA_OUT_DELAY_REG2 2
|
||||
#define CHIP_DATA_OUT_DELAY_REG3 3
|
||||
#define CHIP_DATA_OUT_DELAY_REG4 4
|
||||
#define CHIP_DATA_OUT_DELAY_SET 0x20000000
|
||||
38
slsDetectorSoftware/eigerDetectorServer/EigerTest.cxx
Normal file
38
slsDetectorSoftware/eigerDetectorServer/EigerTest.cxx
Normal file
@ -0,0 +1,38 @@
|
||||
|
||||
/**
|
||||
* @author Ian Johnson
|
||||
* @version 1.0
|
||||
*/
|
||||
|
||||
|
||||
#include <iostream>
|
||||
#include <stdio.h>
|
||||
|
||||
#include <stdlib.h>
|
||||
|
||||
#include "Eiger.h"
|
||||
|
||||
|
||||
using namespace std;
|
||||
|
||||
int main(int argc, char* argv[]){
|
||||
|
||||
cout<<"\n\n\n\n\n\n\n\n\n\n"<<endl;
|
||||
int n = (argc>1) ? atoi(argv[1]):5;
|
||||
|
||||
//Feb *f = new Feb();
|
||||
// f->Test();
|
||||
//delete f;
|
||||
//return 0;
|
||||
|
||||
Eiger* e = new Eiger();
|
||||
e->SetNImages(n);
|
||||
e->SetDynamicRange(32);
|
||||
e->SetExposureTime(0.02);
|
||||
e->SetExposurePeriod(0.050);
|
||||
e->StartAcquisition();
|
||||
|
||||
delete e;
|
||||
|
||||
return 0;
|
||||
}
|
||||
326
slsDetectorSoftware/eigerDetectorServer/Feb.cxx
Normal file
326
slsDetectorSoftware/eigerDetectorServer/Feb.cxx
Normal file
@ -0,0 +1,326 @@
|
||||
|
||||
/**
|
||||
* @author Ian Johnson
|
||||
* @version 1.0
|
||||
*/
|
||||
|
||||
|
||||
//return reversed 1 means good, 0 means failed
|
||||
|
||||
|
||||
#include <iostream>
|
||||
#include <iomanip>
|
||||
//#include <unistd.h>
|
||||
//#include <string.h>
|
||||
//#include <sys/mman.h>
|
||||
//#include <fcntl.h>
|
||||
|
||||
#include "xparameters.h"
|
||||
|
||||
#include "Feb.h"
|
||||
|
||||
using namespace std;
|
||||
|
||||
Feb::Feb(){
|
||||
|
||||
nfebs = 0;
|
||||
feb_numb = 0;
|
||||
|
||||
send_ndata = 0;
|
||||
send_buffer_size = 1026;
|
||||
send_data_raw = new unsigned int [send_buffer_size+1];
|
||||
send_data = &send_data_raw[1];
|
||||
|
||||
recv_ndata = 0;
|
||||
recv_buffer_size = 1026;
|
||||
recv_data_raw = new unsigned int [recv_buffer_size+1];
|
||||
recv_data = &recv_data_raw[1];
|
||||
|
||||
ll = new LocalLinkInterface(XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_RIGHT_BASEADDR);
|
||||
|
||||
}
|
||||
|
||||
Feb::~Feb(){
|
||||
delete ll;
|
||||
if(feb_numb) delete [] feb_numb;
|
||||
delete [] send_data_raw;
|
||||
delete [] recv_data_raw;
|
||||
}
|
||||
|
||||
void Feb::SendCompleteFebList(unsigned int n,unsigned int* list){
|
||||
if(feb_numb) delete [] feb_numb;
|
||||
nfebs = n;
|
||||
feb_numb = new unsigned int [n];
|
||||
for(unsigned int i=0;i<n;i++) feb_numb[i] = list[i];
|
||||
}
|
||||
|
||||
bool Feb::WriteTo(unsigned int ch){
|
||||
if(ch>0xfff) return 0;
|
||||
|
||||
send_data_raw[0] = 0x90000000 | (ch<<16); //we
|
||||
if(ll->Write(4,send_data_raw)!=4) return 0;
|
||||
|
||||
send_data_raw[0] = 0xc0000000; //data
|
||||
return ((send_ndata+1)*4==ll->Write((send_ndata+1)*4,send_data_raw));
|
||||
}
|
||||
|
||||
bool Feb::ReadFrom(unsigned int ch, unsigned int ntrys){
|
||||
if(ch>=0xfff) return 0;
|
||||
|
||||
recv_data_raw[0] = 0xa0000000 | (ch<<16); //read data
|
||||
ll->Write(4,recv_data_raw);
|
||||
usleep(20);
|
||||
|
||||
recv_ndata=-1;
|
||||
for(unsigned int t=0;t<ntrys;t++){
|
||||
if((recv_ndata=ll->Read(recv_buffer_size*4,recv_data_raw)/4)>0){
|
||||
recv_ndata--;
|
||||
break;
|
||||
}
|
||||
cout<<"\t Read try number: "<<t<<endl;
|
||||
usleep(1000);
|
||||
}
|
||||
|
||||
return (recv_ndata>=0);
|
||||
}
|
||||
|
||||
void Feb::PrintData(){
|
||||
cout<<"Sent data: "<<send_ndata<<endl;
|
||||
for(int i=0;i<send_ndata;i++) cout<<"\t"<<i<<")"<<setw(14)<<send_data[i]<<" ("<<hex<<send_data[i]<<")"<<dec<<endl;
|
||||
cout<<"Receive data: "<<recv_ndata<<endl;
|
||||
for(int i=0;i<recv_ndata;i++) cout<<"\t"<<i<<")"<<setw(14)<<recv_data[i]<<" ("<<hex<<recv_data[i]<<")"<<dec<<endl;
|
||||
cout<<endl<<endl;
|
||||
}
|
||||
|
||||
|
||||
bool Feb::CheckHeader(unsigned int valid_bit_mask, bool print_error_info){
|
||||
|
||||
bool header_returned_is_ok = (send_data[0] & valid_bit_mask)==(recv_data[0] & valid_bit_mask);
|
||||
|
||||
if(print_error_info && !header_returned_is_ok){
|
||||
cout<<"Error: Command received not the same as command recieved."<<endl;
|
||||
cout<<"\t\t Header sent: "<<dec<<send_data[0]<<" ("<<hex<<send_data[0]<<") recieved: "<<dec<<recv_data[0]<<" ("<<hex<<recv_data[0]<<")"<<dec<<endl;
|
||||
if(send_ndata>1&&recv_ndata>1){
|
||||
cout<<"\t\t Tail sent: "<<dec<<send_data[send_ndata-1]<<" ("<<hex<<send_data[send_ndata-1]<<") recieved: "<<dec<<recv_data[recv_ndata-1]<<" ("<<hex<<recv_data[recv_ndata-1]<<")"<<dec<<endl;
|
||||
}else{
|
||||
cout<<"Error printing tail, too little data nsent = "<<send_ndata<<", nrecv = "<<recv_ndata<<"."<<endl;
|
||||
}
|
||||
PrintData();
|
||||
}
|
||||
return header_returned_is_ok;
|
||||
}
|
||||
|
||||
|
||||
bool Feb::CheckTail(unsigned int valid_bit_mask){
|
||||
if(send_ndata<=1&&recv_ndata<=1){
|
||||
cout<<"Error checking tail, too little data nsent = "<<send_ndata<<", nrecv = "<<recv_ndata<<"."<<endl;
|
||||
return 0;
|
||||
}
|
||||
|
||||
unsigned int the_tail = recv_data[recv_ndata-1]&valid_bit_mask;
|
||||
if(the_tail!=0){
|
||||
cout<<"Error returned in tail: "<<hex<<the_tail<<" "<<dec<<"("<<the_tail<<")"<<endl;
|
||||
if(the_tail&0x10000000) cout<<"\t\tBusy flag address error."<<endl;
|
||||
if(the_tail&0x20000000) cout<<"\t\tRead register address error."<<endl;
|
||||
if(the_tail&0x40000000) cout<<"\t\tWrite register address error."<<endl;
|
||||
if(the_tail&0x80000000) cout<<"\t\tBram number error."<<endl;
|
||||
if(the_tail&0x08000000) cout<<"\t\tFifo to read from error."<<endl;
|
||||
if(the_tail&0x3ff) cout<<"\t\tNumber of data send error."<<endl;
|
||||
return 0; //error
|
||||
}
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
||||
bool Feb::CheckCommunication(){
|
||||
send_data_raw[0] = 0x8fff0000; //rst-all serial coms and lls
|
||||
if(ll->Write(4,send_data_raw)!=4) return 0;
|
||||
|
||||
cout<<"Feb::CheckingCommunication ...."<<endl;
|
||||
while((ll->Read(recv_buffer_size*4,recv_data_raw)/4)>0) cout<<"\t) Cleanning buffer ..."<<endl;
|
||||
|
||||
return SetByteOrder();
|
||||
}
|
||||
|
||||
|
||||
bool Feb::SetByteOrder(){
|
||||
|
||||
send_ndata = 2;
|
||||
send_data[0] = 0; //header
|
||||
send_data[1] = 0; //tail
|
||||
|
||||
unsigned int dst = 0xff;
|
||||
for(unsigned int i=0;i<nfebs;i++) dst = (dst | feb_numb[i]); //get sub dst bits (left right in this case)
|
||||
bool passed = WriteTo(dst);
|
||||
|
||||
for(unsigned int i=0;i<nfebs;i++){
|
||||
cout<<"\t"<<i<<") Set Byte Order .............. ";
|
||||
unsigned int current_passed = ReadFrom(feb_numb[i])&&(recv_ndata==2)&&CheckHeader();
|
||||
if(current_passed) cout<<"passed."<<endl;
|
||||
else cout<<"failed."<<endl;
|
||||
passed&=current_passed;
|
||||
}
|
||||
cout<<endl;
|
||||
|
||||
return passed;
|
||||
}
|
||||
|
||||
/*
|
||||
bool Feb::CheckSubNumber(unsigned int sub_num){
|
||||
if(sub_num>=nfebs){
|
||||
cout<<"Error invalid sub number "<<sub_num<<" must be less than "<<nfebs<<"."<<endl;
|
||||
return 0;
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
bool Feb::SetStartOnEndOnFebs(int sub_num_s, unsigned int& start_on, unsigned int& end_on){
|
||||
// -1 means write to all
|
||||
|
||||
if(sub_num_s<=-2){
|
||||
cout<<"Error bad subnumber "<<sub_num_s<<"."<<endl;
|
||||
return 0;
|
||||
}
|
||||
|
||||
start_on = sub_num_s!=-1 ? sub_num_s : 0;
|
||||
end_on = sub_num_s!=-1 ? sub_num_s : nfebs - 1;
|
||||
|
||||
return CheckSubNumber(start_on);
|
||||
}
|
||||
*/
|
||||
|
||||
bool Feb::ReadRegister(unsigned int sub_num, unsigned int reg_num,unsigned int& value_read){
|
||||
return ReadRegisters(sub_num,1,®_num,&value_read);
|
||||
}
|
||||
|
||||
|
||||
bool Feb::ReadRegisters(unsigned int sub_num, unsigned int nreads, unsigned int* reg_nums,unsigned int* values_read){
|
||||
//here cout<<"Reading Register ...."<<endl;
|
||||
|
||||
nreads &= 0x3ff; //10 bits
|
||||
if(!nreads||nreads>send_buffer_size-2) return 0;
|
||||
|
||||
send_ndata = nreads+2;
|
||||
send_data[0] = 0x20000000 | nreads << 14; //cmd -> read "00" , nreads
|
||||
|
||||
for(unsigned int i=0;i<nreads;i++) send_data[i+1]=reg_nums[i];
|
||||
send_data[nreads+1] = 0; //tail
|
||||
|
||||
if(!WriteTo(sub_num)||!ReadFrom(sub_num)||recv_ndata!=int(nreads+2)||!CheckHeader()||!CheckTail()){
|
||||
PrintData();
|
||||
cout<<"Error reading register."<<endl;
|
||||
return 0;
|
||||
}
|
||||
|
||||
for(unsigned int i=0;i<nreads;i++) values_read[i] = recv_data[i+1];
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
bool Feb::WriteRegister(unsigned int sub_num, unsigned int reg_num,unsigned int value, bool wait_on, unsigned int wait_on_address){
|
||||
return WriteRegisters(sub_num,1,®_num,&value,&wait_on,&wait_on_address);
|
||||
}
|
||||
|
||||
bool Feb::WriteRegisters(unsigned int sub_num, unsigned int nwrites, unsigned int* reg_nums, unsigned int* values, bool* wait_ons, unsigned int* wait_on_addresses){
|
||||
|
||||
// sub_num == 0xfff means write to all
|
||||
|
||||
nwrites &= 0x3ff; //10 bits
|
||||
if(!nwrites||nwrites>send_buffer_size-2) return 0;
|
||||
|
||||
//cout<<"Write register : "<<this<<" "<<s_num<<" "<<nwrites<<" "<<reg_nums<<" "<<values<<" "<<wait_ons<<" "<<wait_on_addresses<<endl;
|
||||
send_ndata = 2*nwrites+2;
|
||||
send_data[0] = 0x80000000 | nwrites << 14; //cmd -> write nwrites and how many
|
||||
send_data[2*nwrites+1] = 0; //tail
|
||||
|
||||
for(unsigned int i=0;i<nwrites;i++) send_data[2*i+1] = 0x3fff®_nums[i]; // register address data_in(13 downto 0)
|
||||
for(unsigned int i=0;i<nwrites;i++) send_data[2*i+2] = values[i]; // value is data_in(31 downto 0)
|
||||
// wait on busy data(28), address of busy flag data(27 downto 14)
|
||||
if(wait_ons&&wait_on_addresses) for(unsigned int i=0;i<nwrites;i++) send_data[2*i+1] |= (wait_ons[i]<<28 | (0x3fff&wait_on_addresses[i])<<14);
|
||||
|
||||
if(!WriteTo(sub_num)){
|
||||
cout<<sub_num<<") Error writing register(s)."<<endl;
|
||||
PrintData();
|
||||
return 0;
|
||||
}
|
||||
|
||||
bool passed = 1;
|
||||
unsigned int n = (sub_num&0xff)==0xff ? nfebs : 1;
|
||||
unsigned int* nums = (sub_num&0xff)==0xff ? feb_numb : &sub_num;
|
||||
for(unsigned int i=0;i<n;i++){
|
||||
if((sub_num&0xf00&(nums[i]))==0) continue;
|
||||
if(!ReadFrom(nums[i])||recv_ndata!=2||!CheckHeader()){
|
||||
cout<<nums[i]<<") Error writing register(s) response."<<endl;
|
||||
PrintData();
|
||||
passed = 0;
|
||||
}else{
|
||||
passed = passed && CheckTail();
|
||||
}
|
||||
}
|
||||
|
||||
return passed;
|
||||
}
|
||||
|
||||
|
||||
bool Feb::WriteMemory(unsigned int sub_num, unsigned int mem_num, unsigned int start_address, unsigned int nwrites, unsigned int *values){
|
||||
// -1 means write to all
|
||||
|
||||
mem_num &= 0x3f; //6 bits
|
||||
start_address &= 0x3fff; //14 bits
|
||||
nwrites &= 0x3ff; //10 bits
|
||||
if(!nwrites||nwrites>send_buffer_size-2) return 0;
|
||||
|
||||
send_ndata = nwrites+2;
|
||||
send_data[0] = 0xc0000000 | mem_num << 24 | nwrites << 14 | start_address; //cmd -> write to memory, nwrites, mem number, start address
|
||||
send_data[nwrites+1] = 0; //tail
|
||||
for(unsigned int i=0;i<nwrites;i++) send_data[i+1] = values[i];
|
||||
|
||||
|
||||
if(!WriteTo(sub_num)){
|
||||
cout<<sub_num<<") Error writing memory."<<endl;
|
||||
return 0;
|
||||
}
|
||||
|
||||
bool passed = 1;
|
||||
unsigned int n = (sub_num&0xff)==0xff ? nfebs : 1;
|
||||
unsigned int* nums = (sub_num&0xff)==0xff ? feb_numb : &sub_num;
|
||||
for(unsigned int i=0;i<n;i++){
|
||||
if((sub_num&0xf00&(nums[i]))==0) continue;
|
||||
if(!ReadFrom(nums[i])||recv_ndata!=2||!CheckHeader()){
|
||||
cout<<nums[i]<<") Error writing memory response."<<endl;
|
||||
PrintData();
|
||||
passed = 0;
|
||||
}else{
|
||||
passed = passed && CheckTail();
|
||||
}
|
||||
}
|
||||
// unsigned int n = sub_num==0xfff ? nfebs : 1;
|
||||
// unsigned int* nums = sub_num==0xfff ? feb_numb : &sub_num;
|
||||
// for(unsigned int i=0;i<n;i++){
|
||||
|
||||
return passed;
|
||||
}
|
||||
|
||||
|
||||
|
||||
bool Feb::Test(){//int sub_num_s, unsigned int mem_num, unsigned int start_address, unsigned int nwrites, unsigned int *values){
|
||||
// -1 means write to all
|
||||
|
||||
unsigned int reg_nums[10]={0,1,2,3,1,2,3,1,2,3};
|
||||
|
||||
cout<<"Test"<<endl<<endl<<endl<<endl;
|
||||
|
||||
unsigned int value = 0;
|
||||
for(unsigned int i=0;i<10;i++){
|
||||
WriteRegister(0xfff,reg_nums[i%10],i);
|
||||
ReadRegister(256,reg_nums[i%10],value);
|
||||
cout<<i<<" "<<value<<endl;
|
||||
ReadRegister(512,reg_nums[i%10],value);
|
||||
cout<<i<<" "<<value<<endl;
|
||||
WriteMemory(0xfff,0,0,10,reg_nums);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
62
slsDetectorSoftware/eigerDetectorServer/Feb.h
Normal file
62
slsDetectorSoftware/eigerDetectorServer/Feb.h
Normal file
@ -0,0 +1,62 @@
|
||||
|
||||
/**
|
||||
* @author Ian Johnson
|
||||
* @version 1.0
|
||||
*/
|
||||
|
||||
|
||||
#ifndef FEB_H
|
||||
#define FEB_H
|
||||
|
||||
#include "LocalLinkInterface.h"
|
||||
|
||||
class Feb{ //
|
||||
|
||||
private:
|
||||
LocalLinkInterface* ll;
|
||||
|
||||
unsigned int nfebs;
|
||||
unsigned int* feb_numb;
|
||||
|
||||
int send_ndata;
|
||||
unsigned int send_buffer_size;
|
||||
unsigned int* send_data_raw;
|
||||
unsigned int* send_data;
|
||||
|
||||
int recv_ndata;
|
||||
unsigned int recv_buffer_size;
|
||||
unsigned int* recv_data_raw;
|
||||
unsigned int* recv_data;
|
||||
|
||||
bool WriteTo(unsigned int ch);
|
||||
bool ReadFrom(unsigned int ch, unsigned int ntrys=20);
|
||||
bool CheckHeader(unsigned int valid_bit_mask=0xffffffff, bool print_error_info=1);
|
||||
bool CheckTail(unsigned int valid_bit_mask=0xffffffff);
|
||||
|
||||
|
||||
bool SetByteOrder();
|
||||
//bool CheckSubNumber(unsigned int sub_num);
|
||||
//bool SetStartOnEndOnFebs(int sub_num_s, unsigned int& start_on, unsigned int& end_on);
|
||||
void PrintData();
|
||||
|
||||
public:
|
||||
Feb();
|
||||
virtual ~Feb();
|
||||
|
||||
void SendCompleteFebList(unsigned int n,unsigned int* list);
|
||||
bool CheckCommunication();
|
||||
|
||||
bool ReadRegister(unsigned int sub_num, unsigned int reg_num,unsigned int& value_read);
|
||||
bool ReadRegisters(unsigned int sub_num, unsigned int nreads, unsigned int* reg_nums,unsigned int* values_read);
|
||||
|
||||
bool WriteRegister(unsigned int sub_num, unsigned int reg_num,unsigned int value, bool wait_on=0, unsigned int wait_on_address=0);
|
||||
bool WriteRegisters(unsigned int sub_num, unsigned int nwrites, unsigned int* reg_nums, unsigned int* values, bool* wait_ons=0, unsigned int* wait_on_addresses=0);
|
||||
|
||||
bool WriteMemory(unsigned int sub_num, unsigned int mem_num, unsigned int start_address, unsigned int nwrites, unsigned int *values);
|
||||
|
||||
bool Test();
|
||||
|
||||
};
|
||||
|
||||
|
||||
#endif
|
||||
87
slsDetectorSoftware/eigerDetectorServer/HardwareIO.cxx
Normal file
87
slsDetectorSoftware/eigerDetectorServer/HardwareIO.cxx
Normal file
@ -0,0 +1,87 @@
|
||||
|
||||
//Class initially from Gerd and was called mmap_test.c
|
||||
//return reversed 1 means good, 0 means failed
|
||||
|
||||
|
||||
//#include <stdio.h>
|
||||
//#include <unistd.h>
|
||||
//#include <string.h>
|
||||
//#include <sys/mman.h>
|
||||
//#include <fcntl.h>
|
||||
|
||||
#include "HardwareIO.h"
|
||||
|
||||
xfs_u8 HardwareIO::xfs_in8(xfs_u32 InAddress)
|
||||
{
|
||||
/* read the contents of the I/O location and then synchronize the I/O
|
||||
* such that the I/O operation completes before proceeding on
|
||||
*/
|
||||
|
||||
xfs_u8 IoContents;
|
||||
__asm__ volatile ("eieio; lbz %0,0(%1)":"=r" (IoContents):"b"
|
||||
(InAddress));
|
||||
return IoContents;
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
|
||||
xfs_u16 HardwareIO::xfs_in16(xfs_u32 InAddress)
|
||||
{
|
||||
/* read the contents of the I/O location and then synchronize the I/O
|
||||
* such that the I/O operation completes before proceeding on
|
||||
*/
|
||||
|
||||
xfs_u16 IoContents;
|
||||
__asm__ volatile ("eieio; lhz %0,0(%1)":"=r" (IoContents):"b"
|
||||
(InAddress));
|
||||
return IoContents;
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
|
||||
xfs_u32 HardwareIO::xfs_in32(xfs_u32 InAddress)
|
||||
{
|
||||
/* read the contents of the I/O location and then synchronize the I/O
|
||||
* such that the I/O operation completes before proceeding on
|
||||
*/
|
||||
|
||||
xfs_u32 IoContents;
|
||||
__asm__ volatile ("eieio; lwz %0,0(%1)":"=r" (IoContents):"b"
|
||||
(InAddress));
|
||||
return IoContents;
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
|
||||
void HardwareIO::xfs_out8(xfs_u32 OutAddress, xfs_u8 Value)
|
||||
{
|
||||
/* write the contents of the I/O location and then synchronize the I/O
|
||||
* such that the I/O operation completes before proceeding on
|
||||
*/
|
||||
|
||||
__asm__ volatile ("stb %0,0(%1); eieio"::"r" (Value), "b"(OutAddress));
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
void HardwareIO::xfs_out16(xfs_u32 OutAddress, xfs_u16 Value)
|
||||
{
|
||||
/* write the contents of the I/O location and then synchronize the I/O
|
||||
* such that the I/O operation completes before proceeding on
|
||||
*/
|
||||
|
||||
__asm__ volatile ("sth %0,0(%1); eieio"::"r" (Value), "b"(OutAddress));
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
|
||||
void HardwareIO::xfs_out32(xfs_u32 OutAddress, xfs_u32 Value)
|
||||
{
|
||||
/* write the contents of the I/O location and then synchronize the I/O
|
||||
* such that the I/O operation completes before proceeding on
|
||||
*/
|
||||
|
||||
__asm__ volatile ("stw %0,0(%1); eieio"::"r" (Value), "b"(OutAddress));
|
||||
}
|
||||
|
||||
|
||||
|
||||
30
slsDetectorSoftware/eigerDetectorServer/HardwareIO.h
Normal file
30
slsDetectorSoftware/eigerDetectorServer/HardwareIO.h
Normal file
@ -0,0 +1,30 @@
|
||||
|
||||
|
||||
//Class initially from Gerd and was called mmap_test.c
|
||||
|
||||
#ifndef HARDWAREIO_H
|
||||
#define HARDWAREIO_H
|
||||
|
||||
#include "xfs_types.h"
|
||||
|
||||
class HardwareIO{ //
|
||||
|
||||
protected:
|
||||
xfs_u8 xfs_in8(xfs_u32 InAddress);
|
||||
xfs_u16 xfs_in16(xfs_u32 InAddress);
|
||||
xfs_u32 xfs_in32(xfs_u32 InAddress);
|
||||
|
||||
void xfs_out8(xfs_u32 OutAddress, xfs_u8 Value);
|
||||
void xfs_out16(xfs_u32 OutAddress, xfs_u16 Value);
|
||||
void xfs_out32(xfs_u32 OutAddress, xfs_u32 Value);
|
||||
|
||||
|
||||
public:
|
||||
HardwareIO(){};
|
||||
virtual ~HardwareIO(){};
|
||||
|
||||
|
||||
};
|
||||
|
||||
|
||||
#endif
|
||||
@ -0,0 +1,62 @@
|
||||
|
||||
|
||||
//from Gerd and was called mmap_test.h
|
||||
|
||||
#ifndef __PLB_LL_FIFO_H__
|
||||
#define __PLB_LL_FIFO_H__
|
||||
|
||||
|
||||
/******************************************************************************/
|
||||
/* definitions */
|
||||
/******************************************************************************/
|
||||
|
||||
#define PLB_LL_FIFO_REG_CTRL 0
|
||||
#define PLB_LL_FIFO_REG_STATUS 1
|
||||
#define PLB_LL_FIFO_REG_FIFO 2
|
||||
|
||||
#define PLB_LL_FIFO_CTRL_LL_REM_SHIFT 30
|
||||
#define PLB_LL_FIFO_CTRL_LL_REM 0xC0000000
|
||||
#define PLB_LL_FIFO_CTRL_LL_EOF 0x20000000
|
||||
#define PLB_LL_FIFO_CTRL_LL_SOF 0x10000000
|
||||
#define PLB_LL_FIFO_CTRL_LL_MASK 0xF0000000
|
||||
|
||||
|
||||
#define PLB_LL_FIFO_CTRL_TX_RESET 0x08000000
|
||||
#define PLB_LL_FIFO_CTRL_RX_RESET 0x04000000
|
||||
|
||||
#define PLB_LL_FIFO_CTRL_RESET_STATUS 0x00800000
|
||||
#define PLB_LL_FIFO_CTRL_RESET_USER 0x00400000
|
||||
#define PLB_LL_FIFO_CTRL_RESET_LINK 0x00200000
|
||||
#define PLB_LL_FIFO_CTRL_RESET_GT 0x00100000
|
||||
|
||||
#define PLB_LL_FIFO_CTRL_RESET_ALL 0x0CF00000
|
||||
|
||||
// do not reset complete gtx dual in std. case
|
||||
// cause this would reset PLL and stop LL clk
|
||||
#define PLB_LL_FIFO_CTRL_RESET_STD 0x0CE00000
|
||||
|
||||
// reset Rx and Tx Fifo and set User Reset
|
||||
#define PLB_LL_FIFO_CTRL_RESET_FIFO 0x0C400000
|
||||
|
||||
|
||||
#define PLB_LL_FIFO_CTRL_CONFIG_VECTOR 0x000FFFFF
|
||||
|
||||
|
||||
#define PLB_LL_FIFO_STATUS_LL_REM_SHIFT 30
|
||||
#define PLB_LL_FIFO_STATUS_LL_REM 0xC0000000
|
||||
#define PLB_LL_FIFO_STATUS_LL_EOF 0x20000000
|
||||
#define PLB_LL_FIFO_STATUS_LL_SOF 0x10000000
|
||||
|
||||
#define PLB_LL_FIFO_STATUS_EMPTY 0x08000000
|
||||
#define PLB_LL_FIFO_STATUS_ALMOSTEMPTY 0x04000000
|
||||
#define PLB_LL_FIFO_STATUS_FULL 0x02000000
|
||||
#define PLB_LL_FIFO_STATUS_ALMOSTFULL 0x01000000
|
||||
|
||||
#define PLB_LL_FIFO_STATUS_VECTOR 0x000FFFFF
|
||||
|
||||
#define PLB_LL_FIFO_ALMOST_FULL_THRESHOLD_WORDS 100
|
||||
|
||||
|
||||
#endif // __PLB_LL_FIFO_H__
|
||||
|
||||
|
||||
237
slsDetectorSoftware/eigerDetectorServer/LocalLinkInterface.cxx
Normal file
237
slsDetectorSoftware/eigerDetectorServer/LocalLinkInterface.cxx
Normal file
@ -0,0 +1,237 @@
|
||||
|
||||
//Class initially from Gerd and was called mmap_test.c
|
||||
//return reversed 1 means good, 0 means failed
|
||||
|
||||
|
||||
#include <stdio.h>
|
||||
#include <unistd.h>
|
||||
#include <string.h>
|
||||
#include <sys/mman.h>
|
||||
#include <fcntl.h>
|
||||
|
||||
|
||||
#include "HardwareMMappingDefs.h"
|
||||
|
||||
#include "LocalLinkInterface.h"
|
||||
|
||||
|
||||
|
||||
LocalLinkInterface::LocalLinkInterface(unsigned int ll_fifo_badr){
|
||||
// printf("\n v 1 \n");
|
||||
printf("Initialize PLB LL FIFOs\n");
|
||||
ll_fifo_base=0;
|
||||
ll_fifo_ctrl_reg=0;
|
||||
if(Init(ll_fifo_badr)){
|
||||
Reset();
|
||||
printf("\tFIFO Status : 0x%08x\n",StatusVector());
|
||||
}else printf("\tError LocalLink Mappping : 0x%08x\n",ll_fifo_badr);
|
||||
|
||||
printf("\n\n");
|
||||
}
|
||||
|
||||
LocalLinkInterface::~LocalLinkInterface(){};
|
||||
|
||||
|
||||
bool LocalLinkInterface::Init(unsigned int ll_fifo_badr){
|
||||
int fd;
|
||||
void *plb_ll_fifo_ptr;
|
||||
|
||||
if ((fd=open("/dev/mem", O_RDWR)) < 0){
|
||||
fprintf(stderr, "Could not open /dev/mem\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
plb_ll_fifo_ptr = mmap(0, getpagesize(), PROT_READ | PROT_WRITE, MAP_FILE | MAP_SHARED, fd, ll_fifo_badr);
|
||||
close(fd);
|
||||
|
||||
if (plb_ll_fifo_ptr == MAP_FAILED){
|
||||
perror ("mmap");
|
||||
return 0;
|
||||
}
|
||||
|
||||
ll_fifo_base = (xfs_u32) plb_ll_fifo_ptr;
|
||||
ll_fifo_ctrl_reg = 0;
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
||||
|
||||
bool LocalLinkInterface::Reset(){
|
||||
return Reset(PLB_LL_FIFO_CTRL_RESET_STD);
|
||||
}
|
||||
|
||||
bool LocalLinkInterface::Reset(unsigned int rst_mask){
|
||||
ll_fifo_ctrl_reg |= rst_mask;
|
||||
printf("\tCTRL Register bits: 0x%08x\n",ll_fifo_ctrl_reg);
|
||||
|
||||
xfs_out32(ll_fifo_base+4*PLB_LL_FIFO_REG_CTRL,ll_fifo_ctrl_reg);
|
||||
xfs_out32(ll_fifo_base+4*PLB_LL_FIFO_REG_CTRL,ll_fifo_ctrl_reg);
|
||||
xfs_out32(ll_fifo_base+4*PLB_LL_FIFO_REG_CTRL,ll_fifo_ctrl_reg);
|
||||
xfs_out32(ll_fifo_base+4*PLB_LL_FIFO_REG_CTRL,ll_fifo_ctrl_reg);
|
||||
|
||||
ll_fifo_ctrl_reg &= (~rst_mask);
|
||||
|
||||
xfs_out32(ll_fifo_base+4*PLB_LL_FIFO_REG_CTRL,ll_fifo_ctrl_reg);
|
||||
// printf("FIFO CTRL Address: 0x%08x\n FIFO CTRL Register: 0x%08x\n",PLB_LL_FIFO_REG_CTRL,plb_ll_fifo[PLB_LL_FIFO_REG_CTRL]);
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
||||
|
||||
unsigned int LocalLinkInterface::StatusVector(){
|
||||
return xfs_in32(ll_fifo_base+4*PLB_LL_FIFO_REG_STATUS);
|
||||
}
|
||||
|
||||
int LocalLinkInterface::Write(unsigned int buffer_len, void *buffer){
|
||||
// note: buffer must be word (4 byte) aligned
|
||||
// frame_len in byte
|
||||
int vacancy=0;
|
||||
int i;
|
||||
int words_send = 0;
|
||||
int last_word;
|
||||
unsigned int *word_ptr;
|
||||
unsigned int fifo_ctrl;
|
||||
xfs_u32 status;
|
||||
|
||||
if (buffer_len < 1) return -1;
|
||||
|
||||
last_word = (buffer_len-1)/4;
|
||||
word_ptr = (unsigned int *)buffer;
|
||||
|
||||
while (words_send <= last_word)
|
||||
{
|
||||
while (!vacancy)//wait for Fifo to be empty again
|
||||
{
|
||||
status = xfs_in32(ll_fifo_base+4*PLB_LL_FIFO_REG_STATUS);
|
||||
if((status & PLB_LL_FIFO_STATUS_ALMOSTFULL) == 0) vacancy = 1;
|
||||
}
|
||||
|
||||
//Just to know: #define PLB_LL_FIFO_ALMOST_FULL_THRESHOLD_WORDS 100
|
||||
for (i=0; ((i<PLB_LL_FIFO_ALMOST_FULL_THRESHOLD_WORDS) && (words_send <= last_word)); i++)
|
||||
{
|
||||
fifo_ctrl = 0;
|
||||
if (words_send == 0)
|
||||
{
|
||||
fifo_ctrl = PLB_LL_FIFO_CTRL_LL_SOF;//announce the start of file
|
||||
}
|
||||
|
||||
if (words_send == last_word)
|
||||
{
|
||||
fifo_ctrl |= (PLB_LL_FIFO_CTRL_LL_EOF | (( (buffer_len-1)<<PLB_LL_FIFO_CTRL_LL_REM_SHIFT) & PLB_LL_FIFO_CTRL_LL_REM) );
|
||||
}
|
||||
ctrl_reg_write_mask(PLB_LL_FIFO_CTRL_LL_MASK,fifo_ctrl);
|
||||
xfs_out32(ll_fifo_base+4*PLB_LL_FIFO_REG_FIFO,word_ptr[words_send++]);
|
||||
}
|
||||
}
|
||||
return buffer_len;
|
||||
}
|
||||
|
||||
|
||||
int LocalLinkInterface::Read(unsigned int buffer_len, void *buffer){
|
||||
static unsigned int buffer_ptr = 0;
|
||||
// note: buffer must be word (4 byte) aligned
|
||||
// frame_len in byte
|
||||
int len;
|
||||
unsigned int *word_ptr;
|
||||
unsigned int status;
|
||||
volatile unsigned int fifo_val;
|
||||
int sof = 0;
|
||||
|
||||
word_ptr = (unsigned int *)buffer;
|
||||
do
|
||||
{
|
||||
status = xfs_in32(ll_fifo_base+4*PLB_LL_FIFO_REG_STATUS);
|
||||
|
||||
if (!(status & PLB_LL_FIFO_STATUS_EMPTY))
|
||||
{
|
||||
if (status & PLB_LL_FIFO_STATUS_LL_SOF)
|
||||
{
|
||||
if (buffer_ptr)
|
||||
{
|
||||
buffer_ptr = 0;
|
||||
return -1; // buffer overflow
|
||||
}
|
||||
// printf(">>>> SOF\n\r");
|
||||
buffer_ptr = 0;
|
||||
sof = 1;
|
||||
}
|
||||
|
||||
fifo_val = xfs_in32(ll_fifo_base+4*PLB_LL_FIFO_REG_FIFO); //read from fifo
|
||||
|
||||
if ((buffer_ptr > 0) || sof)
|
||||
{
|
||||
if ( (buffer_len >> 2) > buffer_ptr)
|
||||
{
|
||||
word_ptr[buffer_ptr++] = fifo_val; //write to buffer
|
||||
}
|
||||
else
|
||||
{
|
||||
buffer_ptr = 0;
|
||||
return -2; // buffer overflow
|
||||
}
|
||||
|
||||
if (status & PLB_LL_FIFO_STATUS_LL_EOF)
|
||||
{
|
||||
len = (buffer_ptr << 2) -3 + ( (status & PLB_LL_FIFO_STATUS_LL_REM)>>PLB_LL_FIFO_STATUS_LL_REM_SHIFT );
|
||||
// printf(">>>>status=0x%08x EOF len = %d \n\r\n\r",status, len);
|
||||
buffer_ptr = 0;
|
||||
return len;
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
}
|
||||
while(!(status & PLB_LL_FIFO_STATUS_EMPTY));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
bool LocalLinkInterface::ctrl_reg_write_mask(unsigned int mask, unsigned int val){
|
||||
// printf("Fifo CTRL Reg(1): 0x%08x\n",plb_ll_fifo_ctrl_reg);
|
||||
ll_fifo_ctrl_reg &= (~mask);
|
||||
//printf("Fifo CTRL Reg(2): 0x%08x\n",plb_ll_fifo_ctrl_reg);
|
||||
ll_fifo_ctrl_reg |= ( mask & val);
|
||||
// printf("Fifo CTRL Reg: 0x%08x\n",plb_ll_fifo_ctrl_reg);
|
||||
xfs_out32(ll_fifo_base+4*PLB_LL_FIFO_REG_CTRL,ll_fifo_ctrl_reg);
|
||||
// printf("Fifo STAT Reg: 0x%08x\n", plb_ll_fifo[PLB_LL_FIFO_REG_STATUS]);
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
||||
int LocalLinkInterface::Test(unsigned int buffer_len, void *buffer){
|
||||
|
||||
int len;
|
||||
unsigned int rec_buff_len = 4096;
|
||||
unsigned int rec_buffer[4097];
|
||||
|
||||
|
||||
Write(buffer_len,buffer);
|
||||
usleep(10000);
|
||||
|
||||
do{
|
||||
len = Read(rec_buff_len,rec_buffer);
|
||||
printf("receive length: %i\n",len);
|
||||
|
||||
if (len > 0){
|
||||
rec_buffer[len]=0;
|
||||
printf((char*) rec_buffer);
|
||||
printf("\n");
|
||||
}
|
||||
} while(len > 0);
|
||||
|
||||
printf("\n\n\n\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
void LocalLinkInterface::llfifo_print_frame(unsigned char* fbuff, int len){
|
||||
printf("\n\r----Frame of len : %d Byte\n\r",len);
|
||||
for(int i=0;i<len;i++){
|
||||
printf("0x%02x ",fbuff[i] );
|
||||
if ((i&0xf) == 0x7) printf(" ");
|
||||
if ((i&0xf) == 0xf) printf("\n\r");
|
||||
}
|
||||
printf("\n\r");
|
||||
}
|
||||
|
||||
|
||||
44
slsDetectorSoftware/eigerDetectorServer/LocalLinkInterface.h
Normal file
44
slsDetectorSoftware/eigerDetectorServer/LocalLinkInterface.h
Normal file
@ -0,0 +1,44 @@
|
||||
|
||||
//Class initially from Gerd and was called mmap_test.c
|
||||
|
||||
#ifndef LOCALLINKINTERFACE_H
|
||||
#define LOCALLINKINTERFACE_H
|
||||
|
||||
#include "xfs_types.h"
|
||||
#include "HardwareIO.h"
|
||||
|
||||
class LocalLinkInterface: public HardwareIO{ //
|
||||
|
||||
private:
|
||||
|
||||
xfs_u32 ll_fifo_base;
|
||||
unsigned int ll_fifo_ctrl_reg;
|
||||
|
||||
bool Init(unsigned int ll_fifo_badr);
|
||||
bool Reset(unsigned int rst_mask);
|
||||
|
||||
bool ctrl_reg_write_mask(unsigned int mask, unsigned int val);
|
||||
void llfifo_print_frame(unsigned char* fbuff, int len);
|
||||
|
||||
public:
|
||||
LocalLinkInterface(unsigned int ll_fifo_badr);
|
||||
virtual ~LocalLinkInterface();
|
||||
|
||||
unsigned int StatusVector();
|
||||
bool Reset();
|
||||
int Write(unsigned int buffer_len, void *buffer);
|
||||
int Read(unsigned int buffer_len, void *buffer);
|
||||
|
||||
int Test(unsigned int buffer_len, void *buffer);
|
||||
|
||||
/*
|
||||
bool FiFoReset(unsigned int numb);
|
||||
int FifoSend(unsigned int numb, unsigned int frame_len, void *buffer);
|
||||
int FifoReceive(unsigned int numb, unsigned int frame_len, void *buffer);
|
||||
int FifoTest(unsigned int numb,unsigned int send_len, char *send_str);
|
||||
*/
|
||||
|
||||
};
|
||||
|
||||
|
||||
#endif
|
||||
28
slsDetectorSoftware/eigerDetectorServer/LocalLinkTest.cxx
Normal file
28
slsDetectorSoftware/eigerDetectorServer/LocalLinkTest.cxx
Normal file
@ -0,0 +1,28 @@
|
||||
|
||||
#include <stdio.h>
|
||||
|
||||
#include "xparameters.h"
|
||||
|
||||
#include "LocalLinkInterface.h"
|
||||
|
||||
int main(){
|
||||
|
||||
char s[2000];
|
||||
sprintf(s,"papamama");
|
||||
|
||||
LocalLinkInterface* l0 = new LocalLinkInterface(XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR);
|
||||
l0->Test(8,s);
|
||||
LocalLinkInterface* l1 = new LocalLinkInterface(XPAR_PLB_LL_FIFO_AURORA_RX4_TX1_LEFT_BASEADDR);
|
||||
l1->Test(8,s);
|
||||
LocalLinkInterface* l2 = new LocalLinkInterface(XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_RIGHT_BASEADDR);
|
||||
l2->Test(8,s);
|
||||
LocalLinkInterface* l3 = new LocalLinkInterface(XPAR_PLB_LL_FIFO_AURORA_RX4_TX1_RIGHT_BASEADDR);
|
||||
l3->Test(8,s);
|
||||
|
||||
delete l0;
|
||||
delete l1;
|
||||
delete l2;
|
||||
delete l3;
|
||||
|
||||
return 1;
|
||||
}
|
||||
38
slsDetectorSoftware/eigerDetectorServer/Test.cxx
Normal file
38
slsDetectorSoftware/eigerDetectorServer/Test.cxx
Normal file
@ -0,0 +1,38 @@
|
||||
|
||||
/**
|
||||
* @author Ian Johnson
|
||||
* @version 1.0
|
||||
*/
|
||||
|
||||
|
||||
#include <iostream>
|
||||
#include <stdio.h>
|
||||
|
||||
#include "xparameters.h"
|
||||
|
||||
#include "Feb.h"
|
||||
|
||||
|
||||
using namespace std;
|
||||
|
||||
int main(){
|
||||
|
||||
cout<<"\n\n\n\n\n\n\n\n\n\n"<<endl;
|
||||
|
||||
|
||||
char s[2000];
|
||||
sprintf(s,"papamama");
|
||||
|
||||
Feb* feb = new Feb();
|
||||
|
||||
unsigned int v=22;
|
||||
feb->ReadRegister(0,0,v);
|
||||
feb->ReadRegister(0,0xffffffff,v);
|
||||
cout<<endl<<endl;
|
||||
feb->ReadRegister(1,0,v);
|
||||
feb->ReadRegister(1,0xffffffff,v);
|
||||
|
||||
delete feb;
|
||||
|
||||
return 1;
|
||||
}
|
||||
14
slsDetectorSoftware/eigerDetectorServer/build.sh
Executable file
14
slsDetectorSoftware/eigerDetectorServer/build.sh
Executable file
@ -0,0 +1,14 @@
|
||||
|
||||
echo -e "\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n"
|
||||
|
||||
. /opt/eldk-5.1/powerpc-4xx-softfloat/environment-setup-ppc440-linux
|
||||
|
||||
#powerpc-4xx-softfloat-g++ -Wall -o test Test.cxx HardwareIO.cxx LocalLinkInterface.cxx Feb.cxx -I .
|
||||
|
||||
powerpc-4xx-softfloat-g++ -Wall -o eiger_test EigerTest.cxx Eiger.cxx HardwareIO.cxx LocalLinkInterface.cxx Feb.cxx -I .
|
||||
|
||||
#powerpc-4xx-softfloat-g++ -Wall -o hardware_interface_test HardwareInterfaceTest.cxx HardwareInterface.cxx HardwareMMapping.cxx -I .
|
||||
|
||||
cp eiger_test rootfs_executables/.
|
||||
|
||||
|
||||
53
slsDetectorSoftware/eigerDetectorServer/setup.txt
Normal file
53
slsDetectorSoftware/eigerDetectorServer/setup.txt
Normal file
@ -0,0 +1,53 @@
|
||||
|
||||
|
||||
#detector setup
|
||||
#add_module module_number base_address_top (for half module)
|
||||
#add_module module_number base_address_top base_address_bottom (for full module)
|
||||
add_half_module 17 0
|
||||
#add_half_module 17 1 for bottom
|
||||
#add_module 18 10 12
|
||||
#add_module 2 13 15
|
||||
#add_module 1 120 22
|
||||
|
||||
|
||||
#default setting
|
||||
photon_energy 8000
|
||||
dynamic_range 16
|
||||
readout_speed 1 #(0-full,1-half,2-quarter and 3-superslow)
|
||||
readout_mode 0 #(0-parallel,1-non_parallel,2-safe_mode)
|
||||
|
||||
|
||||
#default dacs
|
||||
SvP 0
|
||||
Vtr 1.28
|
||||
Vrf 1.55
|
||||
Vrs 0.7
|
||||
SvN 2
|
||||
Vtgstv 1.278
|
||||
Vcmp_ll 0.5
|
||||
Vcmp_lr 0.5
|
||||
cal 2
|
||||
Vcmp_rl 0.5
|
||||
rxb_rb 0.6
|
||||
rxb_lb 0.6
|
||||
Vcmp_rr 0.5
|
||||
Vcp 0.1
|
||||
Vcn 1
|
||||
Vis 0.775
|
||||
|
||||
#default high_voltage
|
||||
high_voltage 152
|
||||
|
||||
#default iodelays
|
||||
iodelay 675
|
||||
|
||||
#newgoodiodelay 643
|
||||
#halfspeed_add_about 32
|
||||
#goodiodelay 1467
|
||||
#goodiodelay 1550
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
@ -2,10 +2,10 @@
|
||||
#define SVNURL "file:///afs/psi.ch/project/sls_det_software/svn/slsDetectorSoftware/eigerDetectorServer"
|
||||
//#define SVNREPPATH ""
|
||||
#define SVNREPUUID "951219d9-93cf-4727-9268-0efd64621fa3"
|
||||
//#define SVNREV 0x659
|
||||
//#define SVNREV 0x660
|
||||
//#define SVNKIND ""
|
||||
//#define SVNSCHED ""
|
||||
#define SVNAUTH "l_maliakal_d"
|
||||
#define SVNREV 0x659
|
||||
#define SVNDATE 0x20130829
|
||||
#define SVNREV 0x660
|
||||
#define SVNDATE 0x20130904
|
||||
//
|
||||
|
||||
50
slsDetectorSoftware/eigerDetectorServer/xfs_types.h
Normal file
50
slsDetectorSoftware/eigerDetectorServer/xfs_types.h
Normal file
@ -0,0 +1,50 @@
|
||||
#ifndef __XFS_TYPES_H__
|
||||
#define __XFS_TYPES_H__
|
||||
|
||||
/******************************************************************************/
|
||||
/* types */
|
||||
/******************************************************************************/
|
||||
|
||||
typedef unsigned int xfs_u32;
|
||||
typedef unsigned short xfs_u16;
|
||||
typedef unsigned char xfs_u8;
|
||||
|
||||
typedef signed int xfs_i32;
|
||||
typedef signed short xfs_i16;
|
||||
typedef signed char xfs_i8;
|
||||
|
||||
|
||||
// UDP Header
|
||||
typedef struct
|
||||
{
|
||||
// ethternet frame (14 byte)
|
||||
unsigned char dst_mac[6];
|
||||
unsigned char src_mac[6];
|
||||
unsigned char len_type[2];
|
||||
|
||||
// ip header (20 byte)
|
||||
unsigned char ver_headerlen[1];
|
||||
unsigned char service_type[1];
|
||||
unsigned char total_length[2];
|
||||
unsigned char identification[2];
|
||||
unsigned char flags[1];
|
||||
unsigned char frag_offset[1];
|
||||
unsigned char time_to_live[1];
|
||||
unsigned char protocol[1];
|
||||
unsigned char ip_header_checksum[2];
|
||||
unsigned char src_ip[4];
|
||||
unsigned char dst_ip[4];
|
||||
|
||||
// udp header (8 byte)
|
||||
unsigned char src_port[2];
|
||||
unsigned char dst_port[2];
|
||||
unsigned char udp_message_len[2];
|
||||
unsigned char udp_checksum[2];
|
||||
|
||||
} udp_header_type;
|
||||
|
||||
|
||||
|
||||
#endif // __XFS_TYPES_H__
|
||||
|
||||
|
||||
516
slsDetectorSoftware/eigerDetectorServer/xparameters.h
Normal file
516
slsDetectorSoftware/eigerDetectorServer/xparameters.h
Normal file
@ -0,0 +1,516 @@
|
||||
|
||||
/*******************************************************************
|
||||
*
|
||||
* CAUTION: This file is automatically generated by libgen.
|
||||
* Version: Xilinx EDK 12.4 EDK_MS4.81d
|
||||
* DO NOT EDIT.
|
||||
*
|
||||
* Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
|
||||
|
||||
*
|
||||
* Description: Driver parameters
|
||||
*
|
||||
*******************************************************************/
|
||||
|
||||
#define STDIN_BASEADDRESS 0xC0000000
|
||||
#define STDOUT_BASEADDRESS 0xC0000000
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
|
||||
/* Definitions for peripheral BB_IO_SHIFT_REG_PPC440 */
|
||||
#define XPAR_BB_IO_SHIFT_REG_PPC440_BASEADDR 0xD3000000
|
||||
#define XPAR_BB_IO_SHIFT_REG_PPC440_HIGHADDR 0xD300FFFF
|
||||
|
||||
|
||||
/* Definitions for peripheral EIGER_BEB_SYNCH_IO_PPC440 */
|
||||
#define XPAR_EIGER_BEB_SYNCH_IO_PPC440_BASEADDR 0xD3100000
|
||||
#define XPAR_EIGER_BEB_SYNCH_IO_PPC440_HIGHADDR 0xD310FFFF
|
||||
|
||||
|
||||
/* Definitions for peripheral PLB_BRAM_10G */
|
||||
#define XPAR_PLB_BRAM_10G_MEM0_BASEADDR 0xD4100000
|
||||
#define XPAR_PLB_BRAM_10G_MEM0_HIGHADDR 0xD410FFFF
|
||||
|
||||
|
||||
/* Definitions for peripheral PLB_BRAM_TEMAC */
|
||||
#define XPAR_PLB_BRAM_TEMAC_MEM0_BASEADDR 0xD4000000
|
||||
#define XPAR_PLB_BRAM_TEMAC_MEM0_HIGHADDR 0xD400FFFF
|
||||
|
||||
|
||||
/* Definitions for peripheral PLB_GPIO_SYS */
|
||||
#define XPAR_PLB_GPIO_SYS_BASEADDR 0xD1000000
|
||||
#define XPAR_PLB_GPIO_SYS_HIGHADDR 0xD100FFFF
|
||||
|
||||
|
||||
/* Definitions for peripheral PLB_GPIO_TEST */
|
||||
#define XPAR_PLB_GPIO_TEST_BASEADDR 0xD1010000
|
||||
#define XPAR_PLB_GPIO_TEST_HIGHADDR 0xD101FFFF
|
||||
|
||||
|
||||
/* Definitions for peripheral PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT */
|
||||
#define XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR 0xC4100000
|
||||
#define XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_HIGHADDR 0xC410FFFF
|
||||
|
||||
|
||||
/* Definitions for peripheral PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_RIGHT */
|
||||
#define XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_RIGHT_BASEADDR 0xC4110000
|
||||
#define XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_RIGHT_HIGHADDR 0xC411FFFF
|
||||
|
||||
|
||||
/* Definitions for peripheral PLB_LL_FIFO_AURORA_RX4_TX1_LEFT */
|
||||
#define XPAR_PLB_LL_FIFO_AURORA_RX4_TX1_LEFT_BASEADDR 0xC4120000
|
||||
#define XPAR_PLB_LL_FIFO_AURORA_RX4_TX1_LEFT_HIGHADDR 0xC412FFFF
|
||||
|
||||
|
||||
/* Definitions for peripheral PLB_LL_FIFO_AURORA_RX4_TX1_RIGHT */
|
||||
#define XPAR_PLB_LL_FIFO_AURORA_RX4_TX1_RIGHT_BASEADDR 0xC4130000
|
||||
#define XPAR_PLB_LL_FIFO_AURORA_RX4_TX1_RIGHT_HIGHADDR 0xC413FFFF
|
||||
|
||||
|
||||
/* Definitions for peripheral PLB_LL_FIFO_XAUI_10G */
|
||||
#define XPAR_PLB_LL_FIFO_XAUI_10G_BASEADDR 0xC4140000
|
||||
#define XPAR_PLB_LL_FIFO_XAUI_10G_HIGHADDR 0xC414FFFF
|
||||
|
||||
|
||||
/* Definitions for peripheral PLB_V46_CPU_TO_PLB_V46_BRIDGED */
|
||||
#define XPAR_PLB_V46_CPU_TO_PLB_V46_BRIDGED_BRIDGE_BASEADDR 0xCFFF0000
|
||||
#define XPAR_PLB_V46_CPU_TO_PLB_V46_BRIDGED_BRIDGE_HIGHADDR 0xCFFFFFFF
|
||||
#define XPAR_PLB_V46_CPU_TO_PLB_V46_BRIDGED_RNG0_BASEADDR 0xD0000000
|
||||
#define XPAR_PLB_V46_CPU_TO_PLB_V46_BRIDGED_RNG0_HIGHADDR 0xDFFFFFFF
|
||||
|
||||
|
||||
/* Definitions for peripheral PPC_SRAM */
|
||||
#define XPAR_PPC_SRAM_BASEADDR 0x00000000
|
||||
#define XPAR_PPC_SRAM_HIGHADDR 0x01FFFFFF
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
|
||||
/* Definitions for peripheral PFLASH */
|
||||
#define XPAR_PFLASH_NUM_BANKS_MEM 1
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Definitions for peripheral PFLASH */
|
||||
#define XPAR_PFLASH_MEM0_BASEADDR 0xE0000000
|
||||
#define XPAR_PFLASH_MEM0_HIGHADDR 0xE3FFFFFF
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Canonical definitions for peripheral PFLASH */
|
||||
#define XPAR_EMC_0_NUM_BANKS_MEM 1
|
||||
#define XPAR_EMC_0_MEM0_BASEADDR 0xE0000000
|
||||
#define XPAR_EMC_0_MEM0_HIGHADDR 0xE3FFFFFF
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Definitions for driver PLB_SHT1X_IF */
|
||||
#define XPAR_PLB_SHT1X_IF_NUM_INSTANCES 2
|
||||
|
||||
/* Definitions for peripheral PLB_SHT1X_IF_CH1 */
|
||||
#define XPAR_PLB_SHT1X_IF_CH1_DEVICE_ID 0
|
||||
#define XPAR_PLB_SHT1X_IF_CH1_BASEADDR 0xD2200000
|
||||
#define XPAR_PLB_SHT1X_IF_CH1_HIGHADDR 0xD220FFFF
|
||||
|
||||
|
||||
/* Definitions for peripheral PLB_SHT1X_IF_CH2 */
|
||||
#define XPAR_PLB_SHT1X_IF_CH2_DEVICE_ID 1
|
||||
#define XPAR_PLB_SHT1X_IF_CH2_BASEADDR 0xD2210000
|
||||
#define XPAR_PLB_SHT1X_IF_CH2_HIGHADDR 0xD221FFFF
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Definitions for driver UARTLITE */
|
||||
#define XPAR_XUARTLITE_NUM_INSTANCES 1
|
||||
|
||||
/* Definitions for peripheral RS232 */
|
||||
#define XPAR_RS232_BASEADDR 0xC0000000
|
||||
#define XPAR_RS232_HIGHADDR 0xC000FFFF
|
||||
#define XPAR_RS232_DEVICE_ID 0
|
||||
#define XPAR_RS232_BAUDRATE 115200
|
||||
#define XPAR_RS232_USE_PARITY 0
|
||||
#define XPAR_RS232_ODD_PARITY 0
|
||||
#define XPAR_RS232_DATA_BITS 8
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
|
||||
/* Canonical definitions for peripheral RS232 */
|
||||
#define XPAR_UARTLITE_0_DEVICE_ID XPAR_RS232_DEVICE_ID
|
||||
#define XPAR_UARTLITE_0_BASEADDR 0xC0000000
|
||||
#define XPAR_UARTLITE_0_HIGHADDR 0xC000FFFF
|
||||
#define XPAR_UARTLITE_0_BAUDRATE 115200
|
||||
#define XPAR_UARTLITE_0_USE_PARITY 0
|
||||
#define XPAR_UARTLITE_0_ODD_PARITY 0
|
||||
#define XPAR_UARTLITE_0_DATA_BITS 8
|
||||
#define XPAR_UARTLITE_0_SIO_CHAN 1
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Definitions for driver SPI */
|
||||
#define XPAR_XSPI_NUM_INSTANCES 2
|
||||
|
||||
/* Definitions for peripheral SPI_FLASH */
|
||||
#define XPAR_SPI_FLASH_DEVICE_ID 0
|
||||
#define XPAR_SPI_FLASH_BASEADDR 0xD2000000
|
||||
#define XPAR_SPI_FLASH_HIGHADDR 0xD200FFFF
|
||||
#define XPAR_SPI_FLASH_FIFO_EXIST 1
|
||||
#define XPAR_SPI_FLASH_SPI_SLAVE_ONLY 0
|
||||
#define XPAR_SPI_FLASH_NUM_SS_BITS 1
|
||||
#define XPAR_SPI_FLASH_NUM_TRANSFER_BITS 8
|
||||
|
||||
|
||||
/* Definitions for peripheral XPS_SPI_FEB_CFG */
|
||||
#define XPAR_XPS_SPI_FEB_CFG_DEVICE_ID 1
|
||||
#define XPAR_XPS_SPI_FEB_CFG_BASEADDR 0xD2010000
|
||||
#define XPAR_XPS_SPI_FEB_CFG_HIGHADDR 0xD201FFFF
|
||||
#define XPAR_XPS_SPI_FEB_CFG_FIFO_EXIST 1
|
||||
#define XPAR_XPS_SPI_FEB_CFG_SPI_SLAVE_ONLY 0
|
||||
#define XPAR_XPS_SPI_FEB_CFG_NUM_SS_BITS 2
|
||||
#define XPAR_XPS_SPI_FEB_CFG_NUM_TRANSFER_BITS 8
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
|
||||
/* Canonical definitions for peripheral SPI_FLASH */
|
||||
#define XPAR_SPI_0_DEVICE_ID XPAR_SPI_FLASH_DEVICE_ID
|
||||
#define XPAR_SPI_0_BASEADDR 0xD2000000
|
||||
#define XPAR_SPI_0_HIGHADDR 0xD200FFFF
|
||||
#define XPAR_SPI_0_FIFO_EXIST 1
|
||||
#define XPAR_SPI_0_SPI_SLAVE_ONLY 0
|
||||
#define XPAR_SPI_0_NUM_SS_BITS 1
|
||||
#define XPAR_SPI_0_NUM_TRANSFER_BITS 8
|
||||
|
||||
|
||||
/* Canonical definitions for peripheral XPS_SPI_FEB_CFG */
|
||||
#define XPAR_SPI_1_DEVICE_ID XPAR_XPS_SPI_FEB_CFG_DEVICE_ID
|
||||
#define XPAR_SPI_1_BASEADDR 0xD2010000
|
||||
#define XPAR_SPI_1_HIGHADDR 0xD201FFFF
|
||||
#define XPAR_SPI_1_FIFO_EXIST 1
|
||||
#define XPAR_SPI_1_SPI_SLAVE_ONLY 0
|
||||
#define XPAR_SPI_1_NUM_SS_BITS 2
|
||||
#define XPAR_SPI_1_NUM_TRANSFER_BITS 8
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Definitions for driver LLTEMAC */
|
||||
#define XPAR_XLLTEMAC_NUM_INSTANCES 1
|
||||
|
||||
/* Definitions for peripheral TEMAC_INST Channel 0 */
|
||||
#define XPAR_TEMAC_INST_CHAN_0_DEVICE_ID 0
|
||||
#define XPAR_TEMAC_INST_CHAN_0_BASEADDR 0xC3000000
|
||||
#define XPAR_TEMAC_INST_CHAN_0_HIGHADDR 0xC30FFFFF
|
||||
#define XPAR_TEMAC_INST_CHAN_0_TXCSUM 0
|
||||
#define XPAR_TEMAC_INST_CHAN_0_RXCSUM 0
|
||||
#define XPAR_TEMAC_INST_CHAN_0_PHY_TYPE 4
|
||||
#define XPAR_TEMAC_INST_CHAN_0_TXVLAN_TRAN 0
|
||||
#define XPAR_TEMAC_INST_CHAN_0_RXVLAN_TRAN 0
|
||||
#define XPAR_TEMAC_INST_CHAN_0_TXVLAN_TAG 0
|
||||
#define XPAR_TEMAC_INST_CHAN_0_RXVLAN_TAG 0
|
||||
#define XPAR_TEMAC_INST_CHAN_0_TXVLAN_STRP 0
|
||||
#define XPAR_TEMAC_INST_CHAN_0_RXVLAN_STRP 0
|
||||
#define XPAR_TEMAC_INST_CHAN_0_MCAST_EXTEND 0
|
||||
|
||||
/* Canonical definitions for peripheral TEMAC_INST Channel 0 */
|
||||
#define XPAR_LLTEMAC_0_DEVICE_ID 0
|
||||
#define XPAR_LLTEMAC_0_BASEADDR 0xC3000000
|
||||
#define XPAR_LLTEMAC_0_HIGHADDR 0xC30FFFFF
|
||||
#define XPAR_LLTEMAC_0_TXCSUM 0
|
||||
#define XPAR_LLTEMAC_0_RXCSUM 0
|
||||
#define XPAR_LLTEMAC_0_PHY_TYPE 4
|
||||
#define XPAR_LLTEMAC_0_TXVLAN_TRAN 0
|
||||
#define XPAR_LLTEMAC_0_RXVLAN_TRAN 0
|
||||
#define XPAR_LLTEMAC_0_TXVLAN_TAG 0
|
||||
#define XPAR_LLTEMAC_0_RXVLAN_TAG 0
|
||||
#define XPAR_LLTEMAC_0_TXVLAN_STRP 0
|
||||
#define XPAR_LLTEMAC_0_RXVLAN_STRP 0
|
||||
#define XPAR_LLTEMAC_0_MCAST_EXTEND 0
|
||||
#define XPAR_LLTEMAC_0_INTR 1
|
||||
|
||||
|
||||
/* LocalLink TYPE Enumerations */
|
||||
#define XPAR_LL_FIFO 1
|
||||
#define XPAR_LL_DMA 2
|
||||
|
||||
|
||||
/* Canonical LocalLink parameters for TEMAC_INST */
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
|
||||
/* Definitions for peripheral XPS_BRAM_IF_CNTLR_PPC440 */
|
||||
#define XPAR_XPS_BRAM_IF_CNTLR_PPC440_BASEADDR 0xFFFC0000
|
||||
#define XPAR_XPS_BRAM_IF_CNTLR_PPC440_HIGHADDR 0xFFFFFFFF
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
#define XPAR_INTC_MAX_NUM_INTR_INPUTS 5
|
||||
#define XPAR_XINTC_HAS_IPR 1
|
||||
#define XPAR_XINTC_USE_DCR 0
|
||||
/* Definitions for driver INTC */
|
||||
#define XPAR_XINTC_NUM_INSTANCES 1
|
||||
|
||||
/* Definitions for peripheral XPS_INTC_PPC440 */
|
||||
#define XPAR_XPS_INTC_PPC440_DEVICE_ID 0
|
||||
#define XPAR_XPS_INTC_PPC440_BASEADDR 0xC1000000
|
||||
#define XPAR_XPS_INTC_PPC440_HIGHADDR 0xC100FFFF
|
||||
#define XPAR_XPS_INTC_PPC440_KIND_OF_INTR 0xFFFFFFF4
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
#define XPAR_INTC_SINGLE_BASEADDR 0xC1000000
|
||||
#define XPAR_INTC_SINGLE_HIGHADDR 0xC100FFFF
|
||||
#define XPAR_INTC_SINGLE_DEVICE_ID XPAR_XPS_INTC_PPC440_DEVICE_ID
|
||||
#define XPAR_XPS_LL_FIFO_TEMAC_IP2INTC_IRPT_MASK 0X000001
|
||||
#define XPAR_XPS_INTC_PPC440_XPS_LL_FIFO_TEMAC_IP2INTC_IRPT_INTR 0
|
||||
#define XPAR_TEMAC_INST_TEMACINTC0_IRPT_MASK 0X000002
|
||||
#define XPAR_XPS_INTC_PPC440_TEMAC_INST_TEMACINTC0_IRPT_INTR 1
|
||||
#define XPAR_XPS_TIMER_PPC440_INTERRUPT_MASK 0X000004
|
||||
#define XPAR_XPS_INTC_PPC440_XPS_TIMER_PPC440_INTERRUPT_INTR 2
|
||||
#define XPAR_SPI_FLASH_IP2INTC_IRPT_MASK 0X000008
|
||||
#define XPAR_XPS_INTC_PPC440_SPI_FLASH_IP2INTC_IRPT_INTR 3
|
||||
#define XPAR_RS232_INTERRUPT_MASK 0X000010
|
||||
#define XPAR_XPS_INTC_PPC440_RS232_INTERRUPT_INTR 4
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Canonical definitions for peripheral XPS_INTC_PPC440 */
|
||||
#define XPAR_INTC_0_DEVICE_ID XPAR_XPS_INTC_PPC440_DEVICE_ID
|
||||
#define XPAR_INTC_0_BASEADDR 0xC1000000
|
||||
#define XPAR_INTC_0_HIGHADDR 0xC100FFFF
|
||||
#define XPAR_INTC_0_KIND_OF_INTR 0xFFFFFFF4
|
||||
|
||||
#define XPAR_INTC_0_LLFIFO_0_VEC_ID XPAR_XPS_INTC_PPC440_XPS_LL_FIFO_TEMAC_IP2INTC_IRPT_INTR
|
||||
#define XPAR_INTC_0_LLTEMAC_0_VEC_ID XPAR_XPS_INTC_PPC440_TEMAC_INST_TEMACINTC0_IRPT_INTR
|
||||
#define XPAR_INTC_0_TMRCTR_0_VEC_ID XPAR_XPS_INTC_PPC440_XPS_TIMER_PPC440_INTERRUPT_INTR
|
||||
#define XPAR_INTC_0_SPI_0_VEC_ID XPAR_XPS_INTC_PPC440_SPI_FLASH_IP2INTC_IRPT_INTR
|
||||
#define XPAR_INTC_0_UARTLITE_0_VEC_ID XPAR_XPS_INTC_PPC440_RS232_INTERRUPT_INTR
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Definitions for driver LLFIFO */
|
||||
#define XPAR_XLLFIFO_NUM_INSTANCES 1
|
||||
|
||||
/* Definitions for peripheral XPS_LL_FIFO_TEMAC */
|
||||
#define XPAR_XPS_LL_FIFO_TEMAC_DEVICE_ID 0
|
||||
#define XPAR_XPS_LL_FIFO_TEMAC_BASEADDR 0xC4000000
|
||||
#define XPAR_XPS_LL_FIFO_TEMAC_HIGHADDR 0xC400FFFF
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Canonical definitions for peripheral XPS_LL_FIFO_TEMAC */
|
||||
#define XPAR_LLFIFO_0_DEVICE_ID XPAR_XPS_LL_FIFO_TEMAC_DEVICE_ID
|
||||
#define XPAR_LLFIFO_0_BASEADDR 0xC4000000
|
||||
#define XPAR_LLFIFO_0_HIGHADDR 0xC400FFFF
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Definitions for driver SYSMON */
|
||||
#define XPAR_XSYSMON_NUM_INSTANCES 1
|
||||
|
||||
/* Definitions for peripheral XPS_SYSMON_ADC_PPC440 */
|
||||
#define XPAR_XPS_SYSMON_ADC_PPC440_DEVICE_ID 0
|
||||
#define XPAR_XPS_SYSMON_ADC_PPC440_BASEADDR 0xD0010000
|
||||
#define XPAR_XPS_SYSMON_ADC_PPC440_HIGHADDR 0xD001FFFF
|
||||
#define XPAR_XPS_SYSMON_ADC_PPC440_INCLUDE_INTR 1
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
|
||||
/* Canonical definitions for peripheral XPS_SYSMON_ADC_PPC440 */
|
||||
#define XPAR_SYSMON_0_DEVICE_ID XPAR_XPS_SYSMON_ADC_PPC440_DEVICE_ID
|
||||
#define XPAR_SYSMON_0_BASEADDR 0xD0010000
|
||||
#define XPAR_SYSMON_0_HIGHADDR 0xD001FFFF
|
||||
#define XPAR_SYSMON_0_INCLUDE_INTR 1
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Definitions for driver TMRCTR */
|
||||
#define XPAR_XTMRCTR_NUM_INSTANCES 1
|
||||
|
||||
/* Definitions for peripheral XPS_TIMER_PPC440 */
|
||||
#define XPAR_XPS_TIMER_PPC440_DEVICE_ID 0
|
||||
#define XPAR_XPS_TIMER_PPC440_BASEADDR 0xC2000000
|
||||
#define XPAR_XPS_TIMER_PPC440_HIGHADDR 0xC200FFFF
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
|
||||
/* Canonical definitions for peripheral XPS_TIMER_PPC440 */
|
||||
#define XPAR_TMRCTR_0_DEVICE_ID XPAR_XPS_TIMER_PPC440_DEVICE_ID
|
||||
#define XPAR_TMRCTR_0_BASEADDR 0xC2000000
|
||||
#define XPAR_TMRCTR_0_HIGHADDR 0xC200FFFF
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Definitions for bus frequencies */
|
||||
#define XPAR_CPU_PPC440_MPLB_FREQ_HZ 100000000
|
||||
/******************************************************************/
|
||||
|
||||
/* Canonical definitions for bus frequencies */
|
||||
#define XPAR_PROC_BUS_0_FREQ_HZ 100000000
|
||||
/******************************************************************/
|
||||
|
||||
#define XPAR_CPU_PPC440_CORE_CLOCK_FREQ_HZ 400000000
|
||||
#define XPAR_PPC440_VIRTEX5_CORE_CLOCK_FREQ_HZ 400000000
|
||||
#define XPAR_CPU_PPC440_IDCR_BASEADDR 0x00000000
|
||||
/******************************************************************/
|
||||
#define XPAR_CPU_ID 0
|
||||
#define XPAR_PPC440_VIRTEX5_ID 0
|
||||
#define XPAR_PPC440_VIRTEX5_PIR 0b1111
|
||||
#define XPAR_PPC440_VIRTEX5_ENDIAN_RESET 0
|
||||
#define XPAR_PPC440_VIRTEX5_USER_RESET 0b0000
|
||||
#define XPAR_PPC440_VIRTEX5_INTERCONNECT_IMASK 0xffffffff
|
||||
#define XPAR_PPC440_VIRTEX5_ICU_RD_FETCH_PLB_PRIO 0b00
|
||||
#define XPAR_PPC440_VIRTEX5_ICU_RD_SPEC_PLB_PRIO 0b00
|
||||
#define XPAR_PPC440_VIRTEX5_ICU_RD_TOUCH_PLB_PRIO 0b00
|
||||
#define XPAR_PPC440_VIRTEX5_DCU_RD_LD_CACHE_PLB_PRIO 0b00
|
||||
#define XPAR_PPC440_VIRTEX5_DCU_RD_NONCACHE_PLB_PRIO 0b00
|
||||
#define XPAR_PPC440_VIRTEX5_DCU_RD_TOUCH_PLB_PRIO 0b00
|
||||
#define XPAR_PPC440_VIRTEX5_DCU_RD_URGENT_PLB_PRIO 0b00
|
||||
#define XPAR_PPC440_VIRTEX5_DCU_WR_FLUSH_PLB_PRIO 0b00
|
||||
#define XPAR_PPC440_VIRTEX5_DCU_WR_STORE_PLB_PRIO 0b00
|
||||
#define XPAR_PPC440_VIRTEX5_DCU_WR_URGENT_PLB_PRIO 0b00
|
||||
#define XPAR_PPC440_VIRTEX5_DMA0_PLB_PRIO 0b00
|
||||
#define XPAR_PPC440_VIRTEX5_DMA1_PLB_PRIO 0b00
|
||||
#define XPAR_PPC440_VIRTEX5_DMA2_PLB_PRIO 0b00
|
||||
#define XPAR_PPC440_VIRTEX5_DMA3_PLB_PRIO 0b00
|
||||
#define XPAR_PPC440_VIRTEX5_IDCR_BASEADDR 0x00000000
|
||||
#define XPAR_PPC440_VIRTEX5_IDCR_HIGHADDR 0x000000FF
|
||||
#define XPAR_PPC440_VIRTEX5_APU_CONTROL 0b00010000000000000
|
||||
#define XPAR_PPC440_VIRTEX5_APU_UDI_0 0b000000000000000000000000
|
||||
#define XPAR_PPC440_VIRTEX5_APU_UDI_1 0b000000000000000000000000
|
||||
#define XPAR_PPC440_VIRTEX5_APU_UDI_2 0b000000000000000000000000
|
||||
#define XPAR_PPC440_VIRTEX5_APU_UDI_3 0b000000000000000000000000
|
||||
#define XPAR_PPC440_VIRTEX5_APU_UDI_4 0b000000000000000000000000
|
||||
#define XPAR_PPC440_VIRTEX5_APU_UDI_5 0b000000000000000000000000
|
||||
#define XPAR_PPC440_VIRTEX5_APU_UDI_6 0b000000000000000000000000
|
||||
#define XPAR_PPC440_VIRTEX5_APU_UDI_7 0b000000000000000000000000
|
||||
#define XPAR_PPC440_VIRTEX5_APU_UDI_8 0b000000000000000000000000
|
||||
#define XPAR_PPC440_VIRTEX5_APU_UDI_9 0b000000000000000000000000
|
||||
#define XPAR_PPC440_VIRTEX5_APU_UDI_10 0b000000000000000000000000
|
||||
#define XPAR_PPC440_VIRTEX5_APU_UDI_11 0b000000000000000000000000
|
||||
#define XPAR_PPC440_VIRTEX5_APU_UDI_12 0b000000000000000000000000
|
||||
#define XPAR_PPC440_VIRTEX5_APU_UDI_13 0b000000000000000000000000
|
||||
#define XPAR_PPC440_VIRTEX5_APU_UDI_14 0b000000000000000000000000
|
||||
#define XPAR_PPC440_VIRTEX5_APU_UDI_15 0b000000000000000000000000
|
||||
#define XPAR_PPC440_VIRTEX5_PPC440MC_ADDR_BASE 0x00000000
|
||||
#define XPAR_PPC440_VIRTEX5_PPC440MC_ADDR_HIGH 0X01FFFFFF
|
||||
#define XPAR_PPC440_VIRTEX5_PPC440MC_ROW_CONFLICT_MASK 0x00000000
|
||||
#define XPAR_PPC440_VIRTEX5_PPC440MC_BANK_CONFLICT_MASK 0x00000000
|
||||
#define XPAR_PPC440_VIRTEX5_PPC440MC_CONTROL 0X8140008F
|
||||
#define XPAR_PPC440_VIRTEX5_PPC440MC_PRIO_ICU 4
|
||||
#define XPAR_PPC440_VIRTEX5_PPC440MC_PRIO_DCUW 3
|
||||
#define XPAR_PPC440_VIRTEX5_PPC440MC_PRIO_DCUR 2
|
||||
#define XPAR_PPC440_VIRTEX5_PPC440MC_PRIO_SPLB1 0
|
||||
#define XPAR_PPC440_VIRTEX5_PPC440MC_PRIO_SPLB0 1
|
||||
#define XPAR_PPC440_VIRTEX5_PPC440MC_ARB_MODE 0
|
||||
#define XPAR_PPC440_VIRTEX5_PPC440MC_MAX_BURST 8
|
||||
#define XPAR_PPC440_VIRTEX5_MPLB_AWIDTH 32
|
||||
#define XPAR_PPC440_VIRTEX5_MPLB_DWIDTH 128
|
||||
#define XPAR_PPC440_VIRTEX5_MPLB_NATIVE_DWIDTH 128
|
||||
#define XPAR_PPC440_VIRTEX5_MPLB_COUNTER 0x00000500
|
||||
#define XPAR_PPC440_VIRTEX5_MPLB_PRIO_ICU 4
|
||||
#define XPAR_PPC440_VIRTEX5_MPLB_PRIO_DCUW 3
|
||||
#define XPAR_PPC440_VIRTEX5_MPLB_PRIO_DCUR 2
|
||||
#define XPAR_PPC440_VIRTEX5_MPLB_PRIO_SPLB1 0
|
||||
#define XPAR_PPC440_VIRTEX5_MPLB_PRIO_SPLB0 1
|
||||
#define XPAR_PPC440_VIRTEX5_MPLB_ARB_MODE 0
|
||||
#define XPAR_PPC440_VIRTEX5_MPLB_SYNC_TATTRIBUTE 0
|
||||
#define XPAR_PPC440_VIRTEX5_MPLB_MAX_BURST 8
|
||||
#define XPAR_PPC440_VIRTEX5_MPLB_ALLOW_LOCK_XFER 1
|
||||
#define XPAR_PPC440_VIRTEX5_MPLB_READ_PIPE_ENABLE 1
|
||||
#define XPAR_PPC440_VIRTEX5_MPLB_WRITE_PIPE_ENABLE 1
|
||||
#define XPAR_PPC440_VIRTEX5_MPLB_WRITE_POST_ENABLE 1
|
||||
#define XPAR_PPC440_VIRTEX5_MPLB_P2P 0
|
||||
#define XPAR_PPC440_VIRTEX5_MPLB_WDOG_ENABLE 1
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB0_AWIDTH 32
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB0_DWIDTH 128
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB0_NATIVE_DWIDTH 128
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB0_SUPPORT_BURSTS 1
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB0_USE_MPLB_ADDR 0
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB0_NUM_MPLB_ADDR_RNG 0
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB0_RNG_MC_BASEADDR 0xFFFFFFFF
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB0_RNG_MC_HIGHADDR 0x00000000
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB0_RNG0_MPLB_BASEADDR 0xFFFFFFFF
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB0_RNG0_MPLB_HIGHADDR 0x00000000
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB0_RNG1_MPLB_BASEADDR 0xFFFFFFFF
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB0_RNG1_MPLB_HIGHADDR 0x00000000
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB0_RNG2_MPLB_BASEADDR 0xFFFFFFFF
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB0_RNG2_MPLB_HIGHADDR 0x00000000
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB0_RNG3_MPLB_BASEADDR 0xFFFFFFFF
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB0_RNG3_MPLB_HIGHADDR 0x00000000
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB0_NUM_MASTERS 1
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB0_MID_WIDTH 1
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB0_ALLOW_LOCK_XFER 1
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB0_READ_PIPE_ENABLE 1
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB0_PROPAGATE_MIRQ 0
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB0_P2P -1
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB1_AWIDTH 32
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB1_DWIDTH 128
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB1_NATIVE_DWIDTH 128
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB1_SUPPORT_BURSTS 1
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB1_USE_MPLB_ADDR 0
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB1_NUM_MPLB_ADDR_RNG 0
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB1_RNG_MC_BASEADDR 0xFFFFFFFF
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB1_RNG_MC_HIGHADDR 0x00000000
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB1_RNG0_MPLB_BASEADDR 0xFFFFFFFF
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB1_RNG0_MPLB_HIGHADDR 0x00000000
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB1_RNG1_MPLB_BASEADDR 0xFFFFFFFF
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB1_RNG1_MPLB_HIGHADDR 0x00000000
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB1_RNG2_MPLB_BASEADDR 0xFFFFFFFF
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB1_RNG2_MPLB_HIGHADDR 0x00000000
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB1_RNG3_MPLB_BASEADDR 0xFFFFFFFF
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB1_RNG3_MPLB_HIGHADDR 0x00000000
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB1_NUM_MASTERS 1
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB1_MID_WIDTH 1
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB1_ALLOW_LOCK_XFER 1
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB1_READ_PIPE_ENABLE 1
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB1_PROPAGATE_MIRQ 0
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB1_P2P -1
|
||||
#define XPAR_PPC440_VIRTEX5_NUM_DMA 0
|
||||
#define XPAR_PPC440_VIRTEX5_DMA0_TXCHANNELCTRL 0x01010000
|
||||
#define XPAR_PPC440_VIRTEX5_DMA0_RXCHANNELCTRL 0x01010000
|
||||
#define XPAR_PPC440_VIRTEX5_DMA0_CONTROL 0b00000000
|
||||
#define XPAR_PPC440_VIRTEX5_DMA0_TXIRQTIMER 0b1111111111
|
||||
#define XPAR_PPC440_VIRTEX5_DMA0_RXIRQTIMER 0b1111111111
|
||||
#define XPAR_PPC440_VIRTEX5_DMA1_TXCHANNELCTRL 0x01010000
|
||||
#define XPAR_PPC440_VIRTEX5_DMA1_RXCHANNELCTRL 0x01010000
|
||||
#define XPAR_PPC440_VIRTEX5_DMA1_CONTROL 0b00000000
|
||||
#define XPAR_PPC440_VIRTEX5_DMA1_TXIRQTIMER 0b1111111111
|
||||
#define XPAR_PPC440_VIRTEX5_DMA1_RXIRQTIMER 0b1111111111
|
||||
#define XPAR_PPC440_VIRTEX5_DMA2_TXCHANNELCTRL 0x01010000
|
||||
#define XPAR_PPC440_VIRTEX5_DMA2_RXCHANNELCTRL 0x01010000
|
||||
#define XPAR_PPC440_VIRTEX5_DMA2_CONTROL 0b00000000
|
||||
#define XPAR_PPC440_VIRTEX5_DMA2_TXIRQTIMER 0b1111111111
|
||||
#define XPAR_PPC440_VIRTEX5_DMA2_RXIRQTIMER 0b1111111111
|
||||
#define XPAR_PPC440_VIRTEX5_DMA3_TXCHANNELCTRL 0x01010000
|
||||
#define XPAR_PPC440_VIRTEX5_DMA3_RXCHANNELCTRL 0x01010000
|
||||
#define XPAR_PPC440_VIRTEX5_DMA3_CONTROL 0b00000000
|
||||
#define XPAR_PPC440_VIRTEX5_DMA3_TXIRQTIMER 0b1111111111
|
||||
#define XPAR_PPC440_VIRTEX5_DMA3_RXIRQTIMER 0b1111111111
|
||||
#define XPAR_PPC440_VIRTEX5_DCR_AUTOLOCK_ENABLE 1
|
||||
#define XPAR_PPC440_VIRTEX5_PPCDM_ASYNCMODE 0
|
||||
#define XPAR_PPC440_VIRTEX5_PPCDS_ASYNCMODE 0
|
||||
#define XPAR_PPC440_VIRTEX5_GENERATE_PLB_TIMESPECS 1
|
||||
#define XPAR_PPC440_VIRTEX5_HW_VER "1.01.a"
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user