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g2 calibrated settings

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This commit is contained in:
maliakal_d 2021-09-17 17:37:54 +02:00
parent 6abf61e6f9
commit fd59c20975
2 changed files with 12 additions and 2 deletions
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6
slsDetectorServers/gotthard2DetectorServer/slsDetectorFunctionList.c
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@ -472,6 +472,12 @@ void setupDetector() {
// power on chip
powerChip(1);
// default asic value (masks? what do they mean? TODO)
bus_w(ASIC_CONFIG_REG, DEFAULT_ASIC_CONFIG_VALUE);
setPhase(READOUT_C1, DEFAULT_CLK1_PHASE_DEG, 1);
setDBITPipeline(DEFAULT_DBIT_PIPELINE);
// also sets default dac and on chip dac values
if (readConfigFile() == FAIL) {
return;

8
slsDetectorServers/gotthard2DetectorServer/slsDetectorServer_defs.h
View File

@ -52,8 +52,8 @@
#define DEFAULT_TIMING_SOURCE (TIMING_INTERNAL)
#define DEFAULT_ALGORITHM (ALG_HITS)
#define DEFAULT_READOUT_C0 (6) //(144444448) // rdo_clk, 144 MHz
#define DEFAULT_READOUT_C1 (6) //(144444448) // rdo_x2_clk, 144 MHz
#define DEFAULT_READOUT_C0 (8) //(108333336) // rdo_clk, 144 MHz
#define DEFAULT_READOUT_C1 (8) //(108333336) // rdo_x2_clk, 144 MHz
#define DEFAULT_SYSTEM_C0 (5) //(144444448) // run_clk, 144 MHz
#define DEFAULT_SYSTEM_C1 (10) //(72222224) // chip_clk, 72 MHz
#define DEFAULT_SYSTEM_C2 (5) //(144444448) // sync_clk, 144 MHz
@ -65,6 +65,10 @@
#define READOUT_PLL_VCO_FREQ_HZ (866666688) // 866 MHz
#define SYSTEM_PLL_VCO_FREQ_HZ (722222224) // 722 MHz
#define DEFAULT_CLK1_PHASE_DEG (270)
#define DEFAULT_DBIT_PIPELINE (1)
#define DEFAULT_ASIC_CONFIG_VALUE (0x80350000)
#define VETO_DATA_SIZE (160)
typedef struct {
uint64_t frameNumber;