From fd59c20975259784f5f1c839d853b3ccfd57f2ce Mon Sep 17 00:00:00 2001
From: Dhanya Thattil <dhanya.thattil@psi.ch>
Date: Fri, 17 Sep 2021 17:37:54 +0200
Subject: [PATCH] g2 calibrated settings

---
 .../gotthard2DetectorServer/slsDetectorFunctionList.c     | 6 ++++++
 .../gotthard2DetectorServer/slsDetectorServer_defs.h      | 8 ++++++--
 2 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/slsDetectorServers/gotthard2DetectorServer/slsDetectorFunctionList.c b/slsDetectorServers/gotthard2DetectorServer/slsDetectorFunctionList.c
index 8c45ae8ed..17d5175bc 100644
--- a/slsDetectorServers/gotthard2DetectorServer/slsDetectorFunctionList.c
+++ b/slsDetectorServers/gotthard2DetectorServer/slsDetectorFunctionList.c
@@ -472,6 +472,12 @@ void setupDetector() {
     // power on chip
     powerChip(1);
 
+    // default asic value (masks? what do they mean? TODO)
+    bus_w(ASIC_CONFIG_REG, DEFAULT_ASIC_CONFIG_VALUE);
+
+    setPhase(READOUT_C1, DEFAULT_CLK1_PHASE_DEG, 1);
+    setDBITPipeline(DEFAULT_DBIT_PIPELINE);
+
     // also sets default dac and on chip dac values
     if (readConfigFile() == FAIL) {
         return;
diff --git a/slsDetectorServers/gotthard2DetectorServer/slsDetectorServer_defs.h b/slsDetectorServers/gotthard2DetectorServer/slsDetectorServer_defs.h
index 2cc45638f..c84b10e03 100644
--- a/slsDetectorServers/gotthard2DetectorServer/slsDetectorServer_defs.h
+++ b/slsDetectorServers/gotthard2DetectorServer/slsDetectorServer_defs.h
@@ -52,8 +52,8 @@
 #define DEFAULT_TIMING_SOURCE       (TIMING_INTERNAL)
 #define DEFAULT_ALGORITHM           (ALG_HITS)
 
-#define DEFAULT_READOUT_C0 (6)  //(144444448) // rdo_clk, 144 MHz
-#define DEFAULT_READOUT_C1 (6)  //(144444448) // rdo_x2_clk, 144 MHz
+#define DEFAULT_READOUT_C0 (8) //(108333336) // rdo_clk, 144 MHz
+#define DEFAULT_READOUT_C1 (8) //(108333336) // rdo_x2_clk, 144 MHz
 #define DEFAULT_SYSTEM_C0  (5)  //(144444448) // run_clk, 144 MHz
 #define DEFAULT_SYSTEM_C1  (10) //(72222224) // chip_clk, 72 MHz
 #define DEFAULT_SYSTEM_C2  (5)  //(144444448) // sync_clk, 144 MHz
@@ -65,6 +65,10 @@
 #define READOUT_PLL_VCO_FREQ_HZ (866666688) // 866 MHz
 #define SYSTEM_PLL_VCO_FREQ_HZ  (722222224) // 722 MHz
 
+#define DEFAULT_CLK1_PHASE_DEG    (270)
+#define DEFAULT_DBIT_PIPELINE     (1)
+#define DEFAULT_ASIC_CONFIG_VALUE (0x80350000)
+
 #define VETO_DATA_SIZE          (160)
 typedef struct {
     uint64_t frameNumber;