detectors/slsDetectorPackage
25
0
Fork 0
mirror of https://github.com/slsdetectorgroup/slsDetectorPackage.git synced 2025-04-23 06:50:02 +02:00
Code Issues Actions Packages Releases Activity

25 um server using a config.txt file

Browse Source
This commit is contained in:
Dhanya Maliakal 2017-08-03 14:16:18 +02:00
parent 37dd32f1b0
commit fbee70818a
10 changed files with 220 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
slsDetectorSoftware/gotthardDetectorServer/config.txt Normal file
View File

@ -0,0 +1,20 @@
#masterflags (no_master, is_master, is_slave)
masterflags no_master
#master default delay
masterdefaultdelay 70
#patternphase
patternphase 0
#adcphase
adcphase 0
#slave pattern phase
slavepatternphase 0
#slave adc phase
slaveadcphase 0
#rst to sw1 delay
rsttosw1delay 2

175
slsDetectorSoftware/gotthardDetectorServer/firmware_funcs.c
View File

@ -55,6 +55,16 @@ int masterMode=NO_MASTER, syncMode=NO_SYNCHRONIZATION, timingMode=AUTO_TIMING;
enum externalSignalFlag signals[4]={EXT_SIG_OFF, EXT_SIG_OFF, EXT_SIG_OFF, EXT_SIG_OFF};
//for the 25um detectors
int masterflags = NO_MASTER;
int masterdefaultdelay = 62;
int patternphase = 0;
int adcphase = 0;
int slavepatternphase = 0;
int slaveadcphase = 0;
int rsttosw1delay = 2;
#ifdef MCB_FUNCS
extern const int nChans;
extern const int nChips;
@ -230,6 +240,134 @@ u_int32_t bus_r(u_int32_t offset) {
}
void setMasterSlaveConfiguration(){
/*
int masterflags = NO_MASTER;
int masterdefaultdelay = 62;
int patternphase = 0;
int adcphase = 0;
int slavepatternphase = 0;
int slaveadcphase = 0;
int sw1torstdelay = 2;
*/
// global master default delay picked from config file
FILE* fd=fopen(CONFIG_FILE,"r");
if(fd==NULL){
cprintf(RED,"\nWarning: Could not open file\n");
return;
}
cprintf(BLUE,"config file %s opened\n", CONFIG_FILE);
char key[256];
char value[256];
char line[256];
int ival=0;
u_int32_t val=0;
while (fgets(line, sizeof(line), fd)) {
if(line[0] == '#')
continue;
sscanf(line, "%s %s\n", key, value);
if (!strcasecmp(key,"masterflags")) {
if (!strcasecmp(value,"is_master")) {
masterflags = IS_MASTER;
}
else if (!strcasecmp(value,"is_slave")) {
masterflags = IS_SLAVE;
}
else if (!strcasecmp(value,"no_master")){
masterflags = NO_MASTER;
}
else {
cprintf(RED,"could not scan masterflags %s value from config file\n",value);
exit(EXIT_FAILURE);
}
}
else {
if(sscanf(value,"%d",&ival)<=0) {
cprintf(RED,"could not scan patternphase %s value from config file\n",value);
exit(EXIT_FAILURE);
}
if (!strcasecmp(key,"masterdefaultdelay"))
masterdefaultdelay = ival;
else if (!strcasecmp(key,"patternphase"))
patternphase = ival;
else if (!strcasecmp(key,"adcphase"))
adcphase = ival;
else if (!strcasecmp(key,"slavepatternphase"))
slavepatternphase = ival;
else if (!strcasecmp(key,"slaveadcphase"))
slaveadcphase = ival;
else if (!strcasecmp(key,"rsttosw1delay"))
rsttosw1delay = ival;
else {
cprintf(RED,"could not scan parameter name %s from config file\n",key);
exit(EXIT_FAILURE);
}
}
}
cprintf(BLUE, "masterflags: %d\n"
"masterdefaultdelay:%d\n"
"patternphase:%d\n"
"adcphase:%d\n"
"slavepatternphase:%d\n"
"slaveadcphase:%d\n"
"rsttosw1delay:%d\n",
masterflags,
masterdefaultdelay,
patternphase,
adcphase,
slavepatternphase,
slaveadcphase,
rsttosw1delay);
if (masterflags == IS_MASTER) {
// set delay
setDelay(0);
/* Set pattern phase for the master module */
val=bus_r(MULTI_PURPOSE_REG);
val = (val & (~(PLL_CLK_SEL_MSK))) | PLL_CLK_SEL_MASTER_VAL;
bus_w(MULTI_PURPOSE_REG,val);
setPhaseShift(patternphase);
/* Set adc phase for the master module */
val=bus_r(MULTI_PURPOSE_REG);
val = (val & (~(PLL_CLK_SEL_MSK))) | PLL_CLK_SEL_MASTER_ADC_VAL;
bus_w(MULTI_PURPOSE_REG,val);
setPhaseShift(adcphase);
/* Set pattern phase for the slave module */
val=bus_r(MULTI_PURPOSE_REG);
val = (val & (~(PLL_CLK_SEL_MSK))) | PLL_CLK_SEL_SLAVE_VAL;
bus_w(MULTI_PURPOSE_REG,val);
setPhaseShift(slavepatternphase);
/* Set adc phase for the slave module */
val=bus_r(MULTI_PURPOSE_REG);
val = (val & (~(PLL_CLK_SEL_MSK))) | PLL_CLK_SEL_SLAVE_ADC_VAL;
bus_w(MULTI_PURPOSE_REG,val);
setPhaseShift(slaveadcphase);
}
if (masterflags == IS_MASTER || masterflags == IS_SLAVE) {
val=bus_r(MULTI_PURPOSE_REG);
//#ifdef VERBOSE
printf("Value of multipurpose reg:%d\n",bus_r(MULTI_PURPOSE_REG));
//#endif
val = (val & (~(RST_TO_SW1_DELAY_MSK))) | ((rsttosw1delay << RST_TO_SW1_DELAY_OFFSET) & (RST_TO_SW1_DELAY_MSK));
bus_w(MULTI_PURPOSE_REG,val);
}
fclose(fd);
}
int setPhaseShiftOnce(){
u_int32_t addr, reg;
int i;
@ -258,6 +396,31 @@ int setPhaseShiftOnce(){
}
int setPhaseShift(int numphaseshift){
u_int32_t addr, reg;
int i;
addr=MULTI_PURPOSE_REG;
reg=bus_r(addr);
#ifdef VERBOSE
printf("Multipurpose reg:%x\n",reg);
#endif
printf("\nImplementing phase shift of %d\n",numphaseshift);
for (i=0;i<numphaseshift;i++) {
bus_w(addr,reg | PHASE_STEP_BIT);
bus_w(addr,reg & (~PHASE_STEP_BIT));
}
#ifdef VERBOSE
printf("Multipupose reg now:%x\n",bus_r(addr));
#endif
return OK;
}
int cleanFifo(){
u_int32_t addr, reg, val;
@ -926,9 +1089,19 @@ int64_t getPeriod(){
int64_t setDelay(int64_t value){
/* time is in ns */
if (value!=-1) {
if (masterflags == IS_MASTER) {
value += masterdefaultdelay;
cprintf(BLUE,"Actual delay for master: %lld\n", (long long int) value);
}
value*=(1E-9*CLK_FREQ);
}
return set64BitReg(value,SET_DELAY_LSB_REG, SET_DELAY_MSB_REG)/(1E-9*CLK_FREQ);
int64_t retval = set64BitReg(value,SET_DELAY_LSB_REG, SET_DELAY_MSB_REG)/(1E-9*CLK_FREQ);
if (masterflags == IS_MASTER) {
cprintf(BLUE,"Actual delay read from master: %lld\n", (long long int) retval);
retval -= masterdefaultdelay;
}
return retval;
}
int64_t getDelay(){

2
slsDetectorSoftware/gotthardDetectorServer/firmware_funcs.h
View File

@ -28,7 +28,9 @@ u_int16_t bus_w16(u_int32_t offset, u_int16_t data);//aldos function
u_int32_t bus_w(u_int32_t offset, u_int32_t data);
u_int32_t bus_r(u_int32_t offset);
void setMasterSlaveConfiguration();
int setPhaseShiftOnce();
int setPhaseShift(int numphaseshift);
int cleanFifo();
int setDAQRegister();

10
slsDetectorSoftware/gotthardDetectorServer/gitInfo.txt
View File

@ -1,9 +1,9 @@
Path: slsDetectorsPackage/slsDetectorSoftware/gotthardDetectorServer
URL: origin git@git.psi.ch:sls_detectors_software/sls_detector_software.git
Repository Root: origin git@git.psi.ch:sls_detectors_software/sls_detector_software.git
Repsitory UUID: 9f1b82c18ab0893d65bfadeb646b8ea244614632
Revision: 203
Branch: developer
Repsitory UUID: dc7806552a0a896870c4dd94dd47931c39180de7
Revision: 205
Branch: gotthard25um
Last Changed Author: Dhanya_Maliakal
Last Changed Rev: 1443
Last Changed Date: 2017-07-10 10:54:26.000000002 +0200 ./Makefile
Last Changed Rev: 1453
Last Changed Date: 2017-08-03 10:03:31.000000002 +0200 ./firmware_funcs.c

8
slsDetectorSoftware/gotthardDetectorServer/gitInfoGotthard.h
View File

@ -1,11 +1,11 @@
//#define SVNPATH ""
#define SVNURL "git@git.psi.ch:sls_detectors_software/sls_detector_software.git"
//#define SVNREPPATH ""
#define SVNREPUUID "9f1b82c18ab0893d65bfadeb646b8ea244614632"
//#define SVNREV 0x1443
#define SVNREPUUID "dc7806552a0a896870c4dd94dd47931c39180de7"
//#define SVNREV 0x1453
//#define SVNKIND ""
//#define SVNSCHED ""
#define SVNAUTH "Dhanya_Maliakal"
#define SVNREV 0x1443
#define SVNDATE 0x20170710
#define SVNREV 0x1453
#define SVNDATE 0x20170803
//

BIN
slsDetectorSoftware/gotthardDetectorServer/gotthardDetectorServerv3.0.0.1
View File

Binary file not shown.

BIN
slsDetectorSoftware/gotthardDetectorServer/gotthardDetectorServerv3.0.0.2 Executable file
View File

Binary file not shown.

12
slsDetectorSoftware/gotthardDetectorServer/registers_g.h
View File

@ -274,14 +274,22 @@
#define WRITE_BACK_OFFSET 6
#define RESET_BIT 0x00000080
#define RESET_OFFSET 7
#define PLL_CLK_SEL_MSK 0x00000700
#define PLL_CLK_SEL_OFFSET 8
#define PLL_CLK_SEL_MASTER_VAL ((0x1 << PLL_CLK_SEL_OFFSET) & PLL_CLK_SEL_MSK)
#define PLL_CLK_SEL_MASTER_ADC_VAL ((0x2 << PLL_CLK_SEL_OFFSET) & PLL_CLK_SEL_MSK)
#define PLL_CLK_SEL_SLAVE_VAL ((0x3 << PLL_CLK_SEL_OFFSET) & PLL_CLK_SEL_MSK)
#define PLL_CLK_SEL_SLAVE_ADC_VAL ((0x4 << PLL_CLK_SEL_OFFSET) & PLL_CLK_SEL_MSK)
#define ENET_RESETN_BIT 0x00000800
#define ENET_RESETN_OFFSET 11
#define INT_RSTN_BIT 0x00002000
#define INT_RSTN_OFFSET 13
#define INT_RSTN_BIT 0x00001000
#define INT_RSTN_OFFSET 12
#define DIGITAL_TEST_BIT 0x00004000
#define DIGITAL_TEST_OFFSET 14
//#define CHANGE_AT_POWER_ON_BIT 0x00008000
//#define CHANGE_AT_POWER_ON_OFFSET 15
#define RST_TO_SW1_DELAY_MSK 0x000F0000
#define RST_TO_SW1_DELAY_OFFSET 16
/* settings/conf gain register */

4
slsDetectorSoftware/gotthardDetectorServer/server_defs.h
View File

@ -24,6 +24,10 @@
#define NCHIPS_PER_ADC 2
// for 25 um
#define CONFIG_FILE "config.txt"
//#define TRIM_DR ((2**NTRIMBITS)-1)
//#define COUNT_DR ((2**NCOUNTBITS)-1)
#define TRIM_DR (((int)pow(2,NTRIMBITS))-1)

1
slsDetectorSoftware/gotthardDetectorServer/server_funcs.c
View File

@ -99,6 +99,7 @@ int init_detector( int b) {
setMaster(GET_MASTER);
setSynchronization(GET_SYNCHRONIZATION_MODE);
startReceiver(0);
setMasterSlaveConfiguration();
}
strcpy(mess,"dummy message");
strcpy(lastClientIP,"none");