detectors/slsDetectorPackage
24
1
Fork 0
mirror of https://github.com/slsdetectorgroup/slsDetectorPackage.git synced 2026-05-02 02:02:25 +02:00
Code Issues Actions Packages Releases Activity

dont allow raw ints, doubles and implicit conversions

Browse Source
This commit is contained in:
maliakal_d
2026-04-16 16:24:42 +02:00
parent f925c5b1a6
commit fa7187a7e2
3 changed files with 41 additions and 59 deletions
Download Patch File Download Diff File Expand all files Collapse all files
python/slsdet/detector.py
+28 -46
View File
@@ -3521,26 +3521,20 @@ class Detector(CppDetectorApi):
@element
def runclk(self):
"""
[Ctb][Xilinx Ctb] Sets Run clock frequency in MHz. \n
Accepts decimal inputs
"""
[Ctb][Xilinx Ctb] Sets Run clock frequency.
Example
--------
>>> d.runclk
>>> 10MHz
>>> d.runclk = MHz(5)
>>> d.runclk = Hz(5 * 1000 * 1000)
>>> d.runclk = kHz(2000)
"""
return self.getRUNClock()
'''
freq_hz = element_if_equal(self.getRUNClock())
if isinstance(freq_hz, list):
return [value / 1e6 for value in freq_hz]
return freq_hz / 1e6
'''
@runclk.setter
def runclk(self, freq):
'''
if isinstance(freq, dict):
freq_hz = {key: int(round(value * 1e6)) for key, value in freq.items()}
else:
freq_hz = int(round(freq * 1e6))
'''
ut.set_using_dict(self.setRUNClock, freq)
@property
@@ -3618,26 +3612,20 @@ class Detector(CppDetectorApi):
@element
def dbitclk(self):
"""
[Ctb][Xilinx Ctb] Sets clock for latching the digital bits in MHz. \n
Accepts decimal inputs
[Ctb][Xilinx Ctb] Sets clock for latching the digital bits.
Example
--------
>>> d.dbitclk
>>> 10MHz
>>> d.dbitclk = MHz(5)
>>> d.dbitclk = Hz(5 * 1000 * 1000)
>>> d.dbitclk = kHz(2000)
"""
'''
freq_hz = element_if_equal(self.getDBITClock())
if isinstance(freq_hz, list):
return [value / 1e6 for value in freq_hz]
return freq_hz / 1e6
'''
return self.getDBITClock()
@dbitclk.setter
def dbitclk(self, value):
'''
if isinstance(value, dict):
value_hz = {key: int(round(item * 1e6)) for key, item in value.items()}
else:
value_hz = int(round(value * 1e6))
ut.set_using_dict(self.setDBITClock, value_hz)
'''
ut.set_using_dict(self.setDBITClock, value)
@property
@@ -3761,33 +3749,27 @@ class Detector(CppDetectorApi):
@element
def adcclk(self):
"""
[Ctb][Xilinx Ctb] Sets ADC clock frequency in MHz. \n
Accepts decimal inputs
[Ctb][Xilinx Ctb] Sets ADC clock frequency.
Example
--------
>>> d.adcclk
>>> 10MHz
>>> d.adcclk = MHz(5)
>>> d.adcclk = Hz(5 * 1000 * 1000)
>>> d.adcclk = kHz(2000)
"""
'''
freq_hz = element_if_equal(self.getADCClock())
if isinstance(freq_hz, list):
return [value / 1e6 for value in freq_hz]
return freq_hz / 1e6
'''
return self.getADCClock()
@adcclk.setter
def adcclk(self, value):
'''
if isinstance(value, dict):
value_hz = {key: int(round(item * 1e6)) for key, item in value.items()}
else:
value_hz = int(round(value * 1e6))
ut.set_using_dict(self.setADCClock, value_hz)
'''
ut.set_using_dict(self.setADCClock, value)
@property
@element
def syncclk(self):
"""
[Ctb] Sync clock in MHz.
[Ctb] Sync clock.
:setter: Not implemented
"""
python/src/frequency.cpp
-5
View File
@@ -18,9 +18,6 @@ void init_freq(py::module &m) {
py::class_<slsDetectorDefs::Hz> Hz(m, "Hz");
Hz.def(py::init<int>());
Hz.def(py::init([](double v) {
return slsDetectorDefs::Hz(static_cast<int>(std::round(v)));
}));
Hz.def_readwrite("value", &slsDetectorDefs::Hz::value);
Hz.def("__repr__", [](const slsDetectorDefs::Hz &f) {
return sls::ToString(f);
@@ -36,6 +33,4 @@ void init_freq(py::module &m) {
m.def("MHz", [](double v) {
return slsDetectorDefs::Hz(static_cast<int>(std::round(v * MHz)));
});
py::implicitly_convertible<int, slsDetectorDefs::Hz>();
py::implicitly_convertible<double, slsDetectorDefs::Hz>();
}