diff --git a/python/slsdet/detector.py b/python/slsdet/detector.py
index c993e2948..40502e287 100755
--- a/python/slsdet/detector.py
+++ b/python/slsdet/detector.py
@@ -3521,26 +3521,20 @@ class Detector(CppDetectorApi):
     @element
     def runclk(self):
         """
-        [Ctb][Xilinx Ctb] Sets Run clock frequency in MHz. \n
-        Accepts decimal inputs
-        """
+        [Ctb][Xilinx Ctb] Sets Run clock frequency.
 
+        Example
+        --------
+        >>> d.runclk
+        >>> 10MHz
+        >>> d.runclk = MHz(5)
+        >>> d.runclk = Hz(5 * 1000 * 1000)
+        >>> d.runclk = kHz(2000)
+        """
         return self.getRUNClock()
-        '''
-        freq_hz = element_if_equal(self.getRUNClock())
-        if isinstance(freq_hz, list):
-            return [value / 1e6 for value in freq_hz]
-        return freq_hz / 1e6
-        '''
 
     @runclk.setter
     def runclk(self, freq):
-        '''
-        if isinstance(freq, dict):
-            freq_hz = {key: int(round(value * 1e6)) for key, value in freq.items()}
-        else:
-            freq_hz = int(round(freq * 1e6))
-        '''
         ut.set_using_dict(self.setRUNClock, freq) 
 
     @property
@@ -3618,26 +3612,20 @@ class Detector(CppDetectorApi):
     @element
     def dbitclk(self):
         """
-        [Ctb][Xilinx Ctb] Sets clock for latching the digital bits in MHz. \n
-        Accepts decimal inputs
+        [Ctb][Xilinx Ctb] Sets clock for latching the digital bits.
+
+        Example
+        --------
+        >>> d.dbitclk
+        >>> 10MHz
+        >>> d.dbitclk = MHz(5)
+        >>> d.dbitclk = Hz(5 * 1000 * 1000)
+        >>> d.dbitclk = kHz(2000)
         """
-        '''
-        freq_hz = element_if_equal(self.getDBITClock())
-        if isinstance(freq_hz, list):
-            return [value / 1e6 for value in freq_hz]
-        return freq_hz / 1e6
-        '''
         return self.getDBITClock()
 
     @dbitclk.setter
     def dbitclk(self, value):
-        '''
-        if isinstance(value, dict):
-            value_hz = {key: int(round(item * 1e6)) for key, item in value.items()}
-        else:
-            value_hz = int(round(value * 1e6))
-        ut.set_using_dict(self.setDBITClock, value_hz)
-        '''
         ut.set_using_dict(self.setDBITClock, value)
 
     @property
@@ -3761,33 +3749,27 @@ class Detector(CppDetectorApi):
     @element
     def adcclk(self):
         """
-        [Ctb][Xilinx Ctb] Sets ADC clock frequency in MHz. \n
-        Accepts decimal inputs
+        [Ctb][Xilinx Ctb] Sets ADC clock frequency.
+
+        Example
+        --------
+        >>> d.adcclk
+        >>> 10MHz
+        >>> d.adcclk = MHz(5)
+        >>> d.adcclk = Hz(5 * 1000 * 1000)
+        >>> d.adcclk = kHz(2000)
         """
-        '''
-        freq_hz = element_if_equal(self.getADCClock())
-        if isinstance(freq_hz, list):
-            return [value / 1e6 for value in freq_hz]
-        return freq_hz / 1e6
-        '''
         return self.getADCClock()
 
     @adcclk.setter
     def adcclk(self, value):
-        '''
-        if isinstance(value, dict):
-            value_hz = {key: int(round(item * 1e6)) for key, item in value.items()}
-        else:
-            value_hz = int(round(value * 1e6))
-        ut.set_using_dict(self.setADCClock, value_hz)
-        '''
         ut.set_using_dict(self.setADCClock, value)
 
     @property
     @element
     def syncclk(self):
         """
-        [Ctb] Sync clock in MHz.
+        [Ctb] Sync clock.
         
         :setter: Not implemented
         """
diff --git a/python/src/frequency.cpp b/python/src/frequency.cpp
index 792ebf302..5cbf30cfb 100644
--- a/python/src/frequency.cpp
+++ b/python/src/frequency.cpp
@@ -18,9 +18,6 @@ void init_freq(py::module &m) {
 
     py::class_<slsDetectorDefs::Hz> Hz(m, "Hz");
     Hz.def(py::init<int>());
-    Hz.def(py::init([](double v) {
-        return slsDetectorDefs::Hz(static_cast<int>(std::round(v)));
-    }));
     Hz.def_readwrite("value", &slsDetectorDefs::Hz::value);
     Hz.def("__repr__", [](const slsDetectorDefs::Hz &f) { 
         return sls::ToString(f); 
@@ -36,6 +33,4 @@ void init_freq(py::module &m) {
     m.def("MHz", [](double v) {
         return slsDetectorDefs::Hz(static_cast<int>(std::round(v * MHz)));
     });
-    py::implicitly_convertible<int, slsDetectorDefs::Hz>();
-    py::implicitly_convertible<double, slsDetectorDefs::Hz>();
 }
\ No newline at end of file
diff --git a/slsDetectorSoftware/tests/Caller/test-Caller-chiptestboard.cpp b/slsDetectorSoftware/tests/Caller/test-Caller-chiptestboard.cpp
index 035263c8a..0f100b83c 100644
--- a/slsDetectorSoftware/tests/Caller/test-Caller-chiptestboard.cpp
+++ b/slsDetectorSoftware/tests/Caller/test-Caller-chiptestboard.cpp
@@ -719,13 +719,13 @@ TEST_CASE("adcclk", "[.detectorintegration]") {
 
         {
             std::ostringstream oss;
-            caller.call("adcclk", {"20"}, -1, PUT, oss);
-            REQUIRE(oss.str() == "adcclk 20\n");
+            caller.call("adcclk", {"20MHz"}, -1, PUT, oss);
+            REQUIRE(oss.str() == "adcclk 20MHz\n");
         }
         {
             std::ostringstream oss;
-            caller.call("adcclk", {"10"}, -1, PUT, oss);
-            REQUIRE(oss.str() == "adcclk 10\n");
+            caller.call("adcclk", {"10000000"}, -1, PUT, oss);
+            REQUIRE(oss.str() == "adcclk 10000000\n");
         }
 
         {
@@ -835,6 +835,11 @@ TEST_CASE("syncclk", "[.detectorintegration]") {
     Caller caller(&det);
     auto det_type = det.getDetectorType().squash();
     if (det_type == defs::CHIPTESTBOARD) {
+        REQUIRE_NOTHROW(caller.call("syncclk", {"MHZ"}, -1, GET));
+        REQUIRE_NOTHROW(caller.call("syncclk", {"mhz"}, -1, GET));
+        REQUIRE_NOTHROW(caller.call("syncclk", {"MHz"}, -1, GET));
+        REQUIRE_NOTHROW(caller.call("syncclk", {"kHz"}, -1, GET));
+        REQUIRE_NOTHROW(caller.call("syncclk", {"Hz"}, -1, GET));
         REQUIRE_NOTHROW(caller.call("syncclk", {}, -1, GET));
     } else {
         // clock index might work
@@ -1121,13 +1126,13 @@ TEST_CASE("dbitclk", "[.detectorintegration]") {
 
         {
             std::ostringstream oss;
-            caller.call("dbitclk", {"20"}, -1, PUT, oss);
-            REQUIRE(oss.str() == "dbitclk 20\n");
+            caller.call("dbitclk", {"20MHz"}, -1, PUT, oss);
+            REQUIRE(oss.str() == "dbitclk 20MHz\n");
         }
         {
             std::ostringstream oss;
-            caller.call("dbitclk", {"10"}, -1, PUT, oss);
-            REQUIRE(oss.str() == "dbitclk 10\n");
+            caller.call("dbitclk", {"10000000"}, -1, PUT, oss);
+            REQUIRE(oss.str() == "dbitclk 10000000\n");
         }
 
         {