mirror of
https://github.com/slsdetectorgroup/slsDetectorPackage.git
synced 2025-06-07 18:40:42 +02:00
mannnnyyyy changes to jungfrau serverin structure, also to eiger structure a bit
This commit is contained in:
Dhanya Maliakal
parent
046ac97a9b
commit
f74710998d
@ -83,6 +83,191 @@ int normal = 0;
|
||||
#define ONE_GIGA_BUFFER_SIZE 1040
|
||||
|
||||
|
||||
void checkFirmwareCompatibility(){
|
||||
int64_t fwversion = getDetectorId(DETECTOR_FIRMWARE_VERSION);
|
||||
int64_t swversion = getDetectorId(DETECTOR_SOFTWARE_VERSION);
|
||||
int64_t sw_fw_apiversion = getDetectorId(SOFTWARE_FIRMWARE_API_VERSION);
|
||||
|
||||
cprintf(BLUE,"\n\n********************************************************\n"
|
||||
"**********************EIGER Server**********************\n"
|
||||
"********************************************************\n");
|
||||
cprintf(BLUE,"\n"
|
||||
"Firmware Version:\t\t %lld\n"
|
||||
"Software Version:\t\t %llx\n"
|
||||
"F/w-S/w API Version:\t\t %lld\n"
|
||||
"Required Firmware Version:\t %d\n"
|
||||
"\n********************************************************\n",
|
||||
fwversion,swversion,sw_fw_apiversion,REQUIRED_FIRMWARE_VERSION);
|
||||
|
||||
//cant read versions
|
||||
if(!fwversion || !sw_fw_apiversion){
|
||||
cprintf(RED,"FATAL ERROR: Cant read versions from FPGA. Please update firmware\n");
|
||||
cprintf(RED,"Exiting Server. Goodbye!\n\n");
|
||||
exit(-1);
|
||||
}
|
||||
|
||||
//check for API compatibility - old server
|
||||
if(sw_fw_apiversion > REQUIRED_FIRMWARE_VERSION){
|
||||
cprintf(RED,"FATAL ERROR: This software version is incompatible.\n"
|
||||
"Please update it to be compatible with this firmware\n\n");
|
||||
cprintf(RED,"Exiting Server. Goodbye!\n\n");
|
||||
exit(-1);
|
||||
}
|
||||
|
||||
//check for firmware compatibility - old firmware
|
||||
if( REQUIRED_FIRMWARE_VERSION > fwversion){
|
||||
cprintf(RED,"FATAL ERROR: This firmware version is incompatible.\n"
|
||||
"Please update it to v%d to be compatible with this server\n\n", REQUIRED_FIRMWARE_VERSION);
|
||||
cprintf(RED,"Exiting Server. Goodbye!\n\n");
|
||||
exit(-1);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
int moduleTest( enum digitalTestMode arg, int imod){
|
||||
//template testShiftIn from mcb_funcs.c
|
||||
|
||||
//CHIP_TEST
|
||||
//testShiftIn
|
||||
//testShiftOut
|
||||
//testShiftStSel
|
||||
//testDataInOutMux
|
||||
//testExtPulseMux
|
||||
//testOutMux
|
||||
//testFpgaMux
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
int detectorTest( enum digitalTestMode arg){
|
||||
//templates from firmware_funcs.c
|
||||
|
||||
//DETECTOR_FIRMWARE_TEST:testFpga()
|
||||
//DETECTOR_MEMORY_TEST:testRAM()
|
||||
//DETECTOR_BUS_TEST:testBus()
|
||||
//DETECTOR_SOFTWARE_TEST:testFpga()
|
||||
return OK;
|
||||
}
|
||||
|
||||
|
||||
int64_t getDetectorId(enum idMode arg){
|
||||
int64_t retval = -1;
|
||||
|
||||
switch(arg){
|
||||
case DETECTOR_SERIAL_NUMBER:
|
||||
retval = getDetectorNumber();/** to be implemented with mac? */
|
||||
break;
|
||||
case DETECTOR_FIRMWARE_VERSION:
|
||||
return (int64_t)getFirmwareVersion();
|
||||
case SOFTWARE_FIRMWARE_API_VERSION:
|
||||
return (int64_t)Beb_GetFirmwareSoftwareAPIVersion();
|
||||
case DETECTOR_SOFTWARE_VERSION:
|
||||
retval= SVNREV;
|
||||
retval= (retval <<32) | SVNDATE;
|
||||
//cprintf(BLUE,"git date:%x, git rev:%x\n",SVNDATE,SVNREV);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
u_int64_t getFirmwareVersion() {
|
||||
return Beb_GetFirmwareRevision();
|
||||
}
|
||||
|
||||
int64_t getModuleId(enum idMode arg, int imod){
|
||||
|
||||
/**/
|
||||
return -1;
|
||||
}
|
||||
|
||||
|
||||
int getDetectorNumber(){
|
||||
int res=0;
|
||||
|
||||
//execute and get address
|
||||
char output[255];
|
||||
FILE* sysFile = popen("more /home/root/executables/detid.txt", "r");
|
||||
fgets(output, sizeof(output), sysFile);
|
||||
pclose(sysFile);
|
||||
sscanf(output,"%d",&res);
|
||||
printf("detector id: %d\n",res);
|
||||
|
||||
/*
|
||||
int res=0;
|
||||
char hostname[100];
|
||||
if (gethostname(hostname, sizeof hostname) == 0)
|
||||
puts(hostname);
|
||||
else
|
||||
perror("gethostname");
|
||||
sscanf(hostname,"%x",&res);
|
||||
*/
|
||||
return res;
|
||||
}
|
||||
|
||||
|
||||
u_int64_t getDetectorMAC() {
|
||||
char mac[255]="";
|
||||
u_int64_t res=0;
|
||||
|
||||
//execute and get address
|
||||
char output[255];
|
||||
FILE* sysFile = popen("more /sys/class/net/eth0/address", "r");
|
||||
//FILE* sysFile = popen("ifconfig eth0 | grep HWaddr | cut -d \" \" -f 11", "r");
|
||||
fgets(output, sizeof(output), sysFile);
|
||||
pclose(sysFile);
|
||||
|
||||
//getting rid of ":"
|
||||
char * pch;
|
||||
pch = strtok (output,":");
|
||||
while (pch != NULL){
|
||||
strcat(mac,pch);
|
||||
pch = strtok (NULL, ":");
|
||||
}
|
||||
sscanf(mac,"%llx",&res);
|
||||
//increment by 1 for 10g
|
||||
if(send_to_ten_gig)
|
||||
res++;
|
||||
//printf("mac:%llx\n",res);
|
||||
|
||||
return res;
|
||||
}
|
||||
|
||||
|
||||
|
||||
int getDetectorIP(){
|
||||
char temp[50]="";
|
||||
int res=0;
|
||||
//execute and get address
|
||||
char output[255];
|
||||
FILE* sysFile = popen("ifconfig | grep 'inet addr:'| grep -v '127.0.0.1' | cut -d: -f2", "r");
|
||||
fgets(output, sizeof(output), sysFile);
|
||||
pclose(sysFile);
|
||||
|
||||
//converting IPaddress to hex.
|
||||
char* pcword = strtok (output,".");
|
||||
while (pcword != NULL) {
|
||||
sprintf(output,"%02x",atoi(pcword));
|
||||
strcat(temp,output);
|
||||
pcword = strtok (NULL, ".");
|
||||
}
|
||||
strcpy(output,temp);
|
||||
sscanf(output, "%x", &res);
|
||||
//printf("ip:%x\n",res);
|
||||
|
||||
return res;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
int initDetector(){
|
||||
int imod,i,n;
|
||||
n = getNModBoard(1);
|
||||
@ -216,148 +401,10 @@ int getNModBoard(enum dimension arg){
|
||||
|
||||
|
||||
|
||||
int64_t getModuleId(enum idMode arg, int imod){
|
||||
|
||||
/**/
|
||||
return -1;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
int64_t getDetectorId(enum idMode arg){
|
||||
int64_t retval = -1;
|
||||
|
||||
switch(arg){
|
||||
case DETECTOR_SERIAL_NUMBER:
|
||||
retval = getDetectorNumber();/** to be implemented with mac? */
|
||||
break;
|
||||
case DETECTOR_FIRMWARE_VERSION:
|
||||
return (int64_t)Beb_GetFirmwareRevision();
|
||||
case SOFTWARE_FIRMWARE_API_VERSION:
|
||||
return (int64_t)Beb_GetFirmwareSoftwareAPIVersion();
|
||||
case DETECTOR_SOFTWARE_VERSION:
|
||||
retval= SVNREV;
|
||||
retval= (retval <<32) | SVNDATE;
|
||||
//cprintf(BLUE,"git date:%x, git rev:%x\n",SVNDATE,SVNREV);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
|
||||
|
||||
int getDetectorNumber(){
|
||||
int res=0;
|
||||
|
||||
//execute and get address
|
||||
char output[255];
|
||||
FILE* sysFile = popen("more /home/root/executables/detid.txt", "r");
|
||||
fgets(output, sizeof(output), sysFile);
|
||||
pclose(sysFile);
|
||||
sscanf(output,"%d",&res);
|
||||
printf("detector id: %d\n",res);
|
||||
|
||||
/*
|
||||
int res=0;
|
||||
char hostname[100];
|
||||
if (gethostname(hostname, sizeof hostname) == 0)
|
||||
puts(hostname);
|
||||
else
|
||||
perror("gethostname");
|
||||
sscanf(hostname,"%x",&res);
|
||||
*/
|
||||
return res;
|
||||
}
|
||||
|
||||
|
||||
u_int64_t getDetectorMAC() {
|
||||
char mac[255]="";
|
||||
u_int64_t res=0;
|
||||
|
||||
//execute and get address
|
||||
char output[255];
|
||||
FILE* sysFile = popen("more /sys/class/net/eth0/address", "r");
|
||||
//FILE* sysFile = popen("ifconfig eth0 | grep HWaddr | cut -d \" \" -f 11", "r");
|
||||
fgets(output, sizeof(output), sysFile);
|
||||
pclose(sysFile);
|
||||
|
||||
//getting rid of ":"
|
||||
char * pch;
|
||||
pch = strtok (output,":");
|
||||
while (pch != NULL){
|
||||
strcat(mac,pch);
|
||||
pch = strtok (NULL, ":");
|
||||
}
|
||||
sscanf(mac,"%llx",&res);
|
||||
//increment by 1 for 10g
|
||||
if(send_to_ten_gig)
|
||||
res++;
|
||||
//printf("mac:%llx\n",res);
|
||||
|
||||
return res;
|
||||
}
|
||||
|
||||
|
||||
|
||||
int getDetectorIP(){
|
||||
char temp[50]="";
|
||||
int res=0;
|
||||
//execute and get address
|
||||
char output[255];
|
||||
FILE* sysFile = popen("ifconfig | grep 'inet addr:'| grep -v '127.0.0.1' | cut -d: -f2", "r");
|
||||
fgets(output, sizeof(output), sysFile);
|
||||
pclose(sysFile);
|
||||
|
||||
//converting IPaddress to hex.
|
||||
char* pcword = strtok (output,".");
|
||||
while (pcword != NULL) {
|
||||
sprintf(output,"%02x",atoi(pcword));
|
||||
strcat(temp,output);
|
||||
pcword = strtok (NULL, ".");
|
||||
}
|
||||
strcpy(output,temp);
|
||||
sscanf(output, "%x", &res);
|
||||
//printf("ip:%x\n",res);
|
||||
|
||||
return res;
|
||||
}
|
||||
|
||||
|
||||
|
||||
int moduleTest( enum digitalTestMode arg, int imod){
|
||||
//template testShiftIn from mcb_funcs.c
|
||||
|
||||
//CHIP_TEST
|
||||
//testShiftIn
|
||||
//testShiftOut
|
||||
//testShiftStSel
|
||||
//testDataInOutMux
|
||||
//testExtPulseMux
|
||||
//testOutMux
|
||||
//testFpgaMux
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
int detectorTest( enum digitalTestMode arg){
|
||||
//templates from firmware_funcs.c
|
||||
|
||||
//DETECTOR_FIRMWARE_TEST:testFpga()
|
||||
//DETECTOR_MEMORY_TEST:testRAM()
|
||||
//DETECTOR_BUS_TEST:testBus()
|
||||
//DETECTOR_SOFTWARE_TEST:testFpga()
|
||||
return OK;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
@ -6,7 +6,7 @@
|
||||
CROSS = bfin-uclinux-
|
||||
CC = $(CROSS)gcc
|
||||
|
||||
CFLAGS += -Wall -DJUNGFRAUD -DMCB_FUNCS -DDACS_INT -DDEBUG -DV1 #-DVERBOSE #-DVERYVERBOSE #-DVIRTUAL
|
||||
CFLAGS += -Wall -DJUNGFRAUD -DMCB_FUNCS -DDACS_INT #-DVERBOSE #-DVERYVERBOSE #-DVIRTUAL
|
||||
|
||||
|
||||
PROGS= jungfrauDetectorServer
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -48,7 +48,7 @@ int stopWritingFPGAprogram(FILE* filefp);
|
||||
int writeFPGAProgram(char* fpgasrc, size_t fsize, FILE* filefp);
|
||||
|
||||
long int calcChecksum(int sourceip, int destip);
|
||||
void configureMAC(uint32_t destip, uint64_t destmac, uint64_t sourcemac, int detipad, uint32_t destport);
|
||||
void configureMAC(uint32_t destip, uint64_t destmac, uint64_t sourcemac, int sourceip, uint32_t destport);
|
||||
|
||||
int64_t set64BitReg(int64_t value, int aLSB, int aMSB);
|
||||
int64_t get64BitReg(int aLSB, int aMSB);
|
||||
@ -74,9 +74,6 @@ int64_t getTrains();
|
||||
int64_t setProbes(int64_t value);
|
||||
int64_t getProbes();
|
||||
|
||||
int64_t getProgress();
|
||||
int64_t setProgress();
|
||||
|
||||
int64_t getActualTime();
|
||||
int64_t getMeasurementTime();
|
||||
int64_t getFramesFromStart();
|
||||
@ -84,7 +81,6 @@ int64_t getFramesFromStart();
|
||||
u_int32_t runBusy(void);
|
||||
int startStateMachine();
|
||||
int stopStateMachine();
|
||||
int startReadOut();
|
||||
enum runStatus getStatus();
|
||||
void waitForAcquisitionEnd();
|
||||
|
||||
@ -93,7 +89,6 @@ void initDac(int dacnum);
|
||||
int setDac(int dacnum, int dacvalue);
|
||||
int setHighVoltage(int val, int imod);
|
||||
void setAdc(int addr, int val);
|
||||
void configureAdc();
|
||||
void prepareADC();
|
||||
|
||||
int setDynamicRange(int dr);
|
||||
@ -117,8 +112,7 @@ int initConfGain(int isettings,int val,int imod);
|
||||
int initSpeedConfGain(int val);
|
||||
|
||||
void resetPLL();
|
||||
u_int32_t setPllReconfigReg(u_int32_t reg, u_int32_t val, int trig);
|
||||
u_int32_t getPllReconfigReg(u_int32_t reg, int trig);
|
||||
u_int32_t setPllReconfigReg(u_int32_t reg, u_int32_t val);
|
||||
void configurePll();
|
||||
|
||||
int loadImage(int index, short int ImageVals[]);
|
||||
@ -126,10 +120,6 @@ int readCounterBlock(int startACQ, short int CounterVals[]);
|
||||
int resetCounterBlock(int startACQ);
|
||||
int calibratePedestal(int frames);
|
||||
|
||||
u_int32_t setExtSignal(int d, enum externalSignalFlag mode);
|
||||
int getExtSignal(int d);
|
||||
u_int32_t setFPGASignal(int d, enum externalSignalFlag mode);
|
||||
int getFPGASignal(int d);
|
||||
int setTiming(int t);
|
||||
int setMaster(int f);
|
||||
int setSynchronization(int s);
|
||||
|
||||
@ -176,19 +176,24 @@
|
||||
#define TX_IP_CHECKSUM_MSK (0x000000FF << TX_IP_CHECKSUM_OFST)
|
||||
|
||||
/* Configuration Register */
|
||||
#define CONFIG_REG (0x4D << 11) //Not used in software Carlos
|
||||
#define CONFIG_REG (0x4D << 11)
|
||||
|
||||
#define CONFIG_OPERATION_MODE_OFST (16) //Not used in software
|
||||
#define CONFIG_OPERATION_MODE_MSK (0x00000001 << CONFIG_OPERATION_MODE_OFST) //Not used in software
|
||||
#define CONFIG_READOUT_SPEED_OFST (20) //Not used in software
|
||||
#define CONFIG_READOUT_SPEED_MSK (0x00000003 << CONFIG_READOUT_SPEED_OFST) //Not used in software
|
||||
#define CONFIG_QUARTER_SPEED_10MHZ_VAL (0x0 << CONFIG_READOUT_SPEED_OFST) & CONFIG_READOUT_SPEED_MSK //Not used in software
|
||||
#define CONFIG_HALF_SPEED_20MHZ_VAL (0x1 << CONFIG_READOUT_SPEED_OFST) & CONFIG_READOUT_SPEED_MSK //Not used in software
|
||||
#define CONFIG_FULL_SPEED_VAL (0x2 << CONFIG_READOUT_SPEED_OFST) & CONFIG_READOUT_SPEED_MSK //Not used in software and firmware
|
||||
#define CONFIG_TDMA_OFST (24) //Not used in software
|
||||
#define CONFIG_TDMA_MSK (0x00000001 << CONFIG_TDMA_OFST) //Not used in software
|
||||
#define CONFIG_TDMA_TIMESLOT_OFST (25) //Not used in software
|
||||
#define CONFIG_TDMA_TIMESLOT_MSK (0x0000001F << CONFIG_TDMA_TIMESLOT_OFST) //Not used in software
|
||||
#define CONFIG_OPERATION_MODE_OFST (16)
|
||||
#define CONFIG_OPERATION_MODE_MSK (0x00000001 << CONFIG_OPERATION_MODE_OFST)
|
||||
#define CONFIG_MODE_1_X_10GBE_VAL ((0x0 << CONFIG_OPERATION_MODE_OFST) & CONFIG_OPERATION_MODE_MSK)
|
||||
#define CONFIG_MODE_2_X_10GBE_VAL ((0x1 << CONFIG_OPERATION_MODE_OFST) & CONFIG_OPERATION_MODE_MSK)
|
||||
#define CONFIG_READOUT_SPEED_OFST (20)
|
||||
#define CONFIG_READOUT_SPEED_MSK (0x00000003 << CONFIG_READOUT_SPEED_OFST)
|
||||
#define CONFIG_QUARTER_SPEED_10MHZ_VAL ((0x0 << CONFIG_READOUT_SPEED_OFST) & CONFIG_READOUT_SPEED_MSK)
|
||||
#define CONFIG_HALF_SPEED_20MHZ_VAL ((0x1 << CONFIG_READOUT_SPEED_OFST) & CONFIG_READOUT_SPEED_MSK)
|
||||
#define CONFIG_FULL_SPEED_VAL ((0x2 << CONFIG_READOUT_SPEED_OFST) & CONFIG_READOUT_SPEED_MSK)
|
||||
#define CONFIG_TDMA_OFST (24)
|
||||
#define CONFIG_TDMA_MSK (0x00000001 << CONFIG_TDMA_OFST)
|
||||
#define CONFIG_TDMA_DISABLE_VAL ((0x0 << CONFIG_TDMA_OFST) & CONFIG_TDMA_MSK)
|
||||
#define CONFIG_TDMA_ENABLE_VAL ((0x1 << CONFIG_TDMA_OFST) & CONFIG_TDMA_MSK)
|
||||
#define CONFIG_TDMA_TIMESLOT_OFST (25)
|
||||
#define CONFIG_TDMA_TIMESLOT_MSK (0x0000001F << CONFIG_TDMA_TIMESLOT_OFST)
|
||||
#define CONFIG_TDMA_TIMESLOT_0_VAL ((0x0 << CONFIG_TDMA_TIMESLOT_OFST) & CONFIG_TDMA_TIMESLOT_MSK)
|
||||
|
||||
/* External Signal Register */
|
||||
#define EXT_SIGNAL_REG (0x4E << 11)
|
||||
@ -228,28 +233,54 @@
|
||||
#define PLL_CTRL_ADDR_MSK (0x0000003F << PLL_CTRL_ADDR_OFST)
|
||||
|
||||
/* Sample Register (Obsolete) */
|
||||
#define SAMPLE_REG (0x59 << 11)/** is it dbit pipeline?... look at speedvariable */
|
||||
#define SAMPLE_REG (0x59 << 11) /** carlos set speed differently*/
|
||||
|
||||
#define SAMPLE_ADC_SAMPLE_SEL_OFST (0) /** carlos cant use the bits*/
|
||||
#define SAMPLE_ADC_SAMPLE_SEL_MSK (0x00000007 << SAMPLE_ADC_SAMPLE_SEL_OFST)
|
||||
#define SAMPLE_ADC_SAMPLE_0_VAL ((0x0 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
|
||||
#define SAMPLE_ADC_SAMPLE_1_VAL ((0x1 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
|
||||
#define SAMPLE_ADC_SAMPLE_2_VAL ((0x2 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
|
||||
#define SAMPLE_ADC_SAMPLE_3_VAL ((0x3 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
|
||||
#define SAMPLE_ADC_SAMPLE_4_VAL ((0x4 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
|
||||
#define SAMPLE_ADC_SAMPLE_5_VAL ((0x5 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
|
||||
#define SAMPLE_ADC_SAMPLE_6_VAL ((0x6 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
|
||||
#define SAMPLE_ADC_SAMPLE_7_VAL ((0x7 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
|
||||
|
||||
#define SAMPLE_ADC_DECMT_FACTOR_OFST (4)
|
||||
#define SAMPLE_ADC_DECMT_FACTOR_MSK (0x00000007 << SAMPLE_ADC_DECMT_FACTOR_OFST)
|
||||
#define SAMPLE_ADC_DECMT_FACTOR_0_VAL ((0x0 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
|
||||
#define SAMPLE_ADC_DECMT_FACTOR_1_VAL ((0x1 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
|
||||
#define SAMPLE_ADC_DECMT_FACTOR_2_VAL ((0x2 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
|
||||
#define SAMPLE_ADC_DECMT_FACTOR_3_VAL ((0x3 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
|
||||
#define SAMPLE_ADC_DECMT_FACTOR_4_VAL ((0x4 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
|
||||
#define SAMPLE_ADC_DECMT_FACTOR_5_VAL ((0x5 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
|
||||
#define SAMPLE_ADC_DECMT_FACTOR_6_VAL ((0x6 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
|
||||
#define SAMPLE_ADC_DECMT_FACTOR_7_VAL ((0x7 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
|
||||
|
||||
#define SAMPLE_DGTL_SAMPLE_SEL_OFST (8)
|
||||
#define SAMPLE_DGTL_SAMPLE_SEL_MSK (0x00000007 << SAMPLE_DGTL_SAMPLE_SEL_OFST)
|
||||
#define SAMPLE_DGTL_SAMPLE_SEL_MSK (0x0000000F << SAMPLE_DGTL_SAMPLE_SEL_OFST)
|
||||
#define SAMPLE_DGTL_SAMPLE_0_VAL ((0x0 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
|
||||
#define SAMPLE_DGTL_SAMPLE_1_VAL ((0x1 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
|
||||
#define SAMPLE_DGTL_SAMPLE_2_VAL ((0x2 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
|
||||
#define SAMPLE_DGTL_SAMPLE_3_VAL ((0x3 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
|
||||
#define SAMPLE_DGTL_SAMPLE_4_VAL ((0x4 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
|
||||
#define SAMPLE_DGTL_SAMPLE_5_VAL ((0x5 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
|
||||
#define SAMPLE_DGTL_SAMPLE_6_VAL ((0x6 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
|
||||
#define SAMPLE_DGTL_SAMPLE_7_VAL ((0x7 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
|
||||
#define SAMPLE_DGTL_SAMPLE_8_VAL ((0x8 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
|
||||
#define SAMPLE_DGTL_SAMPLE_9_VAL ((0x9 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
|
||||
#define SAMPLE_DGTL_SAMPLE_10_VAL ((0xa << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
|
||||
#define SAMPLE_DGTL_SAMPLE_11_VAL ((0xb << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
|
||||
#define SAMPLE_DGTL_SAMPLE_12_VAL ((0xc << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
|
||||
#define SAMPLE_DGTL_SAMPLE_13_VAL ((0xd << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
|
||||
#define SAMPLE_DGTL_SAMPLE_14_VAL ((0xe << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
|
||||
#define SAMPLE_DGTL_SAMPLE_15_VAL ((0xf << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
|
||||
|
||||
#define SAMPLE_DGTL_DECMT_FACTOR_OFST (12)
|
||||
#define SAMPLE_DGTL_DECMT_FACTOR_MSK (0x00000007 << SAMPLE_DGTL_DECMT_FACTOR_OFST)
|
||||
|
||||
/* Digital Bit Alignment Register (Obsolete) */
|
||||
#define BIT_ALIGN_REG (0x59 << 11)/** carlos same reg value */
|
||||
|
||||
#define BIT_ALIGN_LSB_SAMPLE_SEL_OFST (0)
|
||||
#define BIT_ALIGN_LSB_SAMPLE_SEL_MSK (0x00000007 << BIT_ALIGN_LSB_SAMPLE_SEL_OFST)
|
||||
#define BIT_ALIGN_LSB_LATENCY_OFST (3)
|
||||
#define BIT_ALIGN_LSB_LATENCY_MSK (0x0000001F << BIT_ALIGN_LSB_LATENCY_OFST)
|
||||
#define BIT_ALIGN_MSB_SAMPLE_SEL_OFST (8)
|
||||
#define BIT_ALIGN_MSB_SAMPLE_SEL_MSK (0x00000007 << BIT_ALIGN_MSB_SAMPLE_SEL_OFST)
|
||||
#define BIT_ALIGN_MSB_LATENCY_OFST (11)
|
||||
#define BIT_ALIGN_MSB_LATENCY_MSK (0x0000001F << BIT_ALIGN_MSB_LATENCY_OFST)
|
||||
#define SAMPLE_DGTL_DECMT_FACTOR_MSK (0x00000003 << SAMPLE_DGTL_DECMT_FACTOR_OFST)
|
||||
#define SAMPLE_DECMT_FACTOR_1_VAL ((0x0 << SAMPLE_DGTL_DECMT_FACTOR_OFST) & SAMPLE_DGTL_DECMT_FACTOR_MSK)
|
||||
#define SAMPLE_DECMT_FACTOR_2_VAL ((0x1 << SAMPLE_DGTL_DECMT_FACTOR_OFST) & SAMPLE_DGTL_DECMT_FACTOR_MSK)
|
||||
#define SAMPLE_DECMT_FACTOR_4_VAL ((0x2 << SAMPLE_DGTL_DECMT_FACTOR_OFST) & SAMPLE_DGTL_DECMT_FACTOR_MSK)
|
||||
|
||||
/** Vref Comp Mod Register */
|
||||
#define VREF_COMP_MOD_REG (0x5C << 11) //Not used in software, TBD in firmware
|
||||
@ -318,20 +349,6 @@
|
||||
#define SET_GATES_LSB_REG 106<<11//0x7c<<11
|
||||
#define SET_GATES_MSB_REG 107<<11//0x7d<<11
|
||||
|
||||
#define PLL_RECONFIG_BUSY 0x00100000
|
||||
|
||||
/* for external signal register */ /** Carlos is this implemented?*/
|
||||
#define SIGNAL_OFFSET 4
|
||||
#define SIGNAL_MASK 0xF
|
||||
#define EXT_SIG_OFF 0x0
|
||||
#define EXT_GATE_IN_ACTIVEHIGH 0x1
|
||||
#define EXT_GATE_IN_ACTIVELOW 0x2
|
||||
#define EXT_TRIG_IN_RISING 0x3
|
||||
#define EXT_TRIG_IN_FALLING 0x4
|
||||
//...
|
||||
|
||||
|
||||
|
||||
|
||||
/**ADC SYNC CLEAN FIFO*/
|
||||
#define ADCSYNC_CLEAN_FIFO_BITS 0x300000
|
||||
|
||||
@ -39,9 +39,8 @@ const enum detectorType myDetectorType=GENERIC;
|
||||
int (*flist[256])(int);
|
||||
char mess[MAX_STR_LENGTH];
|
||||
|
||||
int digitalTestBit = 0; /** Carlos will we use this somewhere */
|
||||
int adcvpp = 0x4; /** Carlos will we use this somewhere */
|
||||
|
||||
//set adc val??
|
||||
|
||||
|
||||
|
||||
@ -609,7 +608,7 @@ int digital_test(int file_des) {
|
||||
case DETECTOR_SOFTWARE_TEST:
|
||||
retval=testFpga();
|
||||
break;
|
||||
case DIGITAL_BIT_TEST:
|
||||
case DIGITAL_BIT_TEST:// only for gotthard
|
||||
n = receiveDataOnly(file_des,&ival,sizeof(ival));
|
||||
if (n < 0) {
|
||||
sprintf(mess,"Error reading from socket\n");
|
||||
@ -623,8 +622,6 @@ int digital_test(int file_des) {
|
||||
sprintf(mess,"Detector locked by %s\n",lastClientIP);
|
||||
break;
|
||||
}
|
||||
digitalTestBit = ival;
|
||||
retval=digitalTestBit;
|
||||
break;
|
||||
default:
|
||||
printf("Unknown digital test required %d\n",arg);
|
||||
@ -687,14 +684,8 @@ int write_register(int file_des) {
|
||||
|
||||
if(ret!=FAIL){
|
||||
address=(addr<<11);
|
||||
/*if((address==FIFO_DATA_REG_OFF)||(address==CONTROL_REG)) ask Carlos
|
||||
ret = bus_w16(address,val);
|
||||
else*/
|
||||
ret=bus_w(address,val);
|
||||
if(ret==OK){
|
||||
/*if((address==FIFO_DATA_REG_OFF)||(address==CONTROL_REG)) ask Carlos
|
||||
retval=bus_r16(address);
|
||||
else*/
|
||||
retval=bus_r(address);
|
||||
}
|
||||
}
|
||||
@ -753,9 +744,6 @@ int read_register(int file_des) {
|
||||
|
||||
if(ret!=FAIL){
|
||||
address=(addr<<11);
|
||||
/*if((address==FIFO_DATA_REG_OFF)||(address==CONTROL_REG)) ask Carlos
|
||||
retval=bus_r16(address);
|
||||
else*/
|
||||
retval=bus_r(address);
|
||||
}
|
||||
|
||||
@ -1595,26 +1583,11 @@ int stop_acquisition(int file_des) {
|
||||
|
||||
int start_readout(int file_des) {
|
||||
|
||||
|
||||
int ret=OK;
|
||||
int n;
|
||||
int ret = FAIL;
|
||||
|
||||
|
||||
sprintf(mess,"can't start readout\n");
|
||||
|
||||
#ifdef VERBOSE
|
||||
printf("Starting readout\n");
|
||||
#endif
|
||||
if (differentClients==1 && lockStatus==1) {
|
||||
ret=FAIL;
|
||||
sprintf(mess,"Detector locked by %s\n",lastClientIP);
|
||||
} else {
|
||||
ret=startReadOut();
|
||||
}
|
||||
if (ret==FAIL)
|
||||
sprintf(mess,"Start readout failed\n");
|
||||
else if (differentClients)
|
||||
ret=FORCE_UPDATE;
|
||||
strcpy(mess, "Start Readout is not implemented for this detector!\n");
|
||||
cprintf(RED,"Warning: %s", mess);
|
||||
|
||||
n = sendDataOnly(file_des,&ret,sizeof(ret));
|
||||
if (ret==FAIL) {
|
||||
@ -1858,7 +1831,7 @@ int get_time_left(int file_des) {
|
||||
retval=getFrames();
|
||||
break;
|
||||
case ACQUISITION_TIME:
|
||||
retval=getExposureTime();
|
||||
retval=getExposureTime();/** not implemented */
|
||||
break;
|
||||
case FRAME_PERIOD:
|
||||
retval=getPeriod();
|
||||
@ -1867,7 +1840,7 @@ int get_time_left(int file_des) {
|
||||
retval=getDelay();
|
||||
break;
|
||||
case GATES_NUMBER:
|
||||
retval=getGates();
|
||||
retval=getGates();/** not implemented */
|
||||
break;
|
||||
case PROBES_NUMBER:
|
||||
retval=getProbes();
|
||||
@ -1875,9 +1848,6 @@ int get_time_left(int file_des) {
|
||||
case CYCLES_NUMBER:
|
||||
retval=getTrains();
|
||||
break;
|
||||
case PROGRESS:
|
||||
retval=getProgress();
|
||||
break;
|
||||
case ACTUAL_TIME:
|
||||
retval=getActualTime();
|
||||
break;
|
||||
|
||||
26
slsDetectorSoftware/jungfrauDetectorServerNewStructure/Makefile
Executable file
26
slsDetectorSoftware/jungfrauDetectorServerNewStructure/Makefile
Executable file
@ -0,0 +1,26 @@
|
||||
CROSS = bfin-uclinux-
|
||||
CC = $(CROSS)gcc
|
||||
CFLAGS += -Wall -DJUNGFRAUD -DSLS_DETECTOR_FUNCTION_LIST -DDACS_INT -DSTOP_SERVER #-DVERBOSEI #-DVERBOSE
|
||||
LDLIBS += -lm -lstdc++
|
||||
|
||||
PROGS = jungfrauDetectorServer
|
||||
DESTDIR ?= bin
|
||||
INSTMODE = 0777
|
||||
|
||||
SRC_CLNT = communication_funcs.c slsDetectorServer.c slsDetectorServer_funcs.c slsDetectorFunctionList.c
|
||||
OBJS = $(SRC_CLNT:.c=.o)
|
||||
|
||||
all: clean $(PROGS)
|
||||
|
||||
boot: $(OBJS)
|
||||
|
||||
$(PROGS): $(OBJS)
|
||||
echo $(OBJS)
|
||||
mkdir -p $(DESTDIR)
|
||||
$(CC) -o $@ $^ $(CFLAGS) $(LDLIBS)
|
||||
mv $(PROGS) $(DESTDIR)
|
||||
rm *.gdb
|
||||
|
||||
clean:
|
||||
rm -rf $(DESTDIR)/$(PROGS) *.o
|
||||
|
||||
@ -0,0 +1,25 @@
|
||||
CC = gcc
|
||||
CFLAGS += -Wall -DJUNGFRAUD -DSLS_DETECTOR_FUNCTION_LIST -DDACS_INT -DSTOP_SERVER #-DVERBOSEI #-DVERBOSE
|
||||
LDLIBS += -lm -lstdc++
|
||||
|
||||
PROGS = jungfrauDetectorServer
|
||||
DESTDIR ?= bin
|
||||
INSTMODE = 0777
|
||||
|
||||
SRC_CLNT = communication_funcs.c slsDetectorServer.c slsDetectorServer_funcs.c slsDetectorFunctionList.c
|
||||
OBJS = $(SRC_CLNT:.c=.o)
|
||||
|
||||
all: clean $(PROGS)
|
||||
|
||||
boot: $(OBJS)
|
||||
|
||||
$(PROGS): $(OBJS)
|
||||
echo $(OBJS)
|
||||
mkdir -p $(DESTDIR)
|
||||
$(CC) -o $@ $^ $(CFLAGS) $(LDLIBS)
|
||||
mv $(PROGS) $(DESTDIR)
|
||||
rm *.gdb
|
||||
|
||||
clean:
|
||||
rm -rf $(DESTDIR)/$(PROGS) *.o
|
||||
|
||||
@ -0,0 +1,335 @@
|
||||
#ifndef REGISTER_DEFS_H
|
||||
#define REGISTER_DEFS_H
|
||||
|
||||
/* Definitions for FPGA*/
|
||||
#define CSP0 0x20200000
|
||||
#define MEM_SIZE 0x100000
|
||||
|
||||
/* FPGA Version register */
|
||||
#define FPGA_VERSION_REG (0x00 << 11)
|
||||
|
||||
#define BOARD_REVISION_OFST (0)
|
||||
#define BOARD_REVISION_MSK (0x00FFFFFF << BOARD_REVISION_OFST)
|
||||
#define DETECTOR_TYPE_OFST (24)
|
||||
#define DETECTOR_TYPE_MSK (0x000000FF << DETECTOR_TYPE_OFST)
|
||||
|
||||
|
||||
|
||||
/* Fix pattern register */
|
||||
#define FIX_PATT_REG (0x01 << 11)
|
||||
|
||||
/* Status register */
|
||||
#define STATUS_REG (0x02 << 11)
|
||||
|
||||
#define RUN_BUSY_OFST (0)
|
||||
#define RUN_BUSY_MSK (0x00000001 << RUN_BUSY_OFST)
|
||||
#define WAITING_FOR_TRIGGER_OFST (3)
|
||||
#define WAITING_FOR_TRIGGER_MSK (0x00000001 << WAITING_FOR_TRIGGER_OFST)
|
||||
#define DELAYBEFORE_OFST (4) //Not used in software
|
||||
#define DELAYBEFORE_MSK (0x00000001 << DELAYBEFORE_OFST) //Not used in software
|
||||
#define DELAYAFTER_OFST (5) //Not used in software
|
||||
#define DELAYAFTER_MSK (0x00000001 << DELAYAFTER_OFST) //Not used in software
|
||||
#define STOPPED_OFST (15)
|
||||
#define STOPPED_MSK (0x00000001 << STOPPED_OFST)
|
||||
#define RUNMACHINE_BUSY_OFST (17)
|
||||
#define RUNMACHINE_BUSY_MSK (0x00000001 << RUNMACHINE_BUSY_OFST)
|
||||
|
||||
|
||||
/* Look at me register */
|
||||
#define LOOK_AT_ME_REG (0x03 << 11) //Not used in firmware or software
|
||||
|
||||
/* System Status register */
|
||||
#define SYSTEM_STATUS_REG (0x04 << 11) //Not used in software
|
||||
|
||||
#define DDR3_CAL_DONE_OFST (0) //Not used in software
|
||||
#define DDR3_CAL_DONE_MSK (0x00000001 << DDR3_CAL_DONE_OFST) //Not used in software
|
||||
#define DDR3_CAL_FAIL_OFST (1) //Not used in software
|
||||
#define DDR3_CAL_FAIL_MSK (0x00000001 << DDR3_CAL_FAIL_OFST) //Not used in software
|
||||
#define DDR3_INIT_DONE_OFST (2) //Not used in software
|
||||
#define DDR3_INIT_DONE_MSK (0x00000001 << DDR3_INIT_DONE_OFST) //Not used in software
|
||||
#define RECONFIG_PLL_LCK_OFST (3) //Not used in software
|
||||
#define RECONFIG_PLL_LCK_MSK (0x00000001 << RECONFIG_PLL_LCK_OFST) //Not used in software
|
||||
#define PLL_A_LCK_OFST (4) //Not used in software
|
||||
#define PLL_A_LCK_MSK (0x00000001 << PLL_A_LCK_OFST) //Not used in software
|
||||
#define DD3_PLL_LCK_OFST (5) //Not used in software
|
||||
#define DD3_PLL_LCK_MSK (0x00000001 << DD3_PLL_LCK_OFST) //Not used in software
|
||||
|
||||
|
||||
/* Module Control Board Serial Number Register */
|
||||
#define MOD_SERIAL_NUM_REG (0x0A << 11) //Not used in software
|
||||
|
||||
#define HARDWARE_SERIAL_NUM_OFST (0) //Not used in software
|
||||
#define HARDWARE_SERIAL_NUM_MSK (0x000000FF << HARDWARE_SERIAL_NUM_OFST) //Not used in software
|
||||
#define HARDWARE_VERSION_NUM_OFST (16) //Not used in software
|
||||
#define HARDWARE_VERSION_NUM_MSK (0x0000003F << HARDWARE_VERSION_NUM_OFST) //Not used in software
|
||||
|
||||
|
||||
/* Time from Start 64 bit register */
|
||||
#define TIME_FROM_START_LSB_REG (0x10 << 11)
|
||||
#define TIME_FROM_START_MSB_REG (0x11 << 11)
|
||||
|
||||
/* Get Delay 64 bit register */
|
||||
#define GET_DELAY_LSB_REG (0x12 << 11)
|
||||
#define GET_DELAY_MSB_REG (0x13 << 11)
|
||||
|
||||
/* Get Cycles 64 bit register */
|
||||
#define GET_CYCLES_LSB_REG (0x14 << 11)
|
||||
#define GET_CYCLES_MSB_REG (0x15 << 11)
|
||||
|
||||
/* Get Frames 64 bit register */
|
||||
#define GET_FRAMES_LSB_REG (0x16 << 11)
|
||||
#define GET_FRAMES_MSB_REG (0x17 << 11)
|
||||
|
||||
/* Get Period 64 bit register */
|
||||
#define GET_PERIOD_LSB_REG (0x18 << 11)
|
||||
#define GET_PERIOD_MSB_REG (0x19 << 11)
|
||||
|
||||
/* Get Frames from Start 64 bit register (frames from start Run Control) */
|
||||
#define FRAMES_FROM_START_PG_LSB_REG (0x24 << 11)
|
||||
#define FRAMES_FROM_START_PG_MSB_REG (0x25 << 11)
|
||||
|
||||
/* Measurement Time 64 bit register (timestamp at a frame start until reset)*/
|
||||
#define START_FRAME_TIME_LSB_REG (0x26 << 11)
|
||||
#define START_FRAME_TIME_MSB_REG (0x27 << 11)
|
||||
|
||||
/* SPI (Serial Peripheral Interface) Register */
|
||||
#define SPI_REG (0x40 << 11)
|
||||
|
||||
#define DAC_SERIAL_DIGITAL_OUT_OFST (0)
|
||||
#define DAC_SERIAL_DIGITAL_OUT_MSK (0x00000001 << DAC_SERIAL_DIGITAL_OUT_OFST)
|
||||
#define DAC_SERIAL_CLK_OUT_OFST (1)
|
||||
#define DAC_SERIAL_CLK_OUT_MSK (0x00000001 << DAC_SERIAL_CLK_OUT_OFST)
|
||||
#define DAC_SERIAL_CS_OUT_OFST (2)
|
||||
#define DAC_SERIAL_CS_OUT_MSK (0x00000001 << DAC_SERIAL_CS_OUT_OFST)
|
||||
#define HV_SERIAL_DIGITAL_OUT_OFST (8)
|
||||
#define HV_SERIAL_DIGITAL_OUT_MSK (0x00000001 << HV_SERIAL_DIGITAL_OUT_OFST)
|
||||
#define HV_SERIAL_CLK_OUT_OFST (9)
|
||||
#define HV_SERIAL_CLK_OUT_MSK (0x00000001 << HV_SERIAL_CLK_OUT_OFST)
|
||||
#define HV_SERIAL_CS_OUT_OFST (10)
|
||||
#define HV_SERIAL_CS_OUT_MSK (0x00000001 << HV_SERIAL_CS_OUT_OFST)
|
||||
|
||||
|
||||
/* ADC SPI (Serial Peripheral Interface) Register */
|
||||
#define ADC_SPI_REG (0x41 << 11)
|
||||
|
||||
#define ADC_SERIAL_CLK_OUT_OFST (0)
|
||||
#define ADC_SERIAL_CLK_OUT_MSK (0x00000001 << ADC_SERIAL_CLK_OUT_OFST)
|
||||
#define ADC_SERIAL_DATA_OUT_OFST (1)
|
||||
#define ADC_SERIAL_DATA_OUT_MSK (0x00000001 << ADC_SERIAL_DATA_OUT_OFST)
|
||||
#define ADC_SERIAL_CS_OUT_OFST (2)
|
||||
#define ADC_SERIAL_CS_OUT_MSK (0x0000000F << ADC_SERIAL_CS_OUT_OFST)
|
||||
|
||||
/* ADC offset Register */
|
||||
#define ADC_OFST_REG (0x42 << 11)
|
||||
|
||||
/* ADC Port Invert Register */
|
||||
#define ADC_PORT_INVERT_REG (0x43 << 11)
|
||||
|
||||
/* Receiver IP Address Register */
|
||||
#define RX_IP_REG (0x45 << 11)
|
||||
|
||||
/* UDP Port */
|
||||
#define UDP_PORT_REG (0x46 << 11)
|
||||
|
||||
#define UDP_PORT_RX_OFST (0)
|
||||
#define UDP_PORT_RX_MSK (0x0000FFFF << UDP_PORT_RX_OFST)
|
||||
#define UDP_PORT_TX_OFST (16)
|
||||
#define UDP_PORT_TX_MSK (0x0000FFFF << UDP_PORT_TX_OFST)
|
||||
|
||||
/* Receiver Mac Address 64 bit Register */
|
||||
#define RX_MAC_LSB_REG (0x47 << 11)
|
||||
#define RX_MAC_MSB_REG (0x48 << 11)
|
||||
|
||||
#define RX_MAC_LSB_OFST (0)
|
||||
#define RX_MAC_LSB_MSK (0x0000FFFF << RX_MAC_LSB_OFST)
|
||||
#define RX_MAC_MSB_OFST (0)
|
||||
#define RX_MAC_MSB_MSK (0x000000FF << RX_MAC_MSB_OFST)
|
||||
|
||||
/* Detector/ Transmitter Mac Address 64 bit Register */
|
||||
#define TX_MAC_LSB_REG (0x49 << 11)
|
||||
#define TX_MAC_MSB_REG (0x4A << 11)
|
||||
|
||||
#define TX_MAC_LSB_OFST (0)
|
||||
#define TX_MAC_LSB_MSK (0x0000FFFF << TX_MAC_LSB_OFST)
|
||||
#define TX_MAC_MSB_OFST (0)
|
||||
#define TX_MAC_MSB_MSK (0x000000FF << TX_MAC_MSB_OFST)
|
||||
|
||||
/* Detector/ Transmitter IP Address Register */
|
||||
#define TX_IP_REG (0x4B << 11)
|
||||
|
||||
/* Detector/ Transmitter IP Checksum Register */
|
||||
#define TX_IP_CHECKSUM_REG (0x4C << 11)
|
||||
|
||||
#define TX_IP_CHECKSUM_OFST (0)
|
||||
#define TX_IP_CHECKSUM_MSK (0x000000FF << TX_IP_CHECKSUM_OFST)
|
||||
|
||||
/* Configuration Register */
|
||||
#define CONFIG_REG (0x4D << 11)
|
||||
|
||||
#define CONFIG_OPERATION_MODE_OFST (16)
|
||||
#define CONFIG_OPERATION_MODE_MSK (0x00000001 << CONFIG_OPERATION_MODE_OFST)
|
||||
#define CONFIG_MODE_1_X_10GBE_VAL ((0x0 << CONFIG_OPERATION_MODE_OFST) & CONFIG_OPERATION_MODE_MSK)
|
||||
#define CONFIG_MODE_2_X_10GBE_VAL ((0x1 << CONFIG_OPERATION_MODE_OFST) & CONFIG_OPERATION_MODE_MSK)
|
||||
#define CONFIG_READOUT_SPEED_OFST (20)
|
||||
#define CONFIG_READOUT_SPEED_MSK (0x00000003 << CONFIG_READOUT_SPEED_OFST)
|
||||
#define CONFIG_QUARTER_SPEED_10MHZ_VAL ((0x0 << CONFIG_READOUT_SPEED_OFST) & CONFIG_READOUT_SPEED_MSK)
|
||||
#define CONFIG_HALF_SPEED_20MHZ_VAL ((0x1 << CONFIG_READOUT_SPEED_OFST) & CONFIG_READOUT_SPEED_MSK)
|
||||
#define CONFIG_FULL_SPEED_40MHZ_VAL ((0x2 << CONFIG_READOUT_SPEED_OFST) & CONFIG_READOUT_SPEED_MSK)
|
||||
#define CONFIG_TDMA_OFST (24)
|
||||
#define CONFIG_TDMA_MSK (0x00000001 << CONFIG_TDMA_OFST)
|
||||
#define CONFIG_TDMA_DISABLE_VAL ((0x0 << CONFIG_TDMA_OFST) & CONFIG_TDMA_MSK)
|
||||
#define CONFIG_TDMA_ENABLE_VAL ((0x1 << CONFIG_TDMA_OFST) & CONFIG_TDMA_MSK)
|
||||
#define CONFIG_TDMA_TIMESLOT_OFST (25)
|
||||
#define CONFIG_TDMA_TIMESLOT_MSK (0x0000001F << CONFIG_TDMA_TIMESLOT_OFST)
|
||||
#define CONFIG_TDMA_TIMESLOT_0_VAL ((0x0 << CONFIG_TDMA_TIMESLOT_OFST) & CONFIG_TDMA_TIMESLOT_MSK)
|
||||
|
||||
/* External Signal Register */
|
||||
#define EXT_SIGNAL_REG (0x4E << 11)
|
||||
|
||||
#define EXT_SIGNAL_OFST (0)
|
||||
#define EXT_SIGNAL_MSK (0x00000003 << EXT_SIGNAL_OFST) //enabled when both bits high
|
||||
|
||||
/* Control Register */
|
||||
#define CONTROL_REG (0x4F << 11)
|
||||
|
||||
#define CONTROL_START_ACQ_OFST (0)
|
||||
#define CONTROL_START_ACQ_MSK (0x00000001 << CONTROL_START_ACQ_OFST)
|
||||
#define CONTROL_STOP_ACQ_OFST (1)
|
||||
#define CONTROL_STOP_ACQ_MSK (0x00000001 << CONTROL_STOP_ACQ_OFST)
|
||||
#define CONTROL_CORE_RST_OFST (10)
|
||||
#define CONTROL_CORE_RST_MSK (0x00000001 << CONTROL_CORE_RST_OFST)
|
||||
#define CONTROL_PERIPHERAL_RST_OFST (11) //DDR3 HMem Ctrlr, GBE, Temp
|
||||
#define CONTROL_PERIPHERAL_RST_MSK (0x00000001 << CONTROL_PERIPHERAL_RST_OFST) //DDR3 HMem Ctrlr, GBE, Temp
|
||||
#define CONTROL_DDR3_MEM_RST_OFST (12) //only PHY, not DDR3 PLL ,Not used in software
|
||||
#define CONTROL_DDR3_MEM_RST_MSK (0x00000001 << CONTROL_DDR3_MEM_RST_OFST) //only PHY, not DDR3 PLL ,Not used in software
|
||||
#define CONTROL_ACQ_FIFO_CLR_OFST (14)
|
||||
#define CONTROL_ACQ_FIFO_CLR_MSK (0x00000001 << CONTROL_ACQ_FIFO_CLR_OFST)
|
||||
|
||||
/* Reconfiguratble PLL Paramater Register */
|
||||
#define PLL_PARAM_REG (0x50 << 11)
|
||||
|
||||
/* Reconfiguratble PLL Control Regiser */
|
||||
#define PLL_CONTROL_REG (0x51 << 11)
|
||||
|
||||
#define PLL_CTRL_RECONFIG_RST_OFST (0) //parameter reset
|
||||
#define PLL_CTRL_RECONFIG_RST_MSK (0x00000001 << PLL_CTRL_RECONFIG_RST_OFST) //parameter reset
|
||||
#define PLL_CTRL_WR_PARAMETER_OFST (2)
|
||||
#define PLL_CTRL_WR_PARAMETER_MSK (0x00000001 << PLL_CTRL_WR_PARAMETER_OFST)
|
||||
#define PLL_CTRL_RST_OFST (3)
|
||||
#define PLL_CTRL_RST_MSK (0x00000001 << PLL_CTRL_RST_OFST)
|
||||
#define PLL_CTRL_ADDR_OFST (16)
|
||||
#define PLL_CTRL_ADDR_MSK (0x0000003F << PLL_CTRL_ADDR_OFST)
|
||||
|
||||
/* Sample Register (Obsolete) */
|
||||
#define SAMPLE_REG (0x59 << 11)
|
||||
|
||||
#define SAMPLE_ADC_SAMPLE_SEL_OFST (0)
|
||||
#define SAMPLE_ADC_SAMPLE_SEL_MSK (0x00000007 << SAMPLE_ADC_SAMPLE_SEL_OFST)
|
||||
#define SAMPLE_ADC_SAMPLE_0_VAL ((0x0 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
|
||||
#define SAMPLE_ADC_SAMPLE_1_VAL ((0x1 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
|
||||
#define SAMPLE_ADC_SAMPLE_2_VAL ((0x2 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
|
||||
#define SAMPLE_ADC_SAMPLE_3_VAL ((0x3 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
|
||||
#define SAMPLE_ADC_SAMPLE_4_VAL ((0x4 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
|
||||
#define SAMPLE_ADC_SAMPLE_5_VAL ((0x5 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
|
||||
#define SAMPLE_ADC_SAMPLE_6_VAL ((0x6 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
|
||||
#define SAMPLE_ADC_SAMPLE_7_VAL ((0x7 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
|
||||
|
||||
#define SAMPLE_ADC_DECMT_FACTOR_OFST (4)
|
||||
#define SAMPLE_ADC_DECMT_FACTOR_MSK (0x00000007 << SAMPLE_ADC_DECMT_FACTOR_OFST)
|
||||
#define SAMPLE_ADC_DECMT_FACTOR_0_VAL ((0x0 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
|
||||
#define SAMPLE_ADC_DECMT_FACTOR_1_VAL ((0x1 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
|
||||
#define SAMPLE_ADC_DECMT_FACTOR_2_VAL ((0x2 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
|
||||
#define SAMPLE_ADC_DECMT_FACTOR_3_VAL ((0x3 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
|
||||
#define SAMPLE_ADC_DECMT_FACTOR_4_VAL ((0x4 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
|
||||
#define SAMPLE_ADC_DECMT_FACTOR_5_VAL ((0x5 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
|
||||
#define SAMPLE_ADC_DECMT_FACTOR_6_VAL ((0x6 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
|
||||
#define SAMPLE_ADC_DECMT_FACTOR_7_VAL ((0x7 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
|
||||
|
||||
#define SAMPLE_DGTL_SAMPLE_SEL_OFST (8)
|
||||
#define SAMPLE_DGTL_SAMPLE_SEL_MSK (0x0000000F << SAMPLE_DGTL_SAMPLE_SEL_OFST)
|
||||
#define SAMPLE_DGTL_SAMPLE_0_VAL ((0x0 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
|
||||
#define SAMPLE_DGTL_SAMPLE_1_VAL ((0x1 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
|
||||
#define SAMPLE_DGTL_SAMPLE_2_VAL ((0x2 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
|
||||
#define SAMPLE_DGTL_SAMPLE_3_VAL ((0x3 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
|
||||
#define SAMPLE_DGTL_SAMPLE_4_VAL ((0x4 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
|
||||
#define SAMPLE_DGTL_SAMPLE_5_VAL ((0x5 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
|
||||
#define SAMPLE_DGTL_SAMPLE_6_VAL ((0x6 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
|
||||
#define SAMPLE_DGTL_SAMPLE_7_VAL ((0x7 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
|
||||
#define SAMPLE_DGTL_SAMPLE_8_VAL ((0x8 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
|
||||
#define SAMPLE_DGTL_SAMPLE_9_VAL ((0x9 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
|
||||
#define SAMPLE_DGTL_SAMPLE_10_VAL ((0xa << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
|
||||
#define SAMPLE_DGTL_SAMPLE_11_VAL ((0xb << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
|
||||
#define SAMPLE_DGTL_SAMPLE_12_VAL ((0xc << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
|
||||
#define SAMPLE_DGTL_SAMPLE_13_VAL ((0xd << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
|
||||
#define SAMPLE_DGTL_SAMPLE_14_VAL ((0xe << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
|
||||
#define SAMPLE_DGTL_SAMPLE_15_VAL ((0xf << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
|
||||
|
||||
#define SAMPLE_DGTL_DECMT_FACTOR_OFST (12)
|
||||
#define SAMPLE_DGTL_DECMT_FACTOR_MSK (0x00000003 << SAMPLE_DGTL_DECMT_FACTOR_OFST)
|
||||
#define SAMPLE_DECMT_FACTOR_1_VAL ((0x0 << SAMPLE_DGTL_DECMT_FACTOR_OFST) & SAMPLE_DGTL_DECMT_FACTOR_MSK)
|
||||
#define SAMPLE_DECMT_FACTOR_2_VAL ((0x1 << SAMPLE_DGTL_DECMT_FACTOR_OFST) & SAMPLE_DGTL_DECMT_FACTOR_MSK)
|
||||
#define SAMPLE_DECMT_FACTOR_4_VAL ((0x2 << SAMPLE_DGTL_DECMT_FACTOR_OFST) & SAMPLE_DGTL_DECMT_FACTOR_MSK)
|
||||
|
||||
/** Vref Comp Mod Register */
|
||||
#define VREF_COMP_MOD_REG (0x5C << 11) //Not used in software, TBD in firmware
|
||||
|
||||
/** DAQ Register */
|
||||
#define DAQ_REG (0x5D << 11) //TBD in firmware
|
||||
|
||||
/** Chip Power Register */
|
||||
#define CHIP_POWER_REG (0x5E << 11)
|
||||
|
||||
#define CHIP_POWER_ENABLE_OFST (0)
|
||||
#define CHIP_POWER_ENABLE_MSK (0x00000001 << CHIP_POWER_ENABLE_OFST)
|
||||
|
||||
/* Set Delay 64 bit register */
|
||||
#define SET_DELAY_LSB_REG (0x60 << 11)
|
||||
#define SET_DELAY_MSB_REG (0x61 << 11)
|
||||
|
||||
/* Set Cycles 64 bit register */
|
||||
#define SET_CYCLES_LSB_REG (0x62 << 11)
|
||||
#define SET_CYCLES_MSB_REG (0x63 << 11)
|
||||
|
||||
/* Set Frames 64 bit register */
|
||||
#define SET_FRAMES_LSB_REG (0x64 << 11)
|
||||
#define SET_FRAMES_MSB_REG (0x65 << 11)
|
||||
|
||||
/* Set Period 64 bit register */
|
||||
#define SET_PERIOD_LSB_REG (0x66 << 11)
|
||||
#define SET_PERIOD_MSB_REG (0x67 << 11)
|
||||
|
||||
/* Set Period 64 bit register */
|
||||
#define SET_EXPTIME_LSB_REG (0x68 << 11)
|
||||
#define SET_EXPTIME_MSB_REG (0x69 << 11)
|
||||
|
||||
/* Module Coordinates Register 0 */
|
||||
#define COORD_0 (0x7C << 11)
|
||||
|
||||
#define COORD_0_Y_OFST (0)
|
||||
#define COORD_0_Y_MSK (0x0000FFFF << COORD_0_Y_OFST)
|
||||
#define COORD_0_X_OFST (16)
|
||||
#define COORD_0_X_MSK (0x0000FFFF << COORD_0_X_OFST)
|
||||
|
||||
/* Module Coordinates Register 1 */
|
||||
#define COORD_1 (0x7D << 11)
|
||||
|
||||
#define COORD_0_Z_OFST (0)
|
||||
#define COORD_0_Z_MSK (0x0000FFFF << COORD_0_Z_OFST)
|
||||
|
||||
|
||||
#endif //REGISTERS_G_H
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
1
slsDetectorSoftware/jungfrauDetectorServerNewStructure/ansi.h
Symbolic link
1
slsDetectorSoftware/jungfrauDetectorServerNewStructure/ansi.h
Symbolic link
@ -0,0 +1 @@
|
||||
../../slsReceiverSoftware/include/ansi.h
|
||||
@ -0,0 +1 @@
|
||||
../commonFiles/communication_funcs.c
|
||||
@ -0,0 +1 @@
|
||||
../commonFiles/communication_funcs.h
|
||||
@ -0,0 +1,9 @@
|
||||
Path: slsDetectorsPackage/slsDetectorSoftware/jungfrauDetectorServer
|
||||
URL: origin git@git.psi.ch:sls_detectors_software/sls_detector_software.git/jungfrauDetectorServer
|
||||
Repository Root: origin git@git.psi.ch:sls_detectors_software/sls_detector_software.git
|
||||
Repsitory UUID: 230d6b36e9852214f4ba5ae7c92647f35000b24d
|
||||
Revision: 56
|
||||
Branch: developer
|
||||
Last Changed Author: Dhanya_Maliakal
|
||||
Last Changed Rev: 1313
|
||||
Last Changed Date: 2016-11-30 10:36:34 +0100
|
||||
@ -0,0 +1,11 @@
|
||||
//#define SVNPATH ""
|
||||
#define SVNURL "git@git.psi.ch:sls_detectors_software/sls_detector_software.git/jungfrauDetectorServer"
|
||||
//#define SVNREPPATH ""
|
||||
#define SVNREPUUID "230d6b36e9852214f4ba5ae7c92647f35000b24d"
|
||||
//#define SVNREV 0x1313
|
||||
//#define SVNKIND ""
|
||||
//#define SVNSCHED ""
|
||||
#define SVNAUTH "Dhanya_Maliakal"
|
||||
#define SVNREV 0x1313
|
||||
#define SVNDATE 0x20161130
|
||||
//
|
||||
@ -0,0 +1,11 @@
|
||||
//#define SVNPATH ""
|
||||
#define SVNURL ""
|
||||
//#define SVNREPPATH ""
|
||||
#define SVNREPUUID ""
|
||||
//#define SVNREV ""
|
||||
//#define SVNKIND ""
|
||||
//#define SVNSCHED ""
|
||||
#define SVNAUTH ""
|
||||
#define SVNREV ""
|
||||
#define SVNDATE ""
|
||||
//
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1 @@
|
||||
../slsDetectorServer/slsDetectorFunctionList.h
|
||||
@ -0,0 +1 @@
|
||||
../slsDetectorServer/slsDetectorServer.c
|
||||
@ -0,0 +1,215 @@
|
||||
#ifndef SLSDETECTORSERVER_DEFS_H
|
||||
#define SLSDETECTORSERVER_DEFS_H
|
||||
|
||||
#include "sls_detector_defs.h" //default dynamicgain in settings
|
||||
#include "registers_m.h"
|
||||
#include <stdint.h>
|
||||
|
||||
|
||||
|
||||
#define GOODBYE (-200)
|
||||
//#define REQUIRED_FIRMWARE_VERSION 16
|
||||
//#define FIRMWAREREV 0xcaba //temporary should be in firmware
|
||||
enum clkspeed {FULL_SPEED, HALF_SPEED, QUARTER_SPEED};
|
||||
enum ADC_INDEX {TEMP_FPGA, TEMP_ADC};
|
||||
enum DAC_INDEX { VB_COMP, VDD_PROT, VIN_COM, VREF_PRECH, VB_PIXBUF, VB_DS, VREF_DS, VREF_COMP };
|
||||
#define DEFAULT_DAC_VALS { 1220, /* VB_COMP */ \
|
||||
3000, /* VDD_PROT */ \
|
||||
1053, /* VIN_COM */ \
|
||||
1450, /* VREF_PRECH */ \
|
||||
750, /* VB_PIXBUF */ \
|
||||
1000, /* VB_DS */ \
|
||||
480, /* VREF_DS */ \
|
||||
420 /* VREF_COMP */ \
|
||||
};
|
||||
|
||||
|
||||
/* Hardware Definitions */
|
||||
#define NMAXMODY (1)
|
||||
#define NMAXMODX (1)
|
||||
#define NMAXMOD (NMAXMODX * NMAXMODY)
|
||||
//#define NMODY (1)
|
||||
//#define NMODX (1)
|
||||
//#define NMOD (NMODX * NMODY)
|
||||
#define NCHAN (256 * 256)
|
||||
#define NCHIP (8)
|
||||
#define NADC (0)
|
||||
#define NDAC (8)
|
||||
#define NCHANS (NCHAN * NCHIP * NMAXMOD)
|
||||
#define NDACS (NDAC * NMAXMOD)
|
||||
#define DYNAMIC_RANGE (16)
|
||||
#define DATA_BYTES (NMAXMOD * NCHIP * NCHAN * 2)
|
||||
#define IP_PACKETSIZE (0x2052)
|
||||
#define CLK_RUN (40) /* MHz */
|
||||
#define CLK_SYNC (20) /* MHz */
|
||||
|
||||
|
||||
/** Default Parameters */
|
||||
#define DEFAULT_NUM_FRAMES (100*1000*1000)
|
||||
#define DEFAULT_NUM_CYCLES (1)
|
||||
#define DEFAULT_EXPTIME (10*1000) //ns
|
||||
#define DEFAULT_PERIOD (2*1000*1000) //ns
|
||||
#define DEFAULT_DELAY (0)
|
||||
#define DEFAULT_HIGH_VOLTAGE (0)
|
||||
#define DEFAULT_SETTINGS (DYNAMICGAIN)
|
||||
#define DEFAULT_TX_UDP_PORT (0x7e9a)
|
||||
|
||||
/* Defines in the Firmware */
|
||||
#define FIX_PATT_VAL (0xACDC2014)
|
||||
#define ADC_PORT_INVERT_VAL (0x453b2a9c)
|
||||
|
||||
|
||||
#define SAMPLE_ADC_HALF_SPEED (SAMPLE_DECMT_FACTOR_2_VAL + SAMPLE_DGTL_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_0_VAL + SAMPLE_ADC_SAMPLE_0_VAL) /* 0x1000 */
|
||||
#define SAMPLE_ADC_QUARTER_SPEED (SAMPLE_DECMT_FACTOR_4_VAL + SAMPLE_DGTL_SAMPLE_8_VAL + SAMPLE_ADC_DECMT_FACTOR_1_VAL + SAMPLE_ADC_SAMPLE_0_VAL) /* 0x2810 */
|
||||
#define CONFIG_HALF_SPEED (CONFIG_TDMA_TIMESLOT_0_VAL + CONFIG_TDMA_DISABLE_VAL + CONFIG_HALF_SPEED_20MHZ_VAL + CONFIG_MODE_1_X_10GBE_VAL)
|
||||
#define CONFIG_QUARTER_SPEED (CONFIG_TDMA_TIMESLOT_0_VAL + CONFIG_TDMA_DISABLE_VAL + CONFIG_QUARTER_SPEED_10MHZ_VAL + CONFIG_MODE_1_X_10GBE_VAL)
|
||||
#define ADC_OFST_HALF_SPEED_VAL (0x20) //adc pipeline
|
||||
#define ADC_OFST_QUARTER_SPEED_VAL (0x0f)
|
||||
#define ADC_PHASE_HALF_SPEED (0x41)
|
||||
#define ADC_PHASE_QUARTER_SPEED (0x19)
|
||||
|
||||
/* Maybe not required for jungfrau */
|
||||
#define NTRIMBITS (6)
|
||||
#define NCOUNTBITS (24)
|
||||
#define NCHIPS_PER_ADC (2)
|
||||
#define TRIM_DR (((int)pow(2,NTRIMBITS))-1)
|
||||
#define COUNT_DR (((int)pow(2,NCOUNTBITS))-1)
|
||||
#define ALLMOD (0xffff)
|
||||
#define ALLFIFO (0xffff)
|
||||
|
||||
/* LTC2620 DAC DEFINES */
|
||||
#define LTC2620_DAC_CMD_OFST (20)
|
||||
#define LTC2620_DAC_CMD_MSK (0x0000000F << LTC2620_DAC_CMD_OFST)
|
||||
#define LTC2620_DAC_ADDR_OFST (16)
|
||||
#define LTC2620_DAC_ADDR_MSK (0x0000000F << LTC2620_DAC_ADDR_OFST)
|
||||
#define LTC2620_DAC_DATA_OFST (4)
|
||||
#define LTC2620_DAC_DATA_MSK (0x00000FFF << LTC2620_DAC_DATA_OFST)
|
||||
|
||||
#define LTC2620_DAC_CMD_WRITE (0x00000000 << LTC2620_DAC_CMD_OFST)
|
||||
#define LTC2620_DAC_CMD_SET (0x00000003 << LTC2620_DAC_CMD_OFST)
|
||||
#define LTC2620_DAC_CMD_POWER_DOWN (0x00000004 << LTC2620_DAC_CMD_OFST)
|
||||
#define LTC2620_DAC_NUMBITS (24)
|
||||
|
||||
|
||||
/* MAX1932 HV DEFINES */
|
||||
#define MAX1932_HV_NUMBITS (8)
|
||||
#define MAX1932_HV_DATA_OFST (0)
|
||||
#define MAX1932_HV_DATA_MSK (0x000000FF << MAX1932_HV_DATA_OFST)
|
||||
|
||||
/* AD9257 ADC DEFINES */
|
||||
#define AD9257_ADC_NUMBITS (24)
|
||||
|
||||
#define AD9257_DEV_IND_2_REG (0x04)
|
||||
#define AD9257_CHAN_H_OFST (0)
|
||||
#define AD9257_CHAN_H_MSK (0x00000001 << AD9257_CHAN_H_OFST)
|
||||
#define AD9257_CHAN_G_OFST (1)
|
||||
#define AD9257_CHAN_G_MSK (0x00000001 << AD9257_CHAN_G_OFST)
|
||||
#define AD9257_CHAN_F_OFST (2)
|
||||
#define AD9257_CHAN_F_MSK (0x00000001 << AD9257_CHAN_F_OFST)
|
||||
#define AD9257_CHAN_E_OFST (3)
|
||||
#define AD9257_CHAN_E_MSK (0x00000001 << AD9257_CHAN_E_OFST)
|
||||
|
||||
#define AD9257_DEV_IND_1_REG (0x05)
|
||||
#define AD9257_CHAN_D_OFST (0)
|
||||
#define AD9257_CHAN_D_MSK (0x00000001 << AD9257_CHAN_D_OFST)
|
||||
#define AD9257_CHAN_C_OFST (1)
|
||||
#define AD9257_CHAN_C_MSK (0x00000001 << AD9257_CHAN_C_OFST)
|
||||
#define AD9257_CHAN_B_OFST (2)
|
||||
#define AD9257_CHAN_B_MSK (0x00000001 << AD9257_CHAN_B_OFST)
|
||||
#define AD9257_CHAN_A_OFST (3)
|
||||
#define AD9257_CHAN_A_MSK (0x00000001 << AD9257_CHAN_A_OFST)
|
||||
#define AD9257_CLK_CH_DCO_OFST (4)
|
||||
#define AD9257_CLK_CH_DCO_MSK (0x00000001 << AD9257_CLK_CH_DCO_OFST)
|
||||
#define AD9257_CLK_CH_IFCO_OFST (5)
|
||||
#define AD9257_CLK_CH_IFCO_MSK (0x00000001 << AD9257_CLK_CH_IFCO_OFST)
|
||||
|
||||
#define AD9257_POWER_MODE_REG (0x08)
|
||||
#define AD9257_POWER_INTERNAL_OFST (0)
|
||||
#define AD9257_POWER_INTERNAL_MSK (0x00000003 << AD9257_POWER_INTERNAL_OFST)
|
||||
#define AD9257_INT_RESET_VAL (0x3)
|
||||
#define AD9257_INT_CHIP_RUN_VAL (0x0)
|
||||
#define AD9257_POWER_EXTERNAL_OFST (5)
|
||||
#define AD9257_POWER_EXTERNAL_MSK (0x00000001 << AD9257_POWER_EXTERNAL_OFST)
|
||||
#define AD9257_EXT_FULL_POWER_VAL (0x0)
|
||||
#define AD9257_EXT_STANDBY_VAL (0x1)
|
||||
|
||||
#define AD9257_OUT_MODE_REG (0x14)
|
||||
#define AD9257_OUT_FORMAT_OFST (0)
|
||||
#define AD9257_OUT_FORMAT_MSK (0x00000001 << AD9257_OUT_FORMAT_OFST)
|
||||
#define AD9257_OUT_BINARY_OFST_VAL (0)
|
||||
#define AD9257_OUT_TWOS_COMPL_VAL (1)
|
||||
#define AD9257_OUT_LVDS_OPT_OFST (6)
|
||||
#define AD9257_OUT_LVDS_OPT_MSK (0x00000001 << AD9257_OUT_LVDS_OPT_OFST)
|
||||
#define AD9257_OUT_LVDS_ANSI_VAL (0)
|
||||
#define AD9257_OUT_LVDS_IEEE_VAL (1)
|
||||
|
||||
#define AD9257_OUT_PHASE_REG (0x16)
|
||||
#define AD9257_OUT_CLK_OFST (0)
|
||||
#define AD9257_OUT_CLK_MSK (0x0000000F << AD9257_OUT_CLK_OFST)
|
||||
#define AD9257_OUT_CLK_60_VAL (0x1)
|
||||
#define AD9257_IN_CLK_OFST (4)
|
||||
#define AD9257_IN_CLK_MSK (0x00000007 << AD9257_IN_CLK_OFST)
|
||||
#define AD9257_IN_CLK_0_VAL (0x0)
|
||||
|
||||
#define AD9257_VREF_REG (0x18)
|
||||
#define AD9257_VREF_OFST (0)
|
||||
#define AD9257_VREF_MSK (0x00000003 << AD9257_VREF_OFST)
|
||||
#define AD9257_VREF_1_33_VAL (0x2)
|
||||
|
||||
#define AD9257_TEST_MODE_REG (0x0D)
|
||||
#define AD9257_OUT_TEST_OFST (0)
|
||||
#define AD9257_OUT_TEST_MSK (0x0000000F << AD9257_OUT_TEST_OFST)
|
||||
#define AD9257_NONE_VAL (0x0)
|
||||
#define AD9257_MIXED_BIT_FREQ_VAL (0xC)
|
||||
#define AD9257_TEST_RESET_SHORT_GEN (4)
|
||||
#define AD9257_TEST_RESET_LONG_GEN (5)
|
||||
#define AD9257_USER_IN_MODE_OFST (6)
|
||||
#define AD9257_USER_IN_MODE_MSK (0x00000003 << AD9257_USER_IN_MODE_OFST)
|
||||
|
||||
/** PLL Reconfiguration Registers */
|
||||
//https://www.altera.com/documentation/mcn1424769382940.html
|
||||
#define PLL_MODE_REG (0x00)
|
||||
#define PLL_STATUS_REG (0x01)
|
||||
#define PLL_START_REG (0x02)
|
||||
#define PLL_N_COUNTER_REG (0x03)
|
||||
#define PLL_M_COUNTER_REG (0x04)
|
||||
#define PLL_C_COUNTER_REG (0x05)
|
||||
#define PLL_PHASE_SHIFT_REG (0x06)
|
||||
|
||||
#define PLL_SHIFT_NUM_SHIFTS_OFST (0)
|
||||
#define PLL_SHIFT_NUM_SHIFTS_MSK (0x0000FFFF << PLL_SHIFT_NUM_SHIFTS_OFST)
|
||||
|
||||
#define PLL_SHIFT_CNT_SELECT_OFST (16)
|
||||
#define PLL_SHIFT_CNT_SELECT_MSK (0x0000001F << PLL_SHIFT_CNT_SELECT_OFST)
|
||||
#define PLL_SHIFT_CNT_SLCT_C0_VAL (0x0 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
|
||||
#define PLL_SHIFT_CNT_SLCT_C1_VAL (0x1 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
|
||||
#define PLL_SHIFT_CNT_SLCT_C2_VAL (0x2 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
|
||||
#define PLL_SHIFT_CNT_SLCT_C3_VAL (0x3 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
|
||||
#define PLL_SHIFT_CNT_SLCT_C4_VAL (0x4 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
|
||||
#define PLL_SHIFT_CNT_SLCT_C5_VAL (0x5 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
|
||||
#define PLL_SHIFT_CNT_SLCT_C6_VAL (0x6 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
|
||||
#define PLL_SHIFT_CNT_SLCT_C7_VAL (0x7 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
|
||||
#define PLL_SHIFT_CNT_SLCT_C8_VAL (0x8 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
|
||||
#define PLL_SHIFT_CNT_SLCT_C9_VAL (0x9 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
|
||||
#define PLL_SHIFT_CNT_SLCT_C10_VAL (0x10 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
|
||||
#define PLL_SHIFT_CNT_SLCT_C11_VAL (0x11 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
|
||||
#define PLL_SHIFT_CNT_SLCT_C12_VAL (0x12 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
|
||||
#define PLL_SHIFT_CNT_SLCT_C13_VAL (0x13 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
|
||||
#define PLL_SHIFT_CNT_SLCT_C14_VAL (0x14 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
|
||||
#define PLL_SHIFT_CNT_SLCT_C15_VAL (0x15 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
|
||||
#define PLL_SHIFT_CNT_SLCT_C16_VAL (0x16 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
|
||||
#define PLL_SHIFT_CNT_SLCT_C17_VAL (0x17 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
|
||||
|
||||
#define PLL_SHIFT_UP_DOWN_OFST (21)
|
||||
#define PLL_SHIFT_UP_DOWN_MSK (0x00000001 << PLL_SHIFT_UP_DOWN_OFST)
|
||||
#define PLL_SHIFT_UP_DOWN_NEG_VAL ((0x0 << PLL_SHIFT_UP_DOWN_OFST) & PLL_SHIFT_UP_DOWN_MSK)
|
||||
#define PLL_SHIFT_UP_DOWN_POS_VAL ((0x1 << PLL_SHIFT_UP_DOWN_OFST) & PLL_SHIFT_UP_DOWN_MSK)
|
||||
|
||||
#define PLL_K_COUNTER_REG (0x07)
|
||||
#define PLL_BANDWIDTH_REG (0x08)
|
||||
#define PLL_CHARGEPUMP_REG (0x09)
|
||||
#define PLL_VCO_DIV_REG (0x1c)
|
||||
#define PLL_MIF_REG (0x1f)
|
||||
|
||||
|
||||
#endif /* SLSDETECTORSERVER_DEFS_H */
|
||||
@ -0,0 +1 @@
|
||||
../slsDetectorServer/slsDetectorServer_funcs.c
|
||||
@ -0,0 +1 @@
|
||||
../slsDetectorServer/slsDetectorServer_funcs.h
|
||||
@ -0,0 +1 @@
|
||||
../commonFiles/sls_detector_defs.h
|
||||
@ -0,0 +1 @@
|
||||
../commonFiles/sls_detector_funcs.h
|
||||
@ -0,0 +1 @@
|
||||
../../slsReceiverSoftware/include/sls_receiver_defs.h
|
||||
@ -0,0 +1 @@
|
||||
../../slsReceiverSoftware/include/sls_receiver_funcs.h
|
||||
@ -18,22 +18,46 @@ Here are the definitions, but the actual implementation should be done for each
|
||||
****************************************************/
|
||||
|
||||
|
||||
//basic tests
|
||||
void checkFirmwareCompatibility();
|
||||
#ifdef JUNGFRAUD
|
||||
int checkType();
|
||||
u_int32_t testFpga(void);
|
||||
int testBus(void);
|
||||
#endif
|
||||
int moduleTest( enum digitalTestMode arg, int imod);
|
||||
int detectorTest( enum digitalTestMode arg);
|
||||
|
||||
void getModuleConfiguration();
|
||||
int initDetector();
|
||||
int initDetectorStop();
|
||||
|
||||
int setNMod(int nm, enum dimension dim);
|
||||
int getNModBoard(enum dimension arg);
|
||||
|
||||
int64_t getModuleId(enum idMode arg, int imod);
|
||||
//Ids
|
||||
int64_t getDetectorId(enum idMode arg);
|
||||
u_int64_t getFirmwareVersion();
|
||||
int64_t getModuleId(enum idMode arg, int imod);
|
||||
int getDetectorNumber();
|
||||
u_int64_t getDetectorMAC();
|
||||
int getDetectorIP();
|
||||
|
||||
int moduleTest( enum digitalTestMode arg, int imod);
|
||||
int detectorTest( enum digitalTestMode arg);
|
||||
|
||||
//initialization
|
||||
int initDetector();
|
||||
#ifdef EIGERD
|
||||
int initDetectorStop();
|
||||
void getModuleConfiguration();
|
||||
#endif
|
||||
|
||||
#ifdef JUNGFRAUD
|
||||
int mapCSP0(void);
|
||||
u_int16_t bus_w16(u_int32_t offset, u_int16_t data);
|
||||
u_int16_t bus_r16(u_int32_t offset);
|
||||
u_int32_t bus_w(u_int32_t offset, u_int32_t data);
|
||||
u_int32_t bus_r(u_int32_t offset);
|
||||
#endif
|
||||
|
||||
|
||||
int setNMod(int nm, enum dimension dim);
|
||||
int getNModBoard(enum dimension arg);
|
||||
|
||||
|
||||
|
||||
|
||||
void setDAC(enum detDacIndex ind, int val, int imod, int mV, int retval[]);
|
||||
|
||||
@ -28,7 +28,7 @@ int main(int argc, char *argv[]){
|
||||
#endif
|
||||
if (argc==1) {
|
||||
|
||||
checkFirmwareCompatibility();
|
||||
basictests();
|
||||
//#endif
|
||||
portno = DEFAULT_PORTNO;
|
||||
printf("opening control server on port %d\n",portno );
|
||||
|
||||
@ -7,19 +7,17 @@
|
||||
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
|
||||
#include <arpa/inet.h>
|
||||
int sockfd;
|
||||
|
||||
|
||||
// Global variables
|
||||
|
||||
extern int lockStatus;
|
||||
extern char lastClientIP[INET_ADDRSTRLEN];
|
||||
extern char thisClientIP[INET_ADDRSTRLEN];
|
||||
extern int differentClients;
|
||||
|
||||
|
||||
|
||||
// Global variables
|
||||
int (*flist[256])(int);
|
||||
//defined in the detector specific file
|
||||
//defined in the detector specific Makefile
|
||||
#ifdef MYTHEND
|
||||
const enum detectorType myDetectorType=MYTHEN;
|
||||
#elif GOTTHARDD
|
||||
@ -28,58 +26,25 @@ const enum detectorType myDetectorType=GOTTHARD;
|
||||
const enum detectorType myDetectorType=EIGER;
|
||||
#elif PICASSOD
|
||||
const enum detectorType myDetectorType=PICASSO;
|
||||
#elif MOENCHD
|
||||
const enum detectorType myDetectorType=MOENCH;
|
||||
#elif JUNGFRAUD
|
||||
const enum detectorType myDetectorType=JUNGFRAU;
|
||||
#else
|
||||
const enum detectorType myDetectorType=GENERIC;
|
||||
#endif
|
||||
|
||||
extern enum detectorSettings thisSettings;
|
||||
|
||||
//global variables for optimized readout
|
||||
int sockfd; //updated in slsDetectorServer (extern)
|
||||
int (*flist[256])(int);
|
||||
char mess[MAX_STR_LENGTH];
|
||||
int dataret;
|
||||
//extern
|
||||
int dataBytes = 10;
|
||||
|
||||
|
||||
|
||||
void checkFirmwareCompatibility(){
|
||||
int64_t fwversion = getDetectorId(DETECTOR_FIRMWARE_VERSION);
|
||||
int64_t swversion = getDetectorId(DETECTOR_SOFTWARE_VERSION);
|
||||
int64_t sw_fw_apiversion = getDetectorId(SOFTWARE_FIRMWARE_API_VERSION);
|
||||
|
||||
cprintf(BLUE,"\n\n********************************************************\n"
|
||||
"**********************EIGER Server**********************\n"
|
||||
"********************************************************\n");
|
||||
cprintf(BLUE,"\n"
|
||||
"Firmware Version:\t\t %lld\n"
|
||||
"Software Version:\t\t %llx\n"
|
||||
"F/w-S/w API Version:\t\t %lld\n"
|
||||
"Required Firmware Version:\t %d\n"
|
||||
"\n********************************************************\n",
|
||||
fwversion,swversion,sw_fw_apiversion,REQUIRED_FIRMWARE_VERSION);
|
||||
|
||||
//cant read versions
|
||||
if(!fwversion || !sw_fw_apiversion){
|
||||
cprintf(RED,"FATAL ERROR: Cant read versions from FPGA. Please update firmware\n");
|
||||
cprintf(RED,"Exiting Server. Goodbye!\n\n");
|
||||
exit(-1);
|
||||
}
|
||||
|
||||
//check for API compatibility - old server
|
||||
if(sw_fw_apiversion > REQUIRED_FIRMWARE_VERSION){
|
||||
cprintf(RED,"FATAL ERROR: This software version is incompatible.\n"
|
||||
"Please update it to be compatible with this firmware\n\n");
|
||||
cprintf(RED,"Exiting Server. Goodbye!\n\n");
|
||||
exit(-1);
|
||||
}
|
||||
|
||||
//check for firmware compatibility - old firmware
|
||||
if( REQUIRED_FIRMWARE_VERSION > fwversion){
|
||||
cprintf(RED,"FATAL ERROR: This firmware version is incompatible.\n"
|
||||
"Please update it to v%d to be compatible with this server\n\n", REQUIRED_FIRMWARE_VERSION);
|
||||
cprintf(RED,"Exiting Server. Goodbye!\n\n");
|
||||
exit(-1);
|
||||
}
|
||||
void basictests() {
|
||||
#ifdef SLS_DETECTOR_FUNCTION_LIST
|
||||
checkFirmwareCompatibility();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
@ -431,8 +396,10 @@ int send_update(int file_des) {
|
||||
nm=setDynamicRange(GET_FLAG);
|
||||
#endif
|
||||
n += sendData(file_des,&nm,sizeof(nm),INT32);
|
||||
nm = dataBytes;
|
||||
n += sendData(file_des,&nm,sizeof(nm),INT32);
|
||||
#ifdef SLS_DETECTOR_FUNCTION_LIST
|
||||
dataBytes=calculateDataBytes();
|
||||
#endif
|
||||
n += sendData(file_des,&dataBytes,sizeof(dataBytes),INT32);
|
||||
#ifdef SLS_DETECTOR_FUNCTION_LIST
|
||||
t=setSettings(GET_SETTINGS, GET_FLAG);
|
||||
#endif
|
||||
@ -1016,10 +983,6 @@ int digital_test(int file_des) {
|
||||
#ifdef VERBOSE
|
||||
printf("of module %d\n", imod);
|
||||
#endif
|
||||
#ifndef MYTHEND
|
||||
ret = FAIL;
|
||||
strcpy(mess,"Not applicable/implemented for this detector\n");
|
||||
#else
|
||||
#ifdef SLS_DETECTOR_FUNCTION_LIST
|
||||
if (imod>=0 && imod<getTotalNumberOfModules())
|
||||
retval=moduleTest(arg,imod);
|
||||
@ -1058,7 +1021,7 @@ int digital_test(int file_des) {
|
||||
#endif
|
||||
break;
|
||||
default:
|
||||
printf("Unknown digital test required %d\n",arg);
|
||||
printf("Digital test: %d. Not applicable/implemented for this detector\n",arg);
|
||||
ret=FAIL;
|
||||
retval=FAIL;
|
||||
break;
|
||||
@ -2488,13 +2451,13 @@ int get_run_status(int file_des) {
|
||||
|
||||
|
||||
int start_and_read_all(int file_des) {
|
||||
int dataret1;
|
||||
int dataret1, dataret;
|
||||
#ifdef VERBOSE
|
||||
printf("Starting and reading all frames\n");
|
||||
#endif
|
||||
|
||||
if (differentClients==1 && lockStatus==1) {
|
||||
dataret=FAIL;
|
||||
dataret = FAIL;
|
||||
sprintf(mess,"Detector locked by %s\n",lastClientIP);
|
||||
//ret could be swapped during sendData
|
||||
dataret1 = dataret;
|
||||
@ -2521,7 +2484,7 @@ int start_and_read_all(int file_des) {
|
||||
|
||||
|
||||
int read_frame(int file_des) {
|
||||
int dataret1;
|
||||
int dataret1, dataret;
|
||||
|
||||
if (differentClients==1 && lockStatus==1) {
|
||||
dataret=FAIL;
|
||||
|
||||
@ -11,7 +11,7 @@
|
||||
|
||||
|
||||
//basic server functions
|
||||
void checkFirmwareCompatibility();
|
||||
void basictests();
|
||||
int init_detector(int);
|
||||
int decode_function(int);
|
||||
int function_table();
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user