mirror of
https://github.com/slsdetectorgroup/slsDetectorPackage.git
synced 2025-06-21 09:08:00 +02:00
mannnnyyyy changes to jungfrau serverin structure, also to eiger structure a bit
This commit is contained in:
Dhanya Maliakal
26
slsDetectorSoftware/jungfrauDetectorServerNewStructure/Makefile
Executable file
26
slsDetectorSoftware/jungfrauDetectorServerNewStructure/Makefile
Executable file
@ -0,0 +1,26 @@
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CROSS = bfin-uclinux-
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CC = $(CROSS)gcc
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CFLAGS += -Wall -DJUNGFRAUD -DSLS_DETECTOR_FUNCTION_LIST -DDACS_INT -DSTOP_SERVER #-DVERBOSEI #-DVERBOSE
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LDLIBS += -lm -lstdc++
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PROGS = jungfrauDetectorServer
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DESTDIR ?= bin
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INSTMODE = 0777
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SRC_CLNT = communication_funcs.c slsDetectorServer.c slsDetectorServer_funcs.c slsDetectorFunctionList.c
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OBJS = $(SRC_CLNT:.c=.o)
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all: clean $(PROGS)
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boot: $(OBJS)
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$(PROGS): $(OBJS)
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echo $(OBJS)
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mkdir -p $(DESTDIR)
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$(CC) -o $@ $^ $(CFLAGS) $(LDLIBS)
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mv $(PROGS) $(DESTDIR)
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rm *.gdb
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clean:
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rm -rf $(DESTDIR)/$(PROGS) *.o
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@ -0,0 +1,25 @@
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CC = gcc
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CFLAGS += -Wall -DJUNGFRAUD -DSLS_DETECTOR_FUNCTION_LIST -DDACS_INT -DSTOP_SERVER #-DVERBOSEI #-DVERBOSE
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LDLIBS += -lm -lstdc++
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PROGS = jungfrauDetectorServer
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DESTDIR ?= bin
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INSTMODE = 0777
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SRC_CLNT = communication_funcs.c slsDetectorServer.c slsDetectorServer_funcs.c slsDetectorFunctionList.c
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OBJS = $(SRC_CLNT:.c=.o)
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all: clean $(PROGS)
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boot: $(OBJS)
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$(PROGS): $(OBJS)
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echo $(OBJS)
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mkdir -p $(DESTDIR)
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$(CC) -o $@ $^ $(CFLAGS) $(LDLIBS)
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mv $(PROGS) $(DESTDIR)
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rm *.gdb
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clean:
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rm -rf $(DESTDIR)/$(PROGS) *.o
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@ -0,0 +1,335 @@
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#ifndef REGISTER_DEFS_H
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#define REGISTER_DEFS_H
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/* Definitions for FPGA*/
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#define CSP0 0x20200000
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#define MEM_SIZE 0x100000
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/* FPGA Version register */
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#define FPGA_VERSION_REG (0x00 << 11)
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#define BOARD_REVISION_OFST (0)
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#define BOARD_REVISION_MSK (0x00FFFFFF << BOARD_REVISION_OFST)
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#define DETECTOR_TYPE_OFST (24)
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#define DETECTOR_TYPE_MSK (0x000000FF << DETECTOR_TYPE_OFST)
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/* Fix pattern register */
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#define FIX_PATT_REG (0x01 << 11)
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/* Status register */
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#define STATUS_REG (0x02 << 11)
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#define RUN_BUSY_OFST (0)
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#define RUN_BUSY_MSK (0x00000001 << RUN_BUSY_OFST)
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#define WAITING_FOR_TRIGGER_OFST (3)
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#define WAITING_FOR_TRIGGER_MSK (0x00000001 << WAITING_FOR_TRIGGER_OFST)
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#define DELAYBEFORE_OFST (4) //Not used in software
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#define DELAYBEFORE_MSK (0x00000001 << DELAYBEFORE_OFST) //Not used in software
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#define DELAYAFTER_OFST (5) //Not used in software
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#define DELAYAFTER_MSK (0x00000001 << DELAYAFTER_OFST) //Not used in software
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#define STOPPED_OFST (15)
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#define STOPPED_MSK (0x00000001 << STOPPED_OFST)
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#define RUNMACHINE_BUSY_OFST (17)
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#define RUNMACHINE_BUSY_MSK (0x00000001 << RUNMACHINE_BUSY_OFST)
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/* Look at me register */
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#define LOOK_AT_ME_REG (0x03 << 11) //Not used in firmware or software
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/* System Status register */
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#define SYSTEM_STATUS_REG (0x04 << 11) //Not used in software
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#define DDR3_CAL_DONE_OFST (0) //Not used in software
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#define DDR3_CAL_DONE_MSK (0x00000001 << DDR3_CAL_DONE_OFST) //Not used in software
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#define DDR3_CAL_FAIL_OFST (1) //Not used in software
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#define DDR3_CAL_FAIL_MSK (0x00000001 << DDR3_CAL_FAIL_OFST) //Not used in software
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#define DDR3_INIT_DONE_OFST (2) //Not used in software
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#define DDR3_INIT_DONE_MSK (0x00000001 << DDR3_INIT_DONE_OFST) //Not used in software
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#define RECONFIG_PLL_LCK_OFST (3) //Not used in software
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#define RECONFIG_PLL_LCK_MSK (0x00000001 << RECONFIG_PLL_LCK_OFST) //Not used in software
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#define PLL_A_LCK_OFST (4) //Not used in software
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#define PLL_A_LCK_MSK (0x00000001 << PLL_A_LCK_OFST) //Not used in software
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#define DD3_PLL_LCK_OFST (5) //Not used in software
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#define DD3_PLL_LCK_MSK (0x00000001 << DD3_PLL_LCK_OFST) //Not used in software
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/* Module Control Board Serial Number Register */
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#define MOD_SERIAL_NUM_REG (0x0A << 11) //Not used in software
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#define HARDWARE_SERIAL_NUM_OFST (0) //Not used in software
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#define HARDWARE_SERIAL_NUM_MSK (0x000000FF << HARDWARE_SERIAL_NUM_OFST) //Not used in software
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#define HARDWARE_VERSION_NUM_OFST (16) //Not used in software
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#define HARDWARE_VERSION_NUM_MSK (0x0000003F << HARDWARE_VERSION_NUM_OFST) //Not used in software
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/* Time from Start 64 bit register */
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#define TIME_FROM_START_LSB_REG (0x10 << 11)
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#define TIME_FROM_START_MSB_REG (0x11 << 11)
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/* Get Delay 64 bit register */
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#define GET_DELAY_LSB_REG (0x12 << 11)
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#define GET_DELAY_MSB_REG (0x13 << 11)
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/* Get Cycles 64 bit register */
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#define GET_CYCLES_LSB_REG (0x14 << 11)
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#define GET_CYCLES_MSB_REG (0x15 << 11)
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/* Get Frames 64 bit register */
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#define GET_FRAMES_LSB_REG (0x16 << 11)
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#define GET_FRAMES_MSB_REG (0x17 << 11)
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/* Get Period 64 bit register */
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#define GET_PERIOD_LSB_REG (0x18 << 11)
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#define GET_PERIOD_MSB_REG (0x19 << 11)
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/* Get Frames from Start 64 bit register (frames from start Run Control) */
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#define FRAMES_FROM_START_PG_LSB_REG (0x24 << 11)
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#define FRAMES_FROM_START_PG_MSB_REG (0x25 << 11)
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/* Measurement Time 64 bit register (timestamp at a frame start until reset)*/
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#define START_FRAME_TIME_LSB_REG (0x26 << 11)
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#define START_FRAME_TIME_MSB_REG (0x27 << 11)
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/* SPI (Serial Peripheral Interface) Register */
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#define SPI_REG (0x40 << 11)
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#define DAC_SERIAL_DIGITAL_OUT_OFST (0)
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#define DAC_SERIAL_DIGITAL_OUT_MSK (0x00000001 << DAC_SERIAL_DIGITAL_OUT_OFST)
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#define DAC_SERIAL_CLK_OUT_OFST (1)
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#define DAC_SERIAL_CLK_OUT_MSK (0x00000001 << DAC_SERIAL_CLK_OUT_OFST)
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#define DAC_SERIAL_CS_OUT_OFST (2)
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#define DAC_SERIAL_CS_OUT_MSK (0x00000001 << DAC_SERIAL_CS_OUT_OFST)
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#define HV_SERIAL_DIGITAL_OUT_OFST (8)
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#define HV_SERIAL_DIGITAL_OUT_MSK (0x00000001 << HV_SERIAL_DIGITAL_OUT_OFST)
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#define HV_SERIAL_CLK_OUT_OFST (9)
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#define HV_SERIAL_CLK_OUT_MSK (0x00000001 << HV_SERIAL_CLK_OUT_OFST)
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#define HV_SERIAL_CS_OUT_OFST (10)
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#define HV_SERIAL_CS_OUT_MSK (0x00000001 << HV_SERIAL_CS_OUT_OFST)
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/* ADC SPI (Serial Peripheral Interface) Register */
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#define ADC_SPI_REG (0x41 << 11)
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#define ADC_SERIAL_CLK_OUT_OFST (0)
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#define ADC_SERIAL_CLK_OUT_MSK (0x00000001 << ADC_SERIAL_CLK_OUT_OFST)
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#define ADC_SERIAL_DATA_OUT_OFST (1)
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#define ADC_SERIAL_DATA_OUT_MSK (0x00000001 << ADC_SERIAL_DATA_OUT_OFST)
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#define ADC_SERIAL_CS_OUT_OFST (2)
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#define ADC_SERIAL_CS_OUT_MSK (0x0000000F << ADC_SERIAL_CS_OUT_OFST)
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/* ADC offset Register */
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#define ADC_OFST_REG (0x42 << 11)
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/* ADC Port Invert Register */
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#define ADC_PORT_INVERT_REG (0x43 << 11)
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/* Receiver IP Address Register */
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#define RX_IP_REG (0x45 << 11)
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/* UDP Port */
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#define UDP_PORT_REG (0x46 << 11)
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#define UDP_PORT_RX_OFST (0)
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#define UDP_PORT_RX_MSK (0x0000FFFF << UDP_PORT_RX_OFST)
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#define UDP_PORT_TX_OFST (16)
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#define UDP_PORT_TX_MSK (0x0000FFFF << UDP_PORT_TX_OFST)
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/* Receiver Mac Address 64 bit Register */
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#define RX_MAC_LSB_REG (0x47 << 11)
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#define RX_MAC_MSB_REG (0x48 << 11)
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#define RX_MAC_LSB_OFST (0)
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#define RX_MAC_LSB_MSK (0x0000FFFF << RX_MAC_LSB_OFST)
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#define RX_MAC_MSB_OFST (0)
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#define RX_MAC_MSB_MSK (0x000000FF << RX_MAC_MSB_OFST)
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/* Detector/ Transmitter Mac Address 64 bit Register */
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#define TX_MAC_LSB_REG (0x49 << 11)
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#define TX_MAC_MSB_REG (0x4A << 11)
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#define TX_MAC_LSB_OFST (0)
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#define TX_MAC_LSB_MSK (0x0000FFFF << TX_MAC_LSB_OFST)
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#define TX_MAC_MSB_OFST (0)
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#define TX_MAC_MSB_MSK (0x000000FF << TX_MAC_MSB_OFST)
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/* Detector/ Transmitter IP Address Register */
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#define TX_IP_REG (0x4B << 11)
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/* Detector/ Transmitter IP Checksum Register */
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#define TX_IP_CHECKSUM_REG (0x4C << 11)
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#define TX_IP_CHECKSUM_OFST (0)
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#define TX_IP_CHECKSUM_MSK (0x000000FF << TX_IP_CHECKSUM_OFST)
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/* Configuration Register */
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#define CONFIG_REG (0x4D << 11)
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#define CONFIG_OPERATION_MODE_OFST (16)
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#define CONFIG_OPERATION_MODE_MSK (0x00000001 << CONFIG_OPERATION_MODE_OFST)
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#define CONFIG_MODE_1_X_10GBE_VAL ((0x0 << CONFIG_OPERATION_MODE_OFST) & CONFIG_OPERATION_MODE_MSK)
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#define CONFIG_MODE_2_X_10GBE_VAL ((0x1 << CONFIG_OPERATION_MODE_OFST) & CONFIG_OPERATION_MODE_MSK)
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#define CONFIG_READOUT_SPEED_OFST (20)
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#define CONFIG_READOUT_SPEED_MSK (0x00000003 << CONFIG_READOUT_SPEED_OFST)
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#define CONFIG_QUARTER_SPEED_10MHZ_VAL ((0x0 << CONFIG_READOUT_SPEED_OFST) & CONFIG_READOUT_SPEED_MSK)
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#define CONFIG_HALF_SPEED_20MHZ_VAL ((0x1 << CONFIG_READOUT_SPEED_OFST) & CONFIG_READOUT_SPEED_MSK)
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#define CONFIG_FULL_SPEED_40MHZ_VAL ((0x2 << CONFIG_READOUT_SPEED_OFST) & CONFIG_READOUT_SPEED_MSK)
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#define CONFIG_TDMA_OFST (24)
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#define CONFIG_TDMA_MSK (0x00000001 << CONFIG_TDMA_OFST)
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#define CONFIG_TDMA_DISABLE_VAL ((0x0 << CONFIG_TDMA_OFST) & CONFIG_TDMA_MSK)
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#define CONFIG_TDMA_ENABLE_VAL ((0x1 << CONFIG_TDMA_OFST) & CONFIG_TDMA_MSK)
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#define CONFIG_TDMA_TIMESLOT_OFST (25)
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#define CONFIG_TDMA_TIMESLOT_MSK (0x0000001F << CONFIG_TDMA_TIMESLOT_OFST)
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#define CONFIG_TDMA_TIMESLOT_0_VAL ((0x0 << CONFIG_TDMA_TIMESLOT_OFST) & CONFIG_TDMA_TIMESLOT_MSK)
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/* External Signal Register */
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#define EXT_SIGNAL_REG (0x4E << 11)
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#define EXT_SIGNAL_OFST (0)
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#define EXT_SIGNAL_MSK (0x00000003 << EXT_SIGNAL_OFST) //enabled when both bits high
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/* Control Register */
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#define CONTROL_REG (0x4F << 11)
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#define CONTROL_START_ACQ_OFST (0)
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#define CONTROL_START_ACQ_MSK (0x00000001 << CONTROL_START_ACQ_OFST)
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#define CONTROL_STOP_ACQ_OFST (1)
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#define CONTROL_STOP_ACQ_MSK (0x00000001 << CONTROL_STOP_ACQ_OFST)
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#define CONTROL_CORE_RST_OFST (10)
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#define CONTROL_CORE_RST_MSK (0x00000001 << CONTROL_CORE_RST_OFST)
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#define CONTROL_PERIPHERAL_RST_OFST (11) //DDR3 HMem Ctrlr, GBE, Temp
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#define CONTROL_PERIPHERAL_RST_MSK (0x00000001 << CONTROL_PERIPHERAL_RST_OFST) //DDR3 HMem Ctrlr, GBE, Temp
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#define CONTROL_DDR3_MEM_RST_OFST (12) //only PHY, not DDR3 PLL ,Not used in software
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#define CONTROL_DDR3_MEM_RST_MSK (0x00000001 << CONTROL_DDR3_MEM_RST_OFST) //only PHY, not DDR3 PLL ,Not used in software
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#define CONTROL_ACQ_FIFO_CLR_OFST (14)
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#define CONTROL_ACQ_FIFO_CLR_MSK (0x00000001 << CONTROL_ACQ_FIFO_CLR_OFST)
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/* Reconfiguratble PLL Paramater Register */
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#define PLL_PARAM_REG (0x50 << 11)
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/* Reconfiguratble PLL Control Regiser */
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#define PLL_CONTROL_REG (0x51 << 11)
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#define PLL_CTRL_RECONFIG_RST_OFST (0) //parameter reset
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#define PLL_CTRL_RECONFIG_RST_MSK (0x00000001 << PLL_CTRL_RECONFIG_RST_OFST) //parameter reset
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#define PLL_CTRL_WR_PARAMETER_OFST (2)
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#define PLL_CTRL_WR_PARAMETER_MSK (0x00000001 << PLL_CTRL_WR_PARAMETER_OFST)
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#define PLL_CTRL_RST_OFST (3)
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#define PLL_CTRL_RST_MSK (0x00000001 << PLL_CTRL_RST_OFST)
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#define PLL_CTRL_ADDR_OFST (16)
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#define PLL_CTRL_ADDR_MSK (0x0000003F << PLL_CTRL_ADDR_OFST)
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/* Sample Register (Obsolete) */
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#define SAMPLE_REG (0x59 << 11)
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#define SAMPLE_ADC_SAMPLE_SEL_OFST (0)
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#define SAMPLE_ADC_SAMPLE_SEL_MSK (0x00000007 << SAMPLE_ADC_SAMPLE_SEL_OFST)
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#define SAMPLE_ADC_SAMPLE_0_VAL ((0x0 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
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#define SAMPLE_ADC_SAMPLE_1_VAL ((0x1 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
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#define SAMPLE_ADC_SAMPLE_2_VAL ((0x2 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
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#define SAMPLE_ADC_SAMPLE_3_VAL ((0x3 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
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#define SAMPLE_ADC_SAMPLE_4_VAL ((0x4 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
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#define SAMPLE_ADC_SAMPLE_5_VAL ((0x5 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
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#define SAMPLE_ADC_SAMPLE_6_VAL ((0x6 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
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#define SAMPLE_ADC_SAMPLE_7_VAL ((0x7 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
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#define SAMPLE_ADC_DECMT_FACTOR_OFST (4)
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#define SAMPLE_ADC_DECMT_FACTOR_MSK (0x00000007 << SAMPLE_ADC_DECMT_FACTOR_OFST)
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#define SAMPLE_ADC_DECMT_FACTOR_0_VAL ((0x0 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
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#define SAMPLE_ADC_DECMT_FACTOR_1_VAL ((0x1 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
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#define SAMPLE_ADC_DECMT_FACTOR_2_VAL ((0x2 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
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#define SAMPLE_ADC_DECMT_FACTOR_3_VAL ((0x3 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
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#define SAMPLE_ADC_DECMT_FACTOR_4_VAL ((0x4 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
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#define SAMPLE_ADC_DECMT_FACTOR_5_VAL ((0x5 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
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#define SAMPLE_ADC_DECMT_FACTOR_6_VAL ((0x6 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
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#define SAMPLE_ADC_DECMT_FACTOR_7_VAL ((0x7 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
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#define SAMPLE_DGTL_SAMPLE_SEL_OFST (8)
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#define SAMPLE_DGTL_SAMPLE_SEL_MSK (0x0000000F << SAMPLE_DGTL_SAMPLE_SEL_OFST)
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#define SAMPLE_DGTL_SAMPLE_0_VAL ((0x0 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
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#define SAMPLE_DGTL_SAMPLE_1_VAL ((0x1 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
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#define SAMPLE_DGTL_SAMPLE_2_VAL ((0x2 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
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#define SAMPLE_DGTL_SAMPLE_3_VAL ((0x3 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
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#define SAMPLE_DGTL_SAMPLE_4_VAL ((0x4 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
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#define SAMPLE_DGTL_SAMPLE_5_VAL ((0x5 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
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#define SAMPLE_DGTL_SAMPLE_6_VAL ((0x6 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
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#define SAMPLE_DGTL_SAMPLE_7_VAL ((0x7 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
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#define SAMPLE_DGTL_SAMPLE_8_VAL ((0x8 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
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#define SAMPLE_DGTL_SAMPLE_9_VAL ((0x9 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
|
||||
#define SAMPLE_DGTL_SAMPLE_10_VAL ((0xa << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
|
||||
#define SAMPLE_DGTL_SAMPLE_11_VAL ((0xb << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
|
||||
#define SAMPLE_DGTL_SAMPLE_12_VAL ((0xc << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
|
||||
#define SAMPLE_DGTL_SAMPLE_13_VAL ((0xd << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
|
||||
#define SAMPLE_DGTL_SAMPLE_14_VAL ((0xe << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
|
||||
#define SAMPLE_DGTL_SAMPLE_15_VAL ((0xf << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
|
||||
|
||||
#define SAMPLE_DGTL_DECMT_FACTOR_OFST (12)
|
||||
#define SAMPLE_DGTL_DECMT_FACTOR_MSK (0x00000003 << SAMPLE_DGTL_DECMT_FACTOR_OFST)
|
||||
#define SAMPLE_DECMT_FACTOR_1_VAL ((0x0 << SAMPLE_DGTL_DECMT_FACTOR_OFST) & SAMPLE_DGTL_DECMT_FACTOR_MSK)
|
||||
#define SAMPLE_DECMT_FACTOR_2_VAL ((0x1 << SAMPLE_DGTL_DECMT_FACTOR_OFST) & SAMPLE_DGTL_DECMT_FACTOR_MSK)
|
||||
#define SAMPLE_DECMT_FACTOR_4_VAL ((0x2 << SAMPLE_DGTL_DECMT_FACTOR_OFST) & SAMPLE_DGTL_DECMT_FACTOR_MSK)
|
||||
|
||||
/** Vref Comp Mod Register */
|
||||
#define VREF_COMP_MOD_REG (0x5C << 11) //Not used in software, TBD in firmware
|
||||
|
||||
/** DAQ Register */
|
||||
#define DAQ_REG (0x5D << 11) //TBD in firmware
|
||||
|
||||
/** Chip Power Register */
|
||||
#define CHIP_POWER_REG (0x5E << 11)
|
||||
|
||||
#define CHIP_POWER_ENABLE_OFST (0)
|
||||
#define CHIP_POWER_ENABLE_MSK (0x00000001 << CHIP_POWER_ENABLE_OFST)
|
||||
|
||||
/* Set Delay 64 bit register */
|
||||
#define SET_DELAY_LSB_REG (0x60 << 11)
|
||||
#define SET_DELAY_MSB_REG (0x61 << 11)
|
||||
|
||||
/* Set Cycles 64 bit register */
|
||||
#define SET_CYCLES_LSB_REG (0x62 << 11)
|
||||
#define SET_CYCLES_MSB_REG (0x63 << 11)
|
||||
|
||||
/* Set Frames 64 bit register */
|
||||
#define SET_FRAMES_LSB_REG (0x64 << 11)
|
||||
#define SET_FRAMES_MSB_REG (0x65 << 11)
|
||||
|
||||
/* Set Period 64 bit register */
|
||||
#define SET_PERIOD_LSB_REG (0x66 << 11)
|
||||
#define SET_PERIOD_MSB_REG (0x67 << 11)
|
||||
|
||||
/* Set Period 64 bit register */
|
||||
#define SET_EXPTIME_LSB_REG (0x68 << 11)
|
||||
#define SET_EXPTIME_MSB_REG (0x69 << 11)
|
||||
|
||||
/* Module Coordinates Register 0 */
|
||||
#define COORD_0 (0x7C << 11)
|
||||
|
||||
#define COORD_0_Y_OFST (0)
|
||||
#define COORD_0_Y_MSK (0x0000FFFF << COORD_0_Y_OFST)
|
||||
#define COORD_0_X_OFST (16)
|
||||
#define COORD_0_X_MSK (0x0000FFFF << COORD_0_X_OFST)
|
||||
|
||||
/* Module Coordinates Register 1 */
|
||||
#define COORD_1 (0x7D << 11)
|
||||
|
||||
#define COORD_0_Z_OFST (0)
|
||||
#define COORD_0_Z_MSK (0x0000FFFF << COORD_0_Z_OFST)
|
||||
|
||||
|
||||
#endif //REGISTERS_G_H
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
1
slsDetectorSoftware/jungfrauDetectorServerNewStructure/ansi.h
Symbolic link
1
slsDetectorSoftware/jungfrauDetectorServerNewStructure/ansi.h
Symbolic link
@ -0,0 +1 @@
|
||||
../../slsReceiverSoftware/include/ansi.h
|
||||
@ -0,0 +1 @@
|
||||
../commonFiles/communication_funcs.c
|
||||
@ -0,0 +1 @@
|
||||
../commonFiles/communication_funcs.h
|
||||
@ -0,0 +1,9 @@
|
||||
Path: slsDetectorsPackage/slsDetectorSoftware/jungfrauDetectorServer
|
||||
URL: origin git@git.psi.ch:sls_detectors_software/sls_detector_software.git/jungfrauDetectorServer
|
||||
Repository Root: origin git@git.psi.ch:sls_detectors_software/sls_detector_software.git
|
||||
Repsitory UUID: 230d6b36e9852214f4ba5ae7c92647f35000b24d
|
||||
Revision: 56
|
||||
Branch: developer
|
||||
Last Changed Author: Dhanya_Maliakal
|
||||
Last Changed Rev: 1313
|
||||
Last Changed Date: 2016-11-30 10:36:34 +0100
|
||||
@ -0,0 +1,11 @@
|
||||
//#define SVNPATH ""
|
||||
#define SVNURL "git@git.psi.ch:sls_detectors_software/sls_detector_software.git/jungfrauDetectorServer"
|
||||
//#define SVNREPPATH ""
|
||||
#define SVNREPUUID "230d6b36e9852214f4ba5ae7c92647f35000b24d"
|
||||
//#define SVNREV 0x1313
|
||||
//#define SVNKIND ""
|
||||
//#define SVNSCHED ""
|
||||
#define SVNAUTH "Dhanya_Maliakal"
|
||||
#define SVNREV 0x1313
|
||||
#define SVNDATE 0x20161130
|
||||
//
|
||||
@ -0,0 +1,11 @@
|
||||
//#define SVNPATH ""
|
||||
#define SVNURL ""
|
||||
//#define SVNREPPATH ""
|
||||
#define SVNREPUUID ""
|
||||
//#define SVNREV ""
|
||||
//#define SVNKIND ""
|
||||
//#define SVNSCHED ""
|
||||
#define SVNAUTH ""
|
||||
#define SVNREV ""
|
||||
#define SVNDATE ""
|
||||
//
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1 @@
|
||||
../slsDetectorServer/slsDetectorFunctionList.h
|
||||
@ -0,0 +1 @@
|
||||
../slsDetectorServer/slsDetectorServer.c
|
||||
@ -0,0 +1,215 @@
|
||||
#ifndef SLSDETECTORSERVER_DEFS_H
|
||||
#define SLSDETECTORSERVER_DEFS_H
|
||||
|
||||
#include "sls_detector_defs.h" //default dynamicgain in settings
|
||||
#include "registers_m.h"
|
||||
#include <stdint.h>
|
||||
|
||||
|
||||
|
||||
#define GOODBYE (-200)
|
||||
//#define REQUIRED_FIRMWARE_VERSION 16
|
||||
//#define FIRMWAREREV 0xcaba //temporary should be in firmware
|
||||
enum clkspeed {FULL_SPEED, HALF_SPEED, QUARTER_SPEED};
|
||||
enum ADC_INDEX {TEMP_FPGA, TEMP_ADC};
|
||||
enum DAC_INDEX { VB_COMP, VDD_PROT, VIN_COM, VREF_PRECH, VB_PIXBUF, VB_DS, VREF_DS, VREF_COMP };
|
||||
#define DEFAULT_DAC_VALS { 1220, /* VB_COMP */ \
|
||||
3000, /* VDD_PROT */ \
|
||||
1053, /* VIN_COM */ \
|
||||
1450, /* VREF_PRECH */ \
|
||||
750, /* VB_PIXBUF */ \
|
||||
1000, /* VB_DS */ \
|
||||
480, /* VREF_DS */ \
|
||||
420 /* VREF_COMP */ \
|
||||
};
|
||||
|
||||
|
||||
/* Hardware Definitions */
|
||||
#define NMAXMODY (1)
|
||||
#define NMAXMODX (1)
|
||||
#define NMAXMOD (NMAXMODX * NMAXMODY)
|
||||
//#define NMODY (1)
|
||||
//#define NMODX (1)
|
||||
//#define NMOD (NMODX * NMODY)
|
||||
#define NCHAN (256 * 256)
|
||||
#define NCHIP (8)
|
||||
#define NADC (0)
|
||||
#define NDAC (8)
|
||||
#define NCHANS (NCHAN * NCHIP * NMAXMOD)
|
||||
#define NDACS (NDAC * NMAXMOD)
|
||||
#define DYNAMIC_RANGE (16)
|
||||
#define DATA_BYTES (NMAXMOD * NCHIP * NCHAN * 2)
|
||||
#define IP_PACKETSIZE (0x2052)
|
||||
#define CLK_RUN (40) /* MHz */
|
||||
#define CLK_SYNC (20) /* MHz */
|
||||
|
||||
|
||||
/** Default Parameters */
|
||||
#define DEFAULT_NUM_FRAMES (100*1000*1000)
|
||||
#define DEFAULT_NUM_CYCLES (1)
|
||||
#define DEFAULT_EXPTIME (10*1000) //ns
|
||||
#define DEFAULT_PERIOD (2*1000*1000) //ns
|
||||
#define DEFAULT_DELAY (0)
|
||||
#define DEFAULT_HIGH_VOLTAGE (0)
|
||||
#define DEFAULT_SETTINGS (DYNAMICGAIN)
|
||||
#define DEFAULT_TX_UDP_PORT (0x7e9a)
|
||||
|
||||
/* Defines in the Firmware */
|
||||
#define FIX_PATT_VAL (0xACDC2014)
|
||||
#define ADC_PORT_INVERT_VAL (0x453b2a9c)
|
||||
|
||||
|
||||
#define SAMPLE_ADC_HALF_SPEED (SAMPLE_DECMT_FACTOR_2_VAL + SAMPLE_DGTL_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_0_VAL + SAMPLE_ADC_SAMPLE_0_VAL) /* 0x1000 */
|
||||
#define SAMPLE_ADC_QUARTER_SPEED (SAMPLE_DECMT_FACTOR_4_VAL + SAMPLE_DGTL_SAMPLE_8_VAL + SAMPLE_ADC_DECMT_FACTOR_1_VAL + SAMPLE_ADC_SAMPLE_0_VAL) /* 0x2810 */
|
||||
#define CONFIG_HALF_SPEED (CONFIG_TDMA_TIMESLOT_0_VAL + CONFIG_TDMA_DISABLE_VAL + CONFIG_HALF_SPEED_20MHZ_VAL + CONFIG_MODE_1_X_10GBE_VAL)
|
||||
#define CONFIG_QUARTER_SPEED (CONFIG_TDMA_TIMESLOT_0_VAL + CONFIG_TDMA_DISABLE_VAL + CONFIG_QUARTER_SPEED_10MHZ_VAL + CONFIG_MODE_1_X_10GBE_VAL)
|
||||
#define ADC_OFST_HALF_SPEED_VAL (0x20) //adc pipeline
|
||||
#define ADC_OFST_QUARTER_SPEED_VAL (0x0f)
|
||||
#define ADC_PHASE_HALF_SPEED (0x41)
|
||||
#define ADC_PHASE_QUARTER_SPEED (0x19)
|
||||
|
||||
/* Maybe not required for jungfrau */
|
||||
#define NTRIMBITS (6)
|
||||
#define NCOUNTBITS (24)
|
||||
#define NCHIPS_PER_ADC (2)
|
||||
#define TRIM_DR (((int)pow(2,NTRIMBITS))-1)
|
||||
#define COUNT_DR (((int)pow(2,NCOUNTBITS))-1)
|
||||
#define ALLMOD (0xffff)
|
||||
#define ALLFIFO (0xffff)
|
||||
|
||||
/* LTC2620 DAC DEFINES */
|
||||
#define LTC2620_DAC_CMD_OFST (20)
|
||||
#define LTC2620_DAC_CMD_MSK (0x0000000F << LTC2620_DAC_CMD_OFST)
|
||||
#define LTC2620_DAC_ADDR_OFST (16)
|
||||
#define LTC2620_DAC_ADDR_MSK (0x0000000F << LTC2620_DAC_ADDR_OFST)
|
||||
#define LTC2620_DAC_DATA_OFST (4)
|
||||
#define LTC2620_DAC_DATA_MSK (0x00000FFF << LTC2620_DAC_DATA_OFST)
|
||||
|
||||
#define LTC2620_DAC_CMD_WRITE (0x00000000 << LTC2620_DAC_CMD_OFST)
|
||||
#define LTC2620_DAC_CMD_SET (0x00000003 << LTC2620_DAC_CMD_OFST)
|
||||
#define LTC2620_DAC_CMD_POWER_DOWN (0x00000004 << LTC2620_DAC_CMD_OFST)
|
||||
#define LTC2620_DAC_NUMBITS (24)
|
||||
|
||||
|
||||
/* MAX1932 HV DEFINES */
|
||||
#define MAX1932_HV_NUMBITS (8)
|
||||
#define MAX1932_HV_DATA_OFST (0)
|
||||
#define MAX1932_HV_DATA_MSK (0x000000FF << MAX1932_HV_DATA_OFST)
|
||||
|
||||
/* AD9257 ADC DEFINES */
|
||||
#define AD9257_ADC_NUMBITS (24)
|
||||
|
||||
#define AD9257_DEV_IND_2_REG (0x04)
|
||||
#define AD9257_CHAN_H_OFST (0)
|
||||
#define AD9257_CHAN_H_MSK (0x00000001 << AD9257_CHAN_H_OFST)
|
||||
#define AD9257_CHAN_G_OFST (1)
|
||||
#define AD9257_CHAN_G_MSK (0x00000001 << AD9257_CHAN_G_OFST)
|
||||
#define AD9257_CHAN_F_OFST (2)
|
||||
#define AD9257_CHAN_F_MSK (0x00000001 << AD9257_CHAN_F_OFST)
|
||||
#define AD9257_CHAN_E_OFST (3)
|
||||
#define AD9257_CHAN_E_MSK (0x00000001 << AD9257_CHAN_E_OFST)
|
||||
|
||||
#define AD9257_DEV_IND_1_REG (0x05)
|
||||
#define AD9257_CHAN_D_OFST (0)
|
||||
#define AD9257_CHAN_D_MSK (0x00000001 << AD9257_CHAN_D_OFST)
|
||||
#define AD9257_CHAN_C_OFST (1)
|
||||
#define AD9257_CHAN_C_MSK (0x00000001 << AD9257_CHAN_C_OFST)
|
||||
#define AD9257_CHAN_B_OFST (2)
|
||||
#define AD9257_CHAN_B_MSK (0x00000001 << AD9257_CHAN_B_OFST)
|
||||
#define AD9257_CHAN_A_OFST (3)
|
||||
#define AD9257_CHAN_A_MSK (0x00000001 << AD9257_CHAN_A_OFST)
|
||||
#define AD9257_CLK_CH_DCO_OFST (4)
|
||||
#define AD9257_CLK_CH_DCO_MSK (0x00000001 << AD9257_CLK_CH_DCO_OFST)
|
||||
#define AD9257_CLK_CH_IFCO_OFST (5)
|
||||
#define AD9257_CLK_CH_IFCO_MSK (0x00000001 << AD9257_CLK_CH_IFCO_OFST)
|
||||
|
||||
#define AD9257_POWER_MODE_REG (0x08)
|
||||
#define AD9257_POWER_INTERNAL_OFST (0)
|
||||
#define AD9257_POWER_INTERNAL_MSK (0x00000003 << AD9257_POWER_INTERNAL_OFST)
|
||||
#define AD9257_INT_RESET_VAL (0x3)
|
||||
#define AD9257_INT_CHIP_RUN_VAL (0x0)
|
||||
#define AD9257_POWER_EXTERNAL_OFST (5)
|
||||
#define AD9257_POWER_EXTERNAL_MSK (0x00000001 << AD9257_POWER_EXTERNAL_OFST)
|
||||
#define AD9257_EXT_FULL_POWER_VAL (0x0)
|
||||
#define AD9257_EXT_STANDBY_VAL (0x1)
|
||||
|
||||
#define AD9257_OUT_MODE_REG (0x14)
|
||||
#define AD9257_OUT_FORMAT_OFST (0)
|
||||
#define AD9257_OUT_FORMAT_MSK (0x00000001 << AD9257_OUT_FORMAT_OFST)
|
||||
#define AD9257_OUT_BINARY_OFST_VAL (0)
|
||||
#define AD9257_OUT_TWOS_COMPL_VAL (1)
|
||||
#define AD9257_OUT_LVDS_OPT_OFST (6)
|
||||
#define AD9257_OUT_LVDS_OPT_MSK (0x00000001 << AD9257_OUT_LVDS_OPT_OFST)
|
||||
#define AD9257_OUT_LVDS_ANSI_VAL (0)
|
||||
#define AD9257_OUT_LVDS_IEEE_VAL (1)
|
||||
|
||||
#define AD9257_OUT_PHASE_REG (0x16)
|
||||
#define AD9257_OUT_CLK_OFST (0)
|
||||
#define AD9257_OUT_CLK_MSK (0x0000000F << AD9257_OUT_CLK_OFST)
|
||||
#define AD9257_OUT_CLK_60_VAL (0x1)
|
||||
#define AD9257_IN_CLK_OFST (4)
|
||||
#define AD9257_IN_CLK_MSK (0x00000007 << AD9257_IN_CLK_OFST)
|
||||
#define AD9257_IN_CLK_0_VAL (0x0)
|
||||
|
||||
#define AD9257_VREF_REG (0x18)
|
||||
#define AD9257_VREF_OFST (0)
|
||||
#define AD9257_VREF_MSK (0x00000003 << AD9257_VREF_OFST)
|
||||
#define AD9257_VREF_1_33_VAL (0x2)
|
||||
|
||||
#define AD9257_TEST_MODE_REG (0x0D)
|
||||
#define AD9257_OUT_TEST_OFST (0)
|
||||
#define AD9257_OUT_TEST_MSK (0x0000000F << AD9257_OUT_TEST_OFST)
|
||||
#define AD9257_NONE_VAL (0x0)
|
||||
#define AD9257_MIXED_BIT_FREQ_VAL (0xC)
|
||||
#define AD9257_TEST_RESET_SHORT_GEN (4)
|
||||
#define AD9257_TEST_RESET_LONG_GEN (5)
|
||||
#define AD9257_USER_IN_MODE_OFST (6)
|
||||
#define AD9257_USER_IN_MODE_MSK (0x00000003 << AD9257_USER_IN_MODE_OFST)
|
||||
|
||||
/** PLL Reconfiguration Registers */
|
||||
//https://www.altera.com/documentation/mcn1424769382940.html
|
||||
#define PLL_MODE_REG (0x00)
|
||||
#define PLL_STATUS_REG (0x01)
|
||||
#define PLL_START_REG (0x02)
|
||||
#define PLL_N_COUNTER_REG (0x03)
|
||||
#define PLL_M_COUNTER_REG (0x04)
|
||||
#define PLL_C_COUNTER_REG (0x05)
|
||||
#define PLL_PHASE_SHIFT_REG (0x06)
|
||||
|
||||
#define PLL_SHIFT_NUM_SHIFTS_OFST (0)
|
||||
#define PLL_SHIFT_NUM_SHIFTS_MSK (0x0000FFFF << PLL_SHIFT_NUM_SHIFTS_OFST)
|
||||
|
||||
#define PLL_SHIFT_CNT_SELECT_OFST (16)
|
||||
#define PLL_SHIFT_CNT_SELECT_MSK (0x0000001F << PLL_SHIFT_CNT_SELECT_OFST)
|
||||
#define PLL_SHIFT_CNT_SLCT_C0_VAL (0x0 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
|
||||
#define PLL_SHIFT_CNT_SLCT_C1_VAL (0x1 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
|
||||
#define PLL_SHIFT_CNT_SLCT_C2_VAL (0x2 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
|
||||
#define PLL_SHIFT_CNT_SLCT_C3_VAL (0x3 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
|
||||
#define PLL_SHIFT_CNT_SLCT_C4_VAL (0x4 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
|
||||
#define PLL_SHIFT_CNT_SLCT_C5_VAL (0x5 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
|
||||
#define PLL_SHIFT_CNT_SLCT_C6_VAL (0x6 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
|
||||
#define PLL_SHIFT_CNT_SLCT_C7_VAL (0x7 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
|
||||
#define PLL_SHIFT_CNT_SLCT_C8_VAL (0x8 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
|
||||
#define PLL_SHIFT_CNT_SLCT_C9_VAL (0x9 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
|
||||
#define PLL_SHIFT_CNT_SLCT_C10_VAL (0x10 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
|
||||
#define PLL_SHIFT_CNT_SLCT_C11_VAL (0x11 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
|
||||
#define PLL_SHIFT_CNT_SLCT_C12_VAL (0x12 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
|
||||
#define PLL_SHIFT_CNT_SLCT_C13_VAL (0x13 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
|
||||
#define PLL_SHIFT_CNT_SLCT_C14_VAL (0x14 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
|
||||
#define PLL_SHIFT_CNT_SLCT_C15_VAL (0x15 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
|
||||
#define PLL_SHIFT_CNT_SLCT_C16_VAL (0x16 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
|
||||
#define PLL_SHIFT_CNT_SLCT_C17_VAL (0x17 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
|
||||
|
||||
#define PLL_SHIFT_UP_DOWN_OFST (21)
|
||||
#define PLL_SHIFT_UP_DOWN_MSK (0x00000001 << PLL_SHIFT_UP_DOWN_OFST)
|
||||
#define PLL_SHIFT_UP_DOWN_NEG_VAL ((0x0 << PLL_SHIFT_UP_DOWN_OFST) & PLL_SHIFT_UP_DOWN_MSK)
|
||||
#define PLL_SHIFT_UP_DOWN_POS_VAL ((0x1 << PLL_SHIFT_UP_DOWN_OFST) & PLL_SHIFT_UP_DOWN_MSK)
|
||||
|
||||
#define PLL_K_COUNTER_REG (0x07)
|
||||
#define PLL_BANDWIDTH_REG (0x08)
|
||||
#define PLL_CHARGEPUMP_REG (0x09)
|
||||
#define PLL_VCO_DIV_REG (0x1c)
|
||||
#define PLL_MIF_REG (0x1f)
|
||||
|
||||
|
||||
#endif /* SLSDETECTORSERVER_DEFS_H */
|
||||
@ -0,0 +1 @@
|
||||
../slsDetectorServer/slsDetectorServer_funcs.c
|
||||
@ -0,0 +1 @@
|
||||
../slsDetectorServer/slsDetectorServer_funcs.h
|
||||
@ -0,0 +1 @@
|
||||
../commonFiles/sls_detector_defs.h
|
||||
@ -0,0 +1 @@
|
||||
../commonFiles/sls_detector_funcs.h
|
||||
@ -0,0 +1 @@
|
||||
../../slsReceiverSoftware/include/sls_receiver_defs.h
|
||||
@ -0,0 +1 @@
|
||||
../../slsReceiverSoftware/include/sls_receiver_funcs.h
|
||||
Reference in New Issue
Block a user