mirror of
https://github.com/slsdetectorgroup/slsDetectorPackage.git
synced 2026-01-16 12:33:40 +01:00
mannnnyyyy changes to jungfrau serverin structure, also to eiger structure a bit
This commit is contained in:
@@ -6,7 +6,7 @@
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CROSS = bfin-uclinux-
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CC = $(CROSS)gcc
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CFLAGS += -Wall -DJUNGFRAUD -DMCB_FUNCS -DDACS_INT -DDEBUG -DV1 #-DVERBOSE #-DVERYVERBOSE #-DVIRTUAL
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CFLAGS += -Wall -DJUNGFRAUD -DMCB_FUNCS -DDACS_INT #-DVERBOSE #-DVERYVERBOSE #-DVIRTUAL
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PROGS= jungfrauDetectorServer
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File diff suppressed because it is too large
Load Diff
@@ -48,7 +48,7 @@ int stopWritingFPGAprogram(FILE* filefp);
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int writeFPGAProgram(char* fpgasrc, size_t fsize, FILE* filefp);
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long int calcChecksum(int sourceip, int destip);
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void configureMAC(uint32_t destip, uint64_t destmac, uint64_t sourcemac, int detipad, uint32_t destport);
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void configureMAC(uint32_t destip, uint64_t destmac, uint64_t sourcemac, int sourceip, uint32_t destport);
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int64_t set64BitReg(int64_t value, int aLSB, int aMSB);
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int64_t get64BitReg(int aLSB, int aMSB);
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@@ -74,9 +74,6 @@ int64_t getTrains();
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int64_t setProbes(int64_t value);
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int64_t getProbes();
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int64_t getProgress();
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int64_t setProgress();
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int64_t getActualTime();
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int64_t getMeasurementTime();
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int64_t getFramesFromStart();
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@@ -84,7 +81,6 @@ int64_t getFramesFromStart();
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u_int32_t runBusy(void);
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int startStateMachine();
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int stopStateMachine();
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int startReadOut();
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enum runStatus getStatus();
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void waitForAcquisitionEnd();
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@@ -93,7 +89,6 @@ void initDac(int dacnum);
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int setDac(int dacnum, int dacvalue);
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int setHighVoltage(int val, int imod);
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void setAdc(int addr, int val);
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void configureAdc();
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void prepareADC();
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int setDynamicRange(int dr);
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@@ -117,8 +112,7 @@ int initConfGain(int isettings,int val,int imod);
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int initSpeedConfGain(int val);
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void resetPLL();
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u_int32_t setPllReconfigReg(u_int32_t reg, u_int32_t val, int trig);
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u_int32_t getPllReconfigReg(u_int32_t reg, int trig);
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u_int32_t setPllReconfigReg(u_int32_t reg, u_int32_t val);
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void configurePll();
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int loadImage(int index, short int ImageVals[]);
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@@ -126,10 +120,6 @@ int readCounterBlock(int startACQ, short int CounterVals[]);
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int resetCounterBlock(int startACQ);
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int calibratePedestal(int frames);
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u_int32_t setExtSignal(int d, enum externalSignalFlag mode);
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int getExtSignal(int d);
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u_int32_t setFPGASignal(int d, enum externalSignalFlag mode);
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int getFPGASignal(int d);
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int setTiming(int t);
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int setMaster(int f);
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int setSynchronization(int s);
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@@ -176,19 +176,24 @@
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#define TX_IP_CHECKSUM_MSK (0x000000FF << TX_IP_CHECKSUM_OFST)
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/* Configuration Register */
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#define CONFIG_REG (0x4D << 11) //Not used in software Carlos
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#define CONFIG_REG (0x4D << 11)
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#define CONFIG_OPERATION_MODE_OFST (16) //Not used in software
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#define CONFIG_OPERATION_MODE_MSK (0x00000001 << CONFIG_OPERATION_MODE_OFST) //Not used in software
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#define CONFIG_READOUT_SPEED_OFST (20) //Not used in software
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#define CONFIG_READOUT_SPEED_MSK (0x00000003 << CONFIG_READOUT_SPEED_OFST) //Not used in software
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#define CONFIG_QUARTER_SPEED_10MHZ_VAL (0x0 << CONFIG_READOUT_SPEED_OFST) & CONFIG_READOUT_SPEED_MSK //Not used in software
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#define CONFIG_HALF_SPEED_20MHZ_VAL (0x1 << CONFIG_READOUT_SPEED_OFST) & CONFIG_READOUT_SPEED_MSK //Not used in software
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#define CONFIG_FULL_SPEED_VAL (0x2 << CONFIG_READOUT_SPEED_OFST) & CONFIG_READOUT_SPEED_MSK //Not used in software and firmware
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#define CONFIG_TDMA_OFST (24) //Not used in software
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#define CONFIG_TDMA_MSK (0x00000001 << CONFIG_TDMA_OFST) //Not used in software
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#define CONFIG_TDMA_TIMESLOT_OFST (25) //Not used in software
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#define CONFIG_TDMA_TIMESLOT_MSK (0x0000001F << CONFIG_TDMA_TIMESLOT_OFST) //Not used in software
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#define CONFIG_OPERATION_MODE_OFST (16)
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#define CONFIG_OPERATION_MODE_MSK (0x00000001 << CONFIG_OPERATION_MODE_OFST)
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#define CONFIG_MODE_1_X_10GBE_VAL ((0x0 << CONFIG_OPERATION_MODE_OFST) & CONFIG_OPERATION_MODE_MSK)
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#define CONFIG_MODE_2_X_10GBE_VAL ((0x1 << CONFIG_OPERATION_MODE_OFST) & CONFIG_OPERATION_MODE_MSK)
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#define CONFIG_READOUT_SPEED_OFST (20)
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#define CONFIG_READOUT_SPEED_MSK (0x00000003 << CONFIG_READOUT_SPEED_OFST)
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#define CONFIG_QUARTER_SPEED_10MHZ_VAL ((0x0 << CONFIG_READOUT_SPEED_OFST) & CONFIG_READOUT_SPEED_MSK)
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#define CONFIG_HALF_SPEED_20MHZ_VAL ((0x1 << CONFIG_READOUT_SPEED_OFST) & CONFIG_READOUT_SPEED_MSK)
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#define CONFIG_FULL_SPEED_VAL ((0x2 << CONFIG_READOUT_SPEED_OFST) & CONFIG_READOUT_SPEED_MSK)
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#define CONFIG_TDMA_OFST (24)
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#define CONFIG_TDMA_MSK (0x00000001 << CONFIG_TDMA_OFST)
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#define CONFIG_TDMA_DISABLE_VAL ((0x0 << CONFIG_TDMA_OFST) & CONFIG_TDMA_MSK)
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#define CONFIG_TDMA_ENABLE_VAL ((0x1 << CONFIG_TDMA_OFST) & CONFIG_TDMA_MSK)
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#define CONFIG_TDMA_TIMESLOT_OFST (25)
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#define CONFIG_TDMA_TIMESLOT_MSK (0x0000001F << CONFIG_TDMA_TIMESLOT_OFST)
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#define CONFIG_TDMA_TIMESLOT_0_VAL ((0x0 << CONFIG_TDMA_TIMESLOT_OFST) & CONFIG_TDMA_TIMESLOT_MSK)
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/* External Signal Register */
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#define EXT_SIGNAL_REG (0x4E << 11)
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@@ -228,28 +233,54 @@
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#define PLL_CTRL_ADDR_MSK (0x0000003F << PLL_CTRL_ADDR_OFST)
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/* Sample Register (Obsolete) */
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#define SAMPLE_REG (0x59 << 11)/** is it dbit pipeline?... look at speedvariable */
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#define SAMPLE_REG (0x59 << 11) /** carlos set speed differently*/
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#define SAMPLE_ADC_SAMPLE_SEL_OFST (0) /** carlos cant use the bits*/
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#define SAMPLE_ADC_SAMPLE_SEL_MSK (0x00000007 << SAMPLE_ADC_SAMPLE_SEL_OFST)
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#define SAMPLE_ADC_SAMPLE_0_VAL ((0x0 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
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#define SAMPLE_ADC_SAMPLE_1_VAL ((0x1 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
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#define SAMPLE_ADC_SAMPLE_2_VAL ((0x2 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
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#define SAMPLE_ADC_SAMPLE_3_VAL ((0x3 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
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#define SAMPLE_ADC_SAMPLE_4_VAL ((0x4 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
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#define SAMPLE_ADC_SAMPLE_5_VAL ((0x5 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
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#define SAMPLE_ADC_SAMPLE_6_VAL ((0x6 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
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#define SAMPLE_ADC_SAMPLE_7_VAL ((0x7 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
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#define SAMPLE_ADC_DECMT_FACTOR_OFST (4)
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#define SAMPLE_ADC_DECMT_FACTOR_MSK (0x00000007 << SAMPLE_ADC_DECMT_FACTOR_OFST)
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#define SAMPLE_ADC_DECMT_FACTOR_0_VAL ((0x0 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
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#define SAMPLE_ADC_DECMT_FACTOR_1_VAL ((0x1 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
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#define SAMPLE_ADC_DECMT_FACTOR_2_VAL ((0x2 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
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#define SAMPLE_ADC_DECMT_FACTOR_3_VAL ((0x3 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
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#define SAMPLE_ADC_DECMT_FACTOR_4_VAL ((0x4 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
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#define SAMPLE_ADC_DECMT_FACTOR_5_VAL ((0x5 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
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#define SAMPLE_ADC_DECMT_FACTOR_6_VAL ((0x6 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
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#define SAMPLE_ADC_DECMT_FACTOR_7_VAL ((0x7 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
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#define SAMPLE_DGTL_SAMPLE_SEL_OFST (8)
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#define SAMPLE_DGTL_SAMPLE_SEL_MSK (0x00000007 << SAMPLE_DGTL_SAMPLE_SEL_OFST)
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#define SAMPLE_DGTL_SAMPLE_SEL_MSK (0x0000000F << SAMPLE_DGTL_SAMPLE_SEL_OFST)
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#define SAMPLE_DGTL_SAMPLE_0_VAL ((0x0 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
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#define SAMPLE_DGTL_SAMPLE_1_VAL ((0x1 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
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#define SAMPLE_DGTL_SAMPLE_2_VAL ((0x2 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
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#define SAMPLE_DGTL_SAMPLE_3_VAL ((0x3 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
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#define SAMPLE_DGTL_SAMPLE_4_VAL ((0x4 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
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#define SAMPLE_DGTL_SAMPLE_5_VAL ((0x5 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
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#define SAMPLE_DGTL_SAMPLE_6_VAL ((0x6 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
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#define SAMPLE_DGTL_SAMPLE_7_VAL ((0x7 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
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#define SAMPLE_DGTL_SAMPLE_8_VAL ((0x8 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
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#define SAMPLE_DGTL_SAMPLE_9_VAL ((0x9 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
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#define SAMPLE_DGTL_SAMPLE_10_VAL ((0xa << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
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#define SAMPLE_DGTL_SAMPLE_11_VAL ((0xb << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
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#define SAMPLE_DGTL_SAMPLE_12_VAL ((0xc << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
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#define SAMPLE_DGTL_SAMPLE_13_VAL ((0xd << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
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#define SAMPLE_DGTL_SAMPLE_14_VAL ((0xe << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
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#define SAMPLE_DGTL_SAMPLE_15_VAL ((0xf << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
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#define SAMPLE_DGTL_DECMT_FACTOR_OFST (12)
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#define SAMPLE_DGTL_DECMT_FACTOR_MSK (0x00000007 << SAMPLE_DGTL_DECMT_FACTOR_OFST)
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/* Digital Bit Alignment Register (Obsolete) */
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#define BIT_ALIGN_REG (0x59 << 11)/** carlos same reg value */
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#define BIT_ALIGN_LSB_SAMPLE_SEL_OFST (0)
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#define BIT_ALIGN_LSB_SAMPLE_SEL_MSK (0x00000007 << BIT_ALIGN_LSB_SAMPLE_SEL_OFST)
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#define BIT_ALIGN_LSB_LATENCY_OFST (3)
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#define BIT_ALIGN_LSB_LATENCY_MSK (0x0000001F << BIT_ALIGN_LSB_LATENCY_OFST)
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#define BIT_ALIGN_MSB_SAMPLE_SEL_OFST (8)
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#define BIT_ALIGN_MSB_SAMPLE_SEL_MSK (0x00000007 << BIT_ALIGN_MSB_SAMPLE_SEL_OFST)
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#define BIT_ALIGN_MSB_LATENCY_OFST (11)
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#define BIT_ALIGN_MSB_LATENCY_MSK (0x0000001F << BIT_ALIGN_MSB_LATENCY_OFST)
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#define SAMPLE_DGTL_DECMT_FACTOR_MSK (0x00000003 << SAMPLE_DGTL_DECMT_FACTOR_OFST)
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#define SAMPLE_DECMT_FACTOR_1_VAL ((0x0 << SAMPLE_DGTL_DECMT_FACTOR_OFST) & SAMPLE_DGTL_DECMT_FACTOR_MSK)
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#define SAMPLE_DECMT_FACTOR_2_VAL ((0x1 << SAMPLE_DGTL_DECMT_FACTOR_OFST) & SAMPLE_DGTL_DECMT_FACTOR_MSK)
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#define SAMPLE_DECMT_FACTOR_4_VAL ((0x2 << SAMPLE_DGTL_DECMT_FACTOR_OFST) & SAMPLE_DGTL_DECMT_FACTOR_MSK)
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/** Vref Comp Mod Register */
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#define VREF_COMP_MOD_REG (0x5C << 11) //Not used in software, TBD in firmware
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@@ -318,20 +349,6 @@
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#define SET_GATES_LSB_REG 106<<11//0x7c<<11
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#define SET_GATES_MSB_REG 107<<11//0x7d<<11
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#define PLL_RECONFIG_BUSY 0x00100000
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/* for external signal register */ /** Carlos is this implemented?*/
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#define SIGNAL_OFFSET 4
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#define SIGNAL_MASK 0xF
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#define EXT_SIG_OFF 0x0
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#define EXT_GATE_IN_ACTIVEHIGH 0x1
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#define EXT_GATE_IN_ACTIVELOW 0x2
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#define EXT_TRIG_IN_RISING 0x3
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#define EXT_TRIG_IN_FALLING 0x4
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//...
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/**ADC SYNC CLEAN FIFO*/
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#define ADCSYNC_CLEAN_FIFO_BITS 0x300000
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@@ -39,9 +39,8 @@ const enum detectorType myDetectorType=GENERIC;
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int (*flist[256])(int);
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char mess[MAX_STR_LENGTH];
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int digitalTestBit = 0; /** Carlos will we use this somewhere */
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int adcvpp = 0x4; /** Carlos will we use this somewhere */
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//set adc val??
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@@ -609,7 +608,7 @@ int digital_test(int file_des) {
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case DETECTOR_SOFTWARE_TEST:
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retval=testFpga();
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break;
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case DIGITAL_BIT_TEST:
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case DIGITAL_BIT_TEST:// only for gotthard
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n = receiveDataOnly(file_des,&ival,sizeof(ival));
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if (n < 0) {
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sprintf(mess,"Error reading from socket\n");
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@@ -623,8 +622,6 @@ int digital_test(int file_des) {
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sprintf(mess,"Detector locked by %s\n",lastClientIP);
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break;
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}
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digitalTestBit = ival;
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retval=digitalTestBit;
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break;
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default:
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printf("Unknown digital test required %d\n",arg);
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@@ -687,15 +684,9 @@ int write_register(int file_des) {
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if(ret!=FAIL){
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address=(addr<<11);
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/*if((address==FIFO_DATA_REG_OFF)||(address==CONTROL_REG)) ask Carlos
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ret = bus_w16(address,val);
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else*/
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ret=bus_w(address,val);
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if(ret==OK){
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/*if((address==FIFO_DATA_REG_OFF)||(address==CONTROL_REG)) ask Carlos
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retval=bus_r16(address);
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else*/
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retval=bus_r(address);
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retval=bus_r(address);
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}
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}
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@@ -753,10 +744,7 @@ int read_register(int file_des) {
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if(ret!=FAIL){
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address=(addr<<11);
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/*if((address==FIFO_DATA_REG_OFF)||(address==CONTROL_REG)) ask Carlos
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retval=bus_r16(address);
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else*/
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retval=bus_r(address);
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retval=bus_r(address);
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}
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@@ -1595,26 +1583,11 @@ int stop_acquisition(int file_des) {
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int start_readout(int file_des) {
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int ret=OK;
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int n;
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int ret = FAIL;
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sprintf(mess,"can't start readout\n");
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#ifdef VERBOSE
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printf("Starting readout\n");
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#endif
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if (differentClients==1 && lockStatus==1) {
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ret=FAIL;
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sprintf(mess,"Detector locked by %s\n",lastClientIP);
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} else {
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ret=startReadOut();
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}
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if (ret==FAIL)
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sprintf(mess,"Start readout failed\n");
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else if (differentClients)
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ret=FORCE_UPDATE;
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strcpy(mess, "Start Readout is not implemented for this detector!\n");
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cprintf(RED,"Warning: %s", mess);
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n = sendDataOnly(file_des,&ret,sizeof(ret));
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if (ret==FAIL) {
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@@ -1858,7 +1831,7 @@ int get_time_left(int file_des) {
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retval=getFrames();
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break;
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case ACQUISITION_TIME:
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retval=getExposureTime();
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retval=getExposureTime();/** not implemented */
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break;
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case FRAME_PERIOD:
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retval=getPeriod();
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@@ -1867,7 +1840,7 @@ int get_time_left(int file_des) {
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retval=getDelay();
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break;
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case GATES_NUMBER:
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retval=getGates();
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retval=getGates();/** not implemented */
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break;
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case PROBES_NUMBER:
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retval=getProbes();
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@@ -1875,9 +1848,6 @@ int get_time_left(int file_des) {
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case CYCLES_NUMBER:
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retval=getTrains();
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break;
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case PROGRESS:
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retval=getProgress();
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break;
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case ACTUAL_TIME:
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retval=getActualTime();
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break;
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