mannnnyyyy changes to jungfrau serverin structure, also to eiger structure a bit

This commit is contained in:
Dhanya Maliakal
2017-05-26 18:14:44 +02:00
parent 046ac97a9b
commit f74710998d
29 changed files with 2409 additions and 1181 deletions

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@@ -6,7 +6,7 @@
CROSS = bfin-uclinux-
CC = $(CROSS)gcc
CFLAGS += -Wall -DJUNGFRAUD -DMCB_FUNCS -DDACS_INT -DDEBUG -DV1 #-DVERBOSE #-DVERYVERBOSE #-DVIRTUAL
CFLAGS += -Wall -DJUNGFRAUD -DMCB_FUNCS -DDACS_INT #-DVERBOSE #-DVERYVERBOSE #-DVIRTUAL
PROGS= jungfrauDetectorServer

File diff suppressed because it is too large Load Diff

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@@ -48,7 +48,7 @@ int stopWritingFPGAprogram(FILE* filefp);
int writeFPGAProgram(char* fpgasrc, size_t fsize, FILE* filefp);
long int calcChecksum(int sourceip, int destip);
void configureMAC(uint32_t destip, uint64_t destmac, uint64_t sourcemac, int detipad, uint32_t destport);
void configureMAC(uint32_t destip, uint64_t destmac, uint64_t sourcemac, int sourceip, uint32_t destport);
int64_t set64BitReg(int64_t value, int aLSB, int aMSB);
int64_t get64BitReg(int aLSB, int aMSB);
@@ -74,9 +74,6 @@ int64_t getTrains();
int64_t setProbes(int64_t value);
int64_t getProbes();
int64_t getProgress();
int64_t setProgress();
int64_t getActualTime();
int64_t getMeasurementTime();
int64_t getFramesFromStart();
@@ -84,7 +81,6 @@ int64_t getFramesFromStart();
u_int32_t runBusy(void);
int startStateMachine();
int stopStateMachine();
int startReadOut();
enum runStatus getStatus();
void waitForAcquisitionEnd();
@@ -93,7 +89,6 @@ void initDac(int dacnum);
int setDac(int dacnum, int dacvalue);
int setHighVoltage(int val, int imod);
void setAdc(int addr, int val);
void configureAdc();
void prepareADC();
int setDynamicRange(int dr);
@@ -117,8 +112,7 @@ int initConfGain(int isettings,int val,int imod);
int initSpeedConfGain(int val);
void resetPLL();
u_int32_t setPllReconfigReg(u_int32_t reg, u_int32_t val, int trig);
u_int32_t getPllReconfigReg(u_int32_t reg, int trig);
u_int32_t setPllReconfigReg(u_int32_t reg, u_int32_t val);
void configurePll();
int loadImage(int index, short int ImageVals[]);
@@ -126,10 +120,6 @@ int readCounterBlock(int startACQ, short int CounterVals[]);
int resetCounterBlock(int startACQ);
int calibratePedestal(int frames);
u_int32_t setExtSignal(int d, enum externalSignalFlag mode);
int getExtSignal(int d);
u_int32_t setFPGASignal(int d, enum externalSignalFlag mode);
int getFPGASignal(int d);
int setTiming(int t);
int setMaster(int f);
int setSynchronization(int s);

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@@ -176,19 +176,24 @@
#define TX_IP_CHECKSUM_MSK (0x000000FF << TX_IP_CHECKSUM_OFST)
/* Configuration Register */
#define CONFIG_REG (0x4D << 11) //Not used in software Carlos
#define CONFIG_REG (0x4D << 11)
#define CONFIG_OPERATION_MODE_OFST (16) //Not used in software
#define CONFIG_OPERATION_MODE_MSK (0x00000001 << CONFIG_OPERATION_MODE_OFST) //Not used in software
#define CONFIG_READOUT_SPEED_OFST (20) //Not used in software
#define CONFIG_READOUT_SPEED_MSK (0x00000003 << CONFIG_READOUT_SPEED_OFST) //Not used in software
#define CONFIG_QUARTER_SPEED_10MHZ_VAL (0x0 << CONFIG_READOUT_SPEED_OFST) & CONFIG_READOUT_SPEED_MSK //Not used in software
#define CONFIG_HALF_SPEED_20MHZ_VAL (0x1 << CONFIG_READOUT_SPEED_OFST) & CONFIG_READOUT_SPEED_MSK //Not used in software
#define CONFIG_FULL_SPEED_VAL (0x2 << CONFIG_READOUT_SPEED_OFST) & CONFIG_READOUT_SPEED_MSK //Not used in software and firmware
#define CONFIG_TDMA_OFST (24) //Not used in software
#define CONFIG_TDMA_MSK (0x00000001 << CONFIG_TDMA_OFST) //Not used in software
#define CONFIG_TDMA_TIMESLOT_OFST (25) //Not used in software
#define CONFIG_TDMA_TIMESLOT_MSK (0x0000001F << CONFIG_TDMA_TIMESLOT_OFST) //Not used in software
#define CONFIG_OPERATION_MODE_OFST (16)
#define CONFIG_OPERATION_MODE_MSK (0x00000001 << CONFIG_OPERATION_MODE_OFST)
#define CONFIG_MODE_1_X_10GBE_VAL ((0x0 << CONFIG_OPERATION_MODE_OFST) & CONFIG_OPERATION_MODE_MSK)
#define CONFIG_MODE_2_X_10GBE_VAL ((0x1 << CONFIG_OPERATION_MODE_OFST) & CONFIG_OPERATION_MODE_MSK)
#define CONFIG_READOUT_SPEED_OFST (20)
#define CONFIG_READOUT_SPEED_MSK (0x00000003 << CONFIG_READOUT_SPEED_OFST)
#define CONFIG_QUARTER_SPEED_10MHZ_VAL ((0x0 << CONFIG_READOUT_SPEED_OFST) & CONFIG_READOUT_SPEED_MSK)
#define CONFIG_HALF_SPEED_20MHZ_VAL ((0x1 << CONFIG_READOUT_SPEED_OFST) & CONFIG_READOUT_SPEED_MSK)
#define CONFIG_FULL_SPEED_VAL ((0x2 << CONFIG_READOUT_SPEED_OFST) & CONFIG_READOUT_SPEED_MSK)
#define CONFIG_TDMA_OFST (24)
#define CONFIG_TDMA_MSK (0x00000001 << CONFIG_TDMA_OFST)
#define CONFIG_TDMA_DISABLE_VAL ((0x0 << CONFIG_TDMA_OFST) & CONFIG_TDMA_MSK)
#define CONFIG_TDMA_ENABLE_VAL ((0x1 << CONFIG_TDMA_OFST) & CONFIG_TDMA_MSK)
#define CONFIG_TDMA_TIMESLOT_OFST (25)
#define CONFIG_TDMA_TIMESLOT_MSK (0x0000001F << CONFIG_TDMA_TIMESLOT_OFST)
#define CONFIG_TDMA_TIMESLOT_0_VAL ((0x0 << CONFIG_TDMA_TIMESLOT_OFST) & CONFIG_TDMA_TIMESLOT_MSK)
/* External Signal Register */
#define EXT_SIGNAL_REG (0x4E << 11)
@@ -228,28 +233,54 @@
#define PLL_CTRL_ADDR_MSK (0x0000003F << PLL_CTRL_ADDR_OFST)
/* Sample Register (Obsolete) */
#define SAMPLE_REG (0x59 << 11)/** is it dbit pipeline?... look at speedvariable */
#define SAMPLE_REG (0x59 << 11) /** carlos set speed differently*/
#define SAMPLE_ADC_SAMPLE_SEL_OFST (0) /** carlos cant use the bits*/
#define SAMPLE_ADC_SAMPLE_SEL_MSK (0x00000007 << SAMPLE_ADC_SAMPLE_SEL_OFST)
#define SAMPLE_ADC_SAMPLE_0_VAL ((0x0 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
#define SAMPLE_ADC_SAMPLE_1_VAL ((0x1 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
#define SAMPLE_ADC_SAMPLE_2_VAL ((0x2 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
#define SAMPLE_ADC_SAMPLE_3_VAL ((0x3 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
#define SAMPLE_ADC_SAMPLE_4_VAL ((0x4 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
#define SAMPLE_ADC_SAMPLE_5_VAL ((0x5 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
#define SAMPLE_ADC_SAMPLE_6_VAL ((0x6 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
#define SAMPLE_ADC_SAMPLE_7_VAL ((0x7 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
#define SAMPLE_ADC_DECMT_FACTOR_OFST (4)
#define SAMPLE_ADC_DECMT_FACTOR_MSK (0x00000007 << SAMPLE_ADC_DECMT_FACTOR_OFST)
#define SAMPLE_ADC_DECMT_FACTOR_0_VAL ((0x0 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
#define SAMPLE_ADC_DECMT_FACTOR_1_VAL ((0x1 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
#define SAMPLE_ADC_DECMT_FACTOR_2_VAL ((0x2 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
#define SAMPLE_ADC_DECMT_FACTOR_3_VAL ((0x3 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
#define SAMPLE_ADC_DECMT_FACTOR_4_VAL ((0x4 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
#define SAMPLE_ADC_DECMT_FACTOR_5_VAL ((0x5 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
#define SAMPLE_ADC_DECMT_FACTOR_6_VAL ((0x6 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
#define SAMPLE_ADC_DECMT_FACTOR_7_VAL ((0x7 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
#define SAMPLE_DGTL_SAMPLE_SEL_OFST (8)
#define SAMPLE_DGTL_SAMPLE_SEL_MSK (0x00000007 << SAMPLE_DGTL_SAMPLE_SEL_OFST)
#define SAMPLE_DGTL_SAMPLE_SEL_MSK (0x0000000F << SAMPLE_DGTL_SAMPLE_SEL_OFST)
#define SAMPLE_DGTL_SAMPLE_0_VAL ((0x0 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_1_VAL ((0x1 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_2_VAL ((0x2 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_3_VAL ((0x3 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_4_VAL ((0x4 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_5_VAL ((0x5 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_6_VAL ((0x6 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_7_VAL ((0x7 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_8_VAL ((0x8 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_9_VAL ((0x9 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_10_VAL ((0xa << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_11_VAL ((0xb << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_12_VAL ((0xc << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_13_VAL ((0xd << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_14_VAL ((0xe << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_15_VAL ((0xf << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_DECMT_FACTOR_OFST (12)
#define SAMPLE_DGTL_DECMT_FACTOR_MSK (0x00000007 << SAMPLE_DGTL_DECMT_FACTOR_OFST)
/* Digital Bit Alignment Register (Obsolete) */
#define BIT_ALIGN_REG (0x59 << 11)/** carlos same reg value */
#define BIT_ALIGN_LSB_SAMPLE_SEL_OFST (0)
#define BIT_ALIGN_LSB_SAMPLE_SEL_MSK (0x00000007 << BIT_ALIGN_LSB_SAMPLE_SEL_OFST)
#define BIT_ALIGN_LSB_LATENCY_OFST (3)
#define BIT_ALIGN_LSB_LATENCY_MSK (0x0000001F << BIT_ALIGN_LSB_LATENCY_OFST)
#define BIT_ALIGN_MSB_SAMPLE_SEL_OFST (8)
#define BIT_ALIGN_MSB_SAMPLE_SEL_MSK (0x00000007 << BIT_ALIGN_MSB_SAMPLE_SEL_OFST)
#define BIT_ALIGN_MSB_LATENCY_OFST (11)
#define BIT_ALIGN_MSB_LATENCY_MSK (0x0000001F << BIT_ALIGN_MSB_LATENCY_OFST)
#define SAMPLE_DGTL_DECMT_FACTOR_MSK (0x00000003 << SAMPLE_DGTL_DECMT_FACTOR_OFST)
#define SAMPLE_DECMT_FACTOR_1_VAL ((0x0 << SAMPLE_DGTL_DECMT_FACTOR_OFST) & SAMPLE_DGTL_DECMT_FACTOR_MSK)
#define SAMPLE_DECMT_FACTOR_2_VAL ((0x1 << SAMPLE_DGTL_DECMT_FACTOR_OFST) & SAMPLE_DGTL_DECMT_FACTOR_MSK)
#define SAMPLE_DECMT_FACTOR_4_VAL ((0x2 << SAMPLE_DGTL_DECMT_FACTOR_OFST) & SAMPLE_DGTL_DECMT_FACTOR_MSK)
/** Vref Comp Mod Register */
#define VREF_COMP_MOD_REG (0x5C << 11) //Not used in software, TBD in firmware
@@ -318,20 +349,6 @@
#define SET_GATES_LSB_REG 106<<11//0x7c<<11
#define SET_GATES_MSB_REG 107<<11//0x7d<<11
#define PLL_RECONFIG_BUSY 0x00100000
/* for external signal register */ /** Carlos is this implemented?*/
#define SIGNAL_OFFSET 4
#define SIGNAL_MASK 0xF
#define EXT_SIG_OFF 0x0
#define EXT_GATE_IN_ACTIVEHIGH 0x1
#define EXT_GATE_IN_ACTIVELOW 0x2
#define EXT_TRIG_IN_RISING 0x3
#define EXT_TRIG_IN_FALLING 0x4
//...
/**ADC SYNC CLEAN FIFO*/
#define ADCSYNC_CLEAN_FIFO_BITS 0x300000

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@@ -39,9 +39,8 @@ const enum detectorType myDetectorType=GENERIC;
int (*flist[256])(int);
char mess[MAX_STR_LENGTH];
int digitalTestBit = 0; /** Carlos will we use this somewhere */
int adcvpp = 0x4; /** Carlos will we use this somewhere */
//set adc val??
@@ -609,7 +608,7 @@ int digital_test(int file_des) {
case DETECTOR_SOFTWARE_TEST:
retval=testFpga();
break;
case DIGITAL_BIT_TEST:
case DIGITAL_BIT_TEST:// only for gotthard
n = receiveDataOnly(file_des,&ival,sizeof(ival));
if (n < 0) {
sprintf(mess,"Error reading from socket\n");
@@ -623,8 +622,6 @@ int digital_test(int file_des) {
sprintf(mess,"Detector locked by %s\n",lastClientIP);
break;
}
digitalTestBit = ival;
retval=digitalTestBit;
break;
default:
printf("Unknown digital test required %d\n",arg);
@@ -687,15 +684,9 @@ int write_register(int file_des) {
if(ret!=FAIL){
address=(addr<<11);
/*if((address==FIFO_DATA_REG_OFF)||(address==CONTROL_REG)) ask Carlos
ret = bus_w16(address,val);
else*/
ret=bus_w(address,val);
if(ret==OK){
/*if((address==FIFO_DATA_REG_OFF)||(address==CONTROL_REG)) ask Carlos
retval=bus_r16(address);
else*/
retval=bus_r(address);
retval=bus_r(address);
}
}
@@ -753,10 +744,7 @@ int read_register(int file_des) {
if(ret!=FAIL){
address=(addr<<11);
/*if((address==FIFO_DATA_REG_OFF)||(address==CONTROL_REG)) ask Carlos
retval=bus_r16(address);
else*/
retval=bus_r(address);
retval=bus_r(address);
}
@@ -1595,26 +1583,11 @@ int stop_acquisition(int file_des) {
int start_readout(int file_des) {
int ret=OK;
int n;
int ret = FAIL;
sprintf(mess,"can't start readout\n");
#ifdef VERBOSE
printf("Starting readout\n");
#endif
if (differentClients==1 && lockStatus==1) {
ret=FAIL;
sprintf(mess,"Detector locked by %s\n",lastClientIP);
} else {
ret=startReadOut();
}
if (ret==FAIL)
sprintf(mess,"Start readout failed\n");
else if (differentClients)
ret=FORCE_UPDATE;
strcpy(mess, "Start Readout is not implemented for this detector!\n");
cprintf(RED,"Warning: %s", mess);
n = sendDataOnly(file_des,&ret,sizeof(ret));
if (ret==FAIL) {
@@ -1858,7 +1831,7 @@ int get_time_left(int file_des) {
retval=getFrames();
break;
case ACQUISITION_TIME:
retval=getExposureTime();
retval=getExposureTime();/** not implemented */
break;
case FRAME_PERIOD:
retval=getPeriod();
@@ -1867,7 +1840,7 @@ int get_time_left(int file_des) {
retval=getDelay();
break;
case GATES_NUMBER:
retval=getGates();
retval=getGates();/** not implemented */
break;
case PROBES_NUMBER:
retval=getProbes();
@@ -1875,9 +1848,6 @@ int get_time_left(int file_des) {
case CYCLES_NUMBER:
retval=getTrains();
break;
case PROGRESS:
retval=getProgress();
break;
case ACTUAL_TIME:
retval=getActualTime();
break;