detectors/slsDetectorPackage
25
0
Fork 0
mirror of https://github.com/slsdetectorgroup/slsDetectorPackage.git synced 2025-06-23 18:17:59 +02:00
Code Issues Actions Packages Releases Activity

minor print in temp_Fpgafl in eiger

Browse Source
This commit is contained in:
maliakal_d
2020-09-18 14:18:19 +02:00
parent 0906efaf31
commit f6dd02acc2
2 changed files with 8 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
slsDetectorServers/eigerDetectorServer/slsDetectorFunctionList.c
View File

@ -1313,9 +1313,9 @@ int getADC(enum ADCINDEX ind) {
return 0; return 0;
#else #else
int retval = -1; int retval = -1;
char tempnames[6][20] = {"FPGA EXT", "10GE", "DCDC", char *adc_names[] = {ADC_NAMES};
"SODL", "SODR", "FPGA"};
char cstore[255]; char cstore[255];
memset(cstore, 0, 255);
switch (ind) { switch (ind) {
case TEMP_FPGA: case TEMP_FPGA:
@ -1348,7 +1348,7 @@ int getADC(enum ADCINDEX ind) {
} }
LOG(logINFO, LOG(logINFO,
("Temperature %s: %f°C\n", tempnames[ind], (double)retval / 1000.00)); ("Temperature %s: %f°C\n", adc_names[ind], (double)retval / 1000.00));
return retval; return retval;
#endif #endif

6
slsDetectorServers/eigerDetectorServer/slsDetectorServer_defs.h
View File

@ -63,6 +63,10 @@ enum ADCINDEX {
TEMP_FPGAFEBL, TEMP_FPGAFEBL,
TEMP_FPGAFEBR TEMP_FPGAFEBR
}; };
#define ADC_NAMES \
"FPGA EXT", "10GE", "DCDC", "SODL", "SODR", "FPGA", "FPGA_FL", "FPGA_FR"
enum NETWORKINDEX { TXN_LEFT, TXN_RIGHT, TXN_FRAME, FLOWCTRL_10G }; enum NETWORKINDEX { TXN_LEFT, TXN_RIGHT, TXN_FRAME, FLOWCTRL_10G };
enum ROINDEX { E_PARALLEL, E_NON_PARALLEL }; enum ROINDEX { E_PARALLEL, E_NON_PARALLEL };
enum CLKINDEX { RUN_CLK, NUM_CLOCKS }; enum CLKINDEX { RUN_CLK, NUM_CLOCKS };
@ -130,7 +134,7 @@ enum MASTERINDEX { MASTER_HARDWARE, OW_MASTER, OW_SLAVE };
#define DAC_MAX_STEPS (4096) #define DAC_MAX_STEPS (4096)
#define MAX_SUBFRAME_EXPOSURE_VAL_IN_10NS \ #define MAX_SUBFRAME_EXPOSURE_VAL_IN_10NS \
(0x1FFFFFFF) // 29 bit register for max subframe exposure value (0x1FFFFFFF) // 29 bit register for max subframe exposure value
#define SLAVE_HIGH_VOLTAGE_READ_VAL (-999) #define SLAVE_HIGH_VOLTAGE_READ_VAL (-999)
#define HIGH_VOLTAGE_TOLERANCE (5) #define HIGH_VOLTAGE_TOLERANCE (5)