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minor print in temp_Fpgafl in eiger

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maliakal_d
2020-09-18 14:18:19 +02:00
parent 0906efaf31
commit f6dd02acc2
2 changed files with 8 additions and 4 deletions
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6
slsDetectorServers/eigerDetectorServer/slsDetectorServer_defs.h
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@ -63,6 +63,10 @@ enum ADCINDEX {
TEMP_FPGAFEBL,
TEMP_FPGAFEBR
};
#define ADC_NAMES \
"FPGA EXT", "10GE", "DCDC", "SODL", "SODR", "FPGA", "FPGA_FL", "FPGA_FR"
enum NETWORKINDEX { TXN_LEFT, TXN_RIGHT, TXN_FRAME, FLOWCTRL_10G };
enum ROINDEX { E_PARALLEL, E_NON_PARALLEL };
enum CLKINDEX { RUN_CLK, NUM_CLOCKS };
@ -130,7 +134,7 @@ enum MASTERINDEX { MASTER_HARDWARE, OW_MASTER, OW_SLAVE };
#define DAC_MAX_STEPS (4096)
#define MAX_SUBFRAME_EXPOSURE_VAL_IN_10NS \
(0x1FFFFFFF) // 29 bit register for max subframe exposure value
(0x1FFFFFFF) // 29 bit register for max subframe exposure value
#define SLAVE_HIGH_VOLTAGE_READ_VAL (-999)
#define HIGH_VOLTAGE_TOLERANCE (5)