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Merge branch 'developer' into eiger

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This commit is contained in:
Dhanya Thattil
2020-06-16 16:55:49 +02:00
committed by GitHub
parent ffb1a59df0 7609a2bda4
commit f078e6147d
5 changed files with 23 additions and 23 deletions
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4
slsDetectorServers/eigerDetectorServer/CMakeLists.txt
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@ -58,7 +58,7 @@ target_compile_definitions(eigerDetectorServerSlaveTop_virtual
) )
target_link_libraries(eigerDetectorServerSlaveTop_virtual target_link_libraries(eigerDetectorServerSlaveTop_virtual
PUBLIC pthread rt PUBLIC pthread rt slsProjectCSettings
) )
set_target_properties(eigerDetectorServerSlaveTop_virtual PROPERTIES set_target_properties(eigerDetectorServerSlaveTop_virtual PROPERTIES
@ -86,7 +86,7 @@ target_compile_definitions(eigerDetectorServerSlaveBottom_virtual
) )
target_link_libraries(eigerDetectorServerSlaveBottom_virtual target_link_libraries(eigerDetectorServerSlaveBottom_virtual
PUBLIC pthread rt PUBLIC pthread rt slsProjectCSettings
) )
set_target_properties(eigerDetectorServerSlaveBottom_virtual PROPERTIES set_target_properties(eigerDetectorServerSlaveBottom_virtual PROPERTIES

BIN
slsDetectorServers/mythen3DetectorServer/bin/mythen3DetectorServer_developer
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32
slsDetectorServers/mythen3DetectorServer/slsDetectorFunctionList.c
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@ -813,12 +813,12 @@ int setPeriod(int64_t val) {
return FAIL; return FAIL;
} }
LOG(logINFO, ("Setting period %lld ns\n", (long long int)val)); LOG(logINFO, ("Setting period %lld ns\n", (long long int)val));
val *= (1E-9 * getFrequency(SYSTEM_C2)); val *= (1E-9 * getFrequency(SYSTEM_C0));
set64BitReg(val, SET_PERIOD_LSB_REG, SET_PERIOD_MSB_REG); set64BitReg(val, SET_PERIOD_LSB_REG, SET_PERIOD_MSB_REG);
// validate for tolerance // validate for tolerance
int64_t retval = getPeriod(); int64_t retval = getPeriod();
val /= (1E-9 * getFrequency(SYSTEM_C2)); val /= (1E-9 * getFrequency(SYSTEM_C0));
if (val != retval) { if (val != retval) {
return FAIL; return FAIL;
} }
@ -827,7 +827,7 @@ int setPeriod(int64_t val) {
int64_t getPeriod() { int64_t getPeriod() {
return get64BitReg(SET_PERIOD_LSB_REG, SET_PERIOD_MSB_REG) / return get64BitReg(SET_PERIOD_LSB_REG, SET_PERIOD_MSB_REG) /
(1E-9 * getFrequency(SYSTEM_C2)); (1E-9 * getFrequency(SYSTEM_C0));
} }
void setNumIntGates(int val) { void setNumIntGates(int val) {
@ -860,7 +860,7 @@ void updateGatePeriod() {
} }
} }
LOG(logINFO, ("\tSetting Gate Period to %lld ns\n", (long long int)max)); LOG(logINFO, ("\tSetting Gate Period to %lld ns\n", (long long int)max));
max *= (1E-9 * getFrequency(SYSTEM_C2)); max *= (1E-9 * getFrequency(SYSTEM_C0));
set64BitReg(max, ASIC_EXP_GATE_PERIOD_LSB_REG, set64BitReg(max, ASIC_EXP_GATE_PERIOD_LSB_REG,
ASIC_EXP_GATE_PERIOD_MSB_REG); ASIC_EXP_GATE_PERIOD_MSB_REG);
} }
@ -868,7 +868,7 @@ void updateGatePeriod() {
int64_t getGatePeriod() { int64_t getGatePeriod() {
return get64BitReg(ASIC_EXP_GATE_PERIOD_LSB_REG, return get64BitReg(ASIC_EXP_GATE_PERIOD_LSB_REG,
ASIC_EXP_GATE_PERIOD_MSB_REG) / ASIC_EXP_GATE_PERIOD_MSB_REG) /
(1E-9 * getFrequency(SYSTEM_C2)); (1E-9 * getFrequency(SYSTEM_C0));
} }
int setExpTime(int gateIndex, int64_t val) { int setExpTime(int gateIndex, int64_t val) {
@ -898,12 +898,12 @@ int setExpTime(int gateIndex, int64_t val) {
} }
LOG(logINFO, ("Setting exptime %lld ns (index:%d)\n", (long long int)val, LOG(logINFO, ("Setting exptime %lld ns (index:%d)\n", (long long int)val,
gateIndex)); gateIndex));
val *= (1E-9 * getFrequency(SYSTEM_C2)); val *= (1E-9 * getFrequency(SYSTEM_C0));
set64BitReg(val, alsb, amsb); set64BitReg(val, alsb, amsb);
// validate for tolerance // validate for tolerance
int64_t retval = getExpTime(gateIndex); int64_t retval = getExpTime(gateIndex);
val /= (1E-9 * getFrequency(SYSTEM_C2)); val /= (1E-9 * getFrequency(SYSTEM_C0));
if (val != retval) { if (val != retval) {
return FAIL; return FAIL;
} }
@ -933,7 +933,7 @@ int64_t getExpTime(int gateIndex) {
LOG(logERROR, ("Invalid gate index: %d\n", gateIndex)); LOG(logERROR, ("Invalid gate index: %d\n", gateIndex));
return -1; return -1;
} }
return get64BitReg(alsb, amsb) / (1E-9 * getFrequency(SYSTEM_C2)); return get64BitReg(alsb, amsb) / (1E-9 * getFrequency(SYSTEM_C0));
} }
int setGateDelay(int gateIndex, int64_t val) { int setGateDelay(int gateIndex, int64_t val) {
@ -963,12 +963,12 @@ int setGateDelay(int gateIndex, int64_t val) {
} }
LOG(logINFO, ("Setting gate delay %lld ns (index:%d)\n", (long long int)val, LOG(logINFO, ("Setting gate delay %lld ns (index:%d)\n", (long long int)val,
gateIndex)); gateIndex));
val *= (1E-9 * getFrequency(SYSTEM_C2)); val *= (1E-9 * getFrequency(SYSTEM_C0));
set64BitReg(val, alsb, amsb); set64BitReg(val, alsb, amsb);
// validate for tolerance // validate for tolerance
int64_t retval = getGateDelay(gateIndex); int64_t retval = getGateDelay(gateIndex);
val /= (1E-9 * getFrequency(SYSTEM_C2)); val /= (1E-9 * getFrequency(SYSTEM_C0));
if (val != retval) { if (val != retval) {
return FAIL; return FAIL;
} }
@ -998,7 +998,7 @@ int64_t getGateDelay(int gateIndex) {
LOG(logERROR, ("Invalid gate index: %d\n", gateIndex)); LOG(logERROR, ("Invalid gate index: %d\n", gateIndex));
return -1; return -1;
} }
return get64BitReg(alsb, amsb) / (1E-9 * getFrequency(SYSTEM_C2)); return get64BitReg(alsb, amsb) / (1E-9 * getFrequency(SYSTEM_C0));
} }
void setCounterMask(uint32_t arg) { void setCounterMask(uint32_t arg) {
@ -1027,12 +1027,12 @@ int setDelayAfterTrigger(int64_t val) {
return FAIL; return FAIL;
} }
LOG(logINFO, ("Setting delay after trigger %lld ns\n", (long long int)val)); LOG(logINFO, ("Setting delay after trigger %lld ns\n", (long long int)val));
val *= (1E-9 * getFrequency(SYSTEM_C2)); val *= (1E-9 * getFrequency(SYSTEM_C0));
set64BitReg(val, SET_TRIGGER_DELAY_LSB_REG, SET_TRIGGER_DELAY_MSB_REG); set64BitReg(val, SET_TRIGGER_DELAY_LSB_REG, SET_TRIGGER_DELAY_MSB_REG);
// validate for tolerance // validate for tolerance
int64_t retval = getDelayAfterTrigger(); int64_t retval = getDelayAfterTrigger();
val /= (1E-9 * getFrequency(SYSTEM_C2)); val /= (1E-9 * getFrequency(SYSTEM_C0));
if (val != retval) { if (val != retval) {
return FAIL; return FAIL;
} }
@ -1041,7 +1041,7 @@ int setDelayAfterTrigger(int64_t val) {
int64_t getDelayAfterTrigger() { int64_t getDelayAfterTrigger() {
return get64BitReg(SET_TRIGGER_DELAY_LSB_REG, SET_TRIGGER_DELAY_MSB_REG) / return get64BitReg(SET_TRIGGER_DELAY_LSB_REG, SET_TRIGGER_DELAY_MSB_REG) /
(1E-9 * getFrequency(SYSTEM_C2)); (1E-9 * getFrequency(SYSTEM_C0));
} }
int64_t getNumFramesLeft() { int64_t getNumFramesLeft() {
@ -1054,12 +1054,12 @@ int64_t getNumTriggersLeft() {
int64_t getDelayAfterTriggerLeft() { int64_t getDelayAfterTriggerLeft() {
return get64BitReg(GET_DELAY_LSB_REG, GET_DELAY_MSB_REG) / return get64BitReg(GET_DELAY_LSB_REG, GET_DELAY_MSB_REG) /
(1E-9 * getFrequency(SYSTEM_C2)); (1E-9 * getFrequency(SYSTEM_C0));
} }
int64_t getPeriodLeft() { int64_t getPeriodLeft() {
return get64BitReg(GET_PERIOD_LSB_REG, GET_PERIOD_MSB_REG) / return get64BitReg(GET_PERIOD_LSB_REG, GET_PERIOD_MSB_REG) /
(1E-9 * getFrequency(SYSTEM_C2)); (1E-9 * getFrequency(SYSTEM_C0));
} }
int64_t getFramesFromStart() { int64_t getFramesFromStart() {

8
slsDetectorServers/mythen3DetectorServer/slsDetectorServer_defs.h
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@ -37,9 +37,9 @@
#define DEFAULT_TIMING_MODE (AUTO_TIMING) #define DEFAULT_TIMING_MODE (AUTO_TIMING)
#define DEFAULT_READOUT_C0 (10) //(125000000) // rdo_clk, 125 MHz #define DEFAULT_READOUT_C0 (10) //(125000000) // rdo_clk, 125 MHz
#define DEFAULT_READOUT_C1 (10) //(125000000) // rdo_x2_clk, 125 MHz #define DEFAULT_READOUT_C1 (10) //(125000000) // rdo_x2_clk, 125 MHz
#define DEFAULT_SYSTEM_C0 (5) //(250000000) // run_clk, 250 MHz #define DEFAULT_SYSTEM_C0 (4) //(250000000) // run_clk, 250 MHz
#define DEFAULT_SYSTEM_C1 (10) //(125000000) // chip_clk, 125 MHz #define DEFAULT_SYSTEM_C1 (8) //(125000000) // chip_clk, 125 MHz
#define DEFAULT_SYSTEM_C2 (10) //(125000000) // sync_clk, 125 MHz #define DEFAULT_SYSTEM_C2 (8) //(125000000) // sync_clk, 125 MHz
#define DEFAULT_ASIC_LATCHING_NUM_PULSES (10) #define DEFAULT_ASIC_LATCHING_NUM_PULSES (10)
#define DEFAULT_MSTR_OTPT_P1_NUM_PULSES (20) #define DEFAULT_MSTR_OTPT_P1_NUM_PULSES (20)
@ -47,7 +47,7 @@
#define IP_HEADER_SIZE (20) #define IP_HEADER_SIZE (20)
#define FIXED_PLL_FREQUENCY (020000000) // 20MHz #define FIXED_PLL_FREQUENCY (020000000) // 20MHz
#define READOUT_PLL_VCO_FREQ_HZ (1250000000) // 1.25GHz #define READOUT_PLL_VCO_FREQ_HZ (1250000000) // 1.25GHz
#define SYSTEM_PLL_VCO_FREQ_HZ (1250000000) // 1.25GHz #define SYSTEM_PLL_VCO_FREQ_HZ (1000000000) // 1GHz
#define MAX_PATTERN_LENGTH (0x2000) // maximum number of words (64bit) #define MAX_PATTERN_LENGTH (0x2000) // maximum number of words (64bit)
/** Other Definitions */ /** Other Definitions */

2
slsSupportLib/include/versionAPI.h
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@ -6,7 +6,7 @@
#define APICTB 0x200610 #define APICTB 0x200610
#define APIGOTTHARD 0x200610 #define APIGOTTHARD 0x200610
#define APIJUNGFRAU 0x200610 #define APIJUNGFRAU 0x200610
#define APIMYTHEN3 0x200610
#define APIMOENCH 0x200610 #define APIMOENCH 0x200610
#define APIGOTTHARD2 0x200610 #define APIGOTTHARD2 0x200610
#define APIEIGER 0x200616 #define APIEIGER 0x200616
#define APIMYTHEN3 0x200616