mirror of
https://github.com/slsdetectorgroup/slsDetectorPackage.git
synced 2025-06-12 21:07:13 +02:00
Merge branch 'developer' into eiger
This commit is contained in:
@ -58,7 +58,7 @@ target_compile_definitions(eigerDetectorServerSlaveTop_virtual
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)
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target_link_libraries(eigerDetectorServerSlaveTop_virtual
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PUBLIC pthread rt
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PUBLIC pthread rt slsProjectCSettings
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)
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set_target_properties(eigerDetectorServerSlaveTop_virtual PROPERTIES
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@ -86,7 +86,7 @@ target_compile_definitions(eigerDetectorServerSlaveBottom_virtual
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)
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target_link_libraries(eigerDetectorServerSlaveBottom_virtual
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PUBLIC pthread rt
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PUBLIC pthread rt slsProjectCSettings
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)
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set_target_properties(eigerDetectorServerSlaveBottom_virtual PROPERTIES
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Binary file not shown.
@ -813,12 +813,12 @@ int setPeriod(int64_t val) {
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return FAIL;
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}
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LOG(logINFO, ("Setting period %lld ns\n", (long long int)val));
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val *= (1E-9 * getFrequency(SYSTEM_C2));
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val *= (1E-9 * getFrequency(SYSTEM_C0));
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set64BitReg(val, SET_PERIOD_LSB_REG, SET_PERIOD_MSB_REG);
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// validate for tolerance
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int64_t retval = getPeriod();
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val /= (1E-9 * getFrequency(SYSTEM_C2));
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val /= (1E-9 * getFrequency(SYSTEM_C0));
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if (val != retval) {
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return FAIL;
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}
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@ -827,7 +827,7 @@ int setPeriod(int64_t val) {
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int64_t getPeriod() {
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return get64BitReg(SET_PERIOD_LSB_REG, SET_PERIOD_MSB_REG) /
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(1E-9 * getFrequency(SYSTEM_C2));
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(1E-9 * getFrequency(SYSTEM_C0));
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}
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void setNumIntGates(int val) {
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@ -860,7 +860,7 @@ void updateGatePeriod() {
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}
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}
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LOG(logINFO, ("\tSetting Gate Period to %lld ns\n", (long long int)max));
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max *= (1E-9 * getFrequency(SYSTEM_C2));
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max *= (1E-9 * getFrequency(SYSTEM_C0));
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set64BitReg(max, ASIC_EXP_GATE_PERIOD_LSB_REG,
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ASIC_EXP_GATE_PERIOD_MSB_REG);
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}
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@ -868,7 +868,7 @@ void updateGatePeriod() {
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int64_t getGatePeriod() {
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return get64BitReg(ASIC_EXP_GATE_PERIOD_LSB_REG,
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ASIC_EXP_GATE_PERIOD_MSB_REG) /
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(1E-9 * getFrequency(SYSTEM_C2));
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(1E-9 * getFrequency(SYSTEM_C0));
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}
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int setExpTime(int gateIndex, int64_t val) {
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@ -898,12 +898,12 @@ int setExpTime(int gateIndex, int64_t val) {
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}
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LOG(logINFO, ("Setting exptime %lld ns (index:%d)\n", (long long int)val,
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gateIndex));
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val *= (1E-9 * getFrequency(SYSTEM_C2));
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val *= (1E-9 * getFrequency(SYSTEM_C0));
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set64BitReg(val, alsb, amsb);
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// validate for tolerance
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int64_t retval = getExpTime(gateIndex);
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val /= (1E-9 * getFrequency(SYSTEM_C2));
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val /= (1E-9 * getFrequency(SYSTEM_C0));
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if (val != retval) {
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return FAIL;
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}
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@ -933,7 +933,7 @@ int64_t getExpTime(int gateIndex) {
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LOG(logERROR, ("Invalid gate index: %d\n", gateIndex));
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return -1;
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}
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return get64BitReg(alsb, amsb) / (1E-9 * getFrequency(SYSTEM_C2));
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return get64BitReg(alsb, amsb) / (1E-9 * getFrequency(SYSTEM_C0));
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}
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int setGateDelay(int gateIndex, int64_t val) {
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@ -963,12 +963,12 @@ int setGateDelay(int gateIndex, int64_t val) {
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}
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LOG(logINFO, ("Setting gate delay %lld ns (index:%d)\n", (long long int)val,
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gateIndex));
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val *= (1E-9 * getFrequency(SYSTEM_C2));
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val *= (1E-9 * getFrequency(SYSTEM_C0));
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set64BitReg(val, alsb, amsb);
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// validate for tolerance
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int64_t retval = getGateDelay(gateIndex);
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val /= (1E-9 * getFrequency(SYSTEM_C2));
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val /= (1E-9 * getFrequency(SYSTEM_C0));
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if (val != retval) {
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return FAIL;
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}
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@ -998,7 +998,7 @@ int64_t getGateDelay(int gateIndex) {
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LOG(logERROR, ("Invalid gate index: %d\n", gateIndex));
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return -1;
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}
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return get64BitReg(alsb, amsb) / (1E-9 * getFrequency(SYSTEM_C2));
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return get64BitReg(alsb, amsb) / (1E-9 * getFrequency(SYSTEM_C0));
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}
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void setCounterMask(uint32_t arg) {
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@ -1027,12 +1027,12 @@ int setDelayAfterTrigger(int64_t val) {
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return FAIL;
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}
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LOG(logINFO, ("Setting delay after trigger %lld ns\n", (long long int)val));
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val *= (1E-9 * getFrequency(SYSTEM_C2));
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val *= (1E-9 * getFrequency(SYSTEM_C0));
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set64BitReg(val, SET_TRIGGER_DELAY_LSB_REG, SET_TRIGGER_DELAY_MSB_REG);
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// validate for tolerance
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int64_t retval = getDelayAfterTrigger();
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val /= (1E-9 * getFrequency(SYSTEM_C2));
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val /= (1E-9 * getFrequency(SYSTEM_C0));
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if (val != retval) {
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return FAIL;
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}
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@ -1041,7 +1041,7 @@ int setDelayAfterTrigger(int64_t val) {
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int64_t getDelayAfterTrigger() {
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return get64BitReg(SET_TRIGGER_DELAY_LSB_REG, SET_TRIGGER_DELAY_MSB_REG) /
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(1E-9 * getFrequency(SYSTEM_C2));
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(1E-9 * getFrequency(SYSTEM_C0));
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}
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int64_t getNumFramesLeft() {
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@ -1054,12 +1054,12 @@ int64_t getNumTriggersLeft() {
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int64_t getDelayAfterTriggerLeft() {
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return get64BitReg(GET_DELAY_LSB_REG, GET_DELAY_MSB_REG) /
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(1E-9 * getFrequency(SYSTEM_C2));
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(1E-9 * getFrequency(SYSTEM_C0));
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}
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int64_t getPeriodLeft() {
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return get64BitReg(GET_PERIOD_LSB_REG, GET_PERIOD_MSB_REG) /
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(1E-9 * getFrequency(SYSTEM_C2));
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(1E-9 * getFrequency(SYSTEM_C0));
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}
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int64_t getFramesFromStart() {
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@ -37,9 +37,9 @@
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#define DEFAULT_TIMING_MODE (AUTO_TIMING)
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#define DEFAULT_READOUT_C0 (10) //(125000000) // rdo_clk, 125 MHz
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#define DEFAULT_READOUT_C1 (10) //(125000000) // rdo_x2_clk, 125 MHz
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#define DEFAULT_SYSTEM_C0 (5) //(250000000) // run_clk, 250 MHz
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#define DEFAULT_SYSTEM_C1 (10) //(125000000) // chip_clk, 125 MHz
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#define DEFAULT_SYSTEM_C2 (10) //(125000000) // sync_clk, 125 MHz
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#define DEFAULT_SYSTEM_C0 (4) //(250000000) // run_clk, 250 MHz
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#define DEFAULT_SYSTEM_C1 (8) //(125000000) // chip_clk, 125 MHz
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#define DEFAULT_SYSTEM_C2 (8) //(125000000) // sync_clk, 125 MHz
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#define DEFAULT_ASIC_LATCHING_NUM_PULSES (10)
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#define DEFAULT_MSTR_OTPT_P1_NUM_PULSES (20)
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@ -47,7 +47,7 @@
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#define IP_HEADER_SIZE (20)
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#define FIXED_PLL_FREQUENCY (020000000) // 20MHz
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#define READOUT_PLL_VCO_FREQ_HZ (1250000000) // 1.25GHz
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#define SYSTEM_PLL_VCO_FREQ_HZ (1250000000) // 1.25GHz
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#define SYSTEM_PLL_VCO_FREQ_HZ (1000000000) // 1GHz
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#define MAX_PATTERN_LENGTH (0x2000) // maximum number of words (64bit)
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/** Other Definitions */
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@ -6,7 +6,7 @@
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#define APICTB 0x200610
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#define APIGOTTHARD 0x200610
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#define APIJUNGFRAU 0x200610
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#define APIMYTHEN3 0x200610
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#define APIMOENCH 0x200610
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#define APIGOTTHARD2 0x200610
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#define APIEIGER 0x200616
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#define APIMYTHEN3 0x200616
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