mirror of
https://github.com/slsdetectorgroup/slsDetectorPackage.git
synced 2025-06-12 21:07:13 +02:00
gotthard2 with veto data on second interface
This commit is contained in:
@ -1,110 +1,112 @@
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#pragma once
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// clang-format off
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#define REG_OFFSET (4)
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/* Base addresses 0x1804 0000 ---------------------------------------------*/
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/* Reconfiguration core for readout pll */
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#define BASE_READOUT_PLL (0x0000) // 0x1804_0000 - 0x1804_07FF
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#define BASE_READOUT_PLL (0x0000) // 0x1804_0000 - 0x1804_07FF
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/* Reconfiguration core for system pll */
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#define BASE_SYSTEM_PLL (0x0800) // 0x1804_0800 - 0x1804_0FFF
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#define BASE_SYSTEM_PLL (0x0800) // 0x1804_0800 - 0x1804_0FFF
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/* Clock Generation */
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#define BASE_CLK_GENERATION (0x1000) // 0x1804_1000 - 0x1804_XXXX //TODO
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/* Base addresses 0x1806 0000 ---------------------------------------------*/
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/* General purpose control and status registers */
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#define BASE_CONTROL (0x0000) // 0x1806_0000 - 0x1806_00FF
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#define BASE_CONTROL (0x0000) // 0x1806_0000 - 0x1806_00FF
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// https://git.psi.ch/sls_detectors_firmware/gotthard_II_mcb/blob/master/code/hdl/ctrl/ctrl.vhd
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/* ASIC Control */
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#define BASE_ASIC (0x0100) // 0x1806_0100 - 0x1806_011F
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#define BASE_ASIC (0x0100) // 0x1806_0100 - 0x1806_011F
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// https://git.psi.ch/sls_detectors_firmware/gotthard_II_mcb/blob/master/code/hdl/asic/asic_ctrl.vhd
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/* ASIC Digital Interface. Data recovery core */
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#define BASE_ADIF (0x0120) // 0x1806_0120 - 0x1806_012F
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#define BASE_ADIF (0x0120) // 0x1806_0120 - 0x1806_012F
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// https://git.psi.ch/sls_detectors_firmware/gotthard_II_mcb/blob/master/code/hdl/adif/adif_ctrl.vhd
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/* Formatting of data core */
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#define BASE_FMT (0x0130) // 0x1806_0130 - 0x1806_013F
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#define BASE_FMT (0x0130) // 0x1806_0130 - 0x1806_013F
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/* Packetizer */
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#define BASE_PKT (0x0140) // 0x1806_0140 - 0x1806_014F
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#define BASE_PKT (0x0140) // 0x1806_0140 - 0x1806_014F
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// https://git.psi.ch/sls_detectors_firmware/gotthard_II_mcb/blob/master/code/hdl/pkt/pkt_ctrl.vhd
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/* Flow control and status registers */
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#define BASE_FLOW_CONTROL (0x00200) // 0x1806_0200 - 0x1806_02FF
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#define BASE_FLOW_CONTROL (0x00200) // 0x1806_0200 - 0x1806_02FF
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// https://git.psi.ch/sls_detectors_firmware/vhdl_library/blob/f37608230b4721661f29aacc20124555705ee705/flow/flow_ctrl.vhd
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/* UDP datagram generator */
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#define BASE_UDP_RAM (0x01000) // 0x1806_1000 - 0x1806_1FFF
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#define BASE_UDP_RAM (0x01000) // 0x1806_1000 - 0x1806_1FFF
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/* Clock Generation registers
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* ------------------------------------------------------*/
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#define PLL_RESET_REG (0x00 * REG_OFFSET + BASE_CLK_GENERATION)
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#define PLL_RESET_REG (0x00 * REG_OFFSET + BASE_CLK_GENERATION)
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#define PLL_RESET_READOUT_OFST (0)
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#define PLL_RESET_READOUT_MSK (0x00000001 << PLL_RESET_READOUT_OFST)
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#define PLL_RESET_SYSTEM_OFST (1)
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#define PLL_RESET_SYSTEM_MSK (0x00000001 << PLL_RESET_SYSTEM_OFST)
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#define PLL_RESET_READOUT_OFST (0)
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#define PLL_RESET_READOUT_MSK (0x00000001 << PLL_RESET_READOUT_OFST)
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#define PLL_RESET_SYSTEM_OFST (1)
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#define PLL_RESET_SYSTEM_MSK (0x00000001 << PLL_RESET_SYSTEM_OFST)
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/* Control registers --------------------------------------------------*/
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/* Module Control Board Serial Number register */
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#define MCB_SERIAL_NO_REG (0x00 * REG_OFFSET + BASE_CONTROL)
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#define MCB_SERIAL_NO_REG (0x00 * REG_OFFSET + BASE_CONTROL)
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#define MCB_SERIAL_NO_VRSN_OFST (16)
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#define MCB_SERIAL_NO_VRSN_MSK (0x0000001F << MCB_SERIAL_NO_VRSN_OFST)
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#define MCB_SERIAL_NO_VRSN_OFST (16)
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#define MCB_SERIAL_NO_VRSN_MSK (0x0000001F << MCB_SERIAL_NO_VRSN_OFST)
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/* FPGA Version register */
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#define FPGA_VERSION_REG (0x01 * REG_OFFSET + BASE_CONTROL)
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#define FPGA_VERSION_REG (0x01 * REG_OFFSET + BASE_CONTROL)
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#define FPGA_COMPILATION_DATE_OFST (0)
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#define FPGA_COMPILATION_DATE_MSK (0x00FFFFFF << FPGA_COMPILATION_DATE_OFST)
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#define DETECTOR_TYPE_OFST (24)
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#define DETECTOR_TYPE_MSK (0x000000FF << DETECTOR_TYPE_OFST)
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#define FPGA_COMPILATION_DATE_OFST (0)
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#define FPGA_COMPILATION_DATE_MSK (0x00FFFFFF << FPGA_COMPILATION_DATE_OFST)
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#define DETECTOR_TYPE_OFST (24)
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#define DETECTOR_TYPE_MSK (0x000000FF << DETECTOR_TYPE_OFST)
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/* API Version register */
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#define API_VERSION_REG (0x02 * REG_OFFSET + BASE_CONTROL)
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#define API_VERSION_REG (0x02 * REG_OFFSET + BASE_CONTROL)
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#define API_VERSION_OFST (0)
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#define API_VERSION_MSK (0x00FFFFFF << API_VERSION_OFST)
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#define API_VERSION_DETECTOR_TYPE_OFST (24) // Not used in software
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#define API_VERSION_DETECTOR_TYPE_MSK \
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(0x000000FF << API_VERSION_DETECTOR_TYPE_OFST) // Not used in software
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#define API_VERSION_OFST (0)
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#define API_VERSION_MSK (0x00FFFFFF << API_VERSION_OFST)
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#define API_VERSION_DETECTOR_TYPE_OFST (24) // Not used in software
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#define API_VERSION_DETECTOR_TYPE_MSK (0x000000FF << API_VERSION_DETECTOR_TYPE_OFST) // Not used in software
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/* Fix pattern register */
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#define FIX_PATT_REG (0x03 * REG_OFFSET + BASE_CONTROL)
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#define FIX_PATT_VAL (0xACDC2019)
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#define FIX_PATT_REG (0x03 * REG_OFFSET + BASE_CONTROL)
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#define FIX_PATT_VAL (0xACDC2019)
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/* Status register */
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#define STATUS_REG (0x04 * REG_OFFSET + BASE_CONTROL)
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#define STATUS_REG (0x04 * REG_OFFSET + BASE_CONTROL)
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/* Look at me read only register */
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#define LOOK_AT_ME_REG (0x05 * REG_OFFSET + BASE_CONTROL)
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#define LOOK_AT_ME_REG (0x05 * REG_OFFSET + BASE_CONTROL)
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/* System status register */
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#define SYSTEM_STATUS_REG (0x06 * REG_OFFSET + BASE_CONTROL)
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#define SYSTEM_STATUS_REG (0x06 * REG_OFFSET + BASE_CONTROL)
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/* Config RW regiseter */
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#define CONFIG_REG (0x20 * REG_OFFSET + BASE_CONTROL)
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#define CONFIG_REG (0x20 * REG_OFFSET + BASE_CONTROL)
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#define CONFIG_VETO_ENBL_OFST (0)
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#define CONFIG_VETO_ENBL_MSK (0x00000001 << CONFIG_VETO_ENBL_OFST)
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/* Control RW register */
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#define CONTROL_REG (0x21 * REG_OFFSET + BASE_CONTROL)
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#define CONTROL_REG (0x21 * REG_OFFSET + BASE_CONTROL)
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#define CONTROL_STRT_ACQSTN_OFST (0)
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#define CONTROL_STRT_ACQSTN_MSK (0x00000001 << CONTROL_STRT_ACQSTN_OFST)
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#define CONTROL_STP_ACQSTN_OFST (1)
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#define CONTROL_STP_ACQSTN_MSK (0x00000001 << CONTROL_STP_ACQSTN_OFST)
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#define CONTROL_CRE_RST_OFST (10)
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#define CONTROL_CRE_RST_MSK (0x00000001 << CONTROL_CRE_RST_OFST)
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#define CONTROL_PRPHRL_RST_OFST (11) // Only GBE10?
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#define CONTROL_PRPHRL_RST_MSK (0x00000001 << CONTROL_PRPHRL_RST_OFST)
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#define CONTROL_CLR_ACQSTN_FIFO_OFST (15)
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#define CONTROL_CLR_ACQSTN_FIFO_MSK (0x00000001 << CONTROL_CLR_ACQSTN_FIFO_OFST)
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#define CONTROL_TIMING_SOURCE_EXT_OFST (17)
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#define CONTROL_TIMING_SOURCE_EXT_MSK \
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(0x00000001 << CONTROL_TIMING_SOURCE_EXT_OFST)
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#define CONTROL_PWR_CHIP_OFST (31)
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#define CONTROL_PWR_CHIP_MSK (0x00000001 << CONTROL_PWR_CHIP_OFST)
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#define CONTROL_STRT_ACQSTN_OFST (0)
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#define CONTROL_STRT_ACQSTN_MSK (0x00000001 << CONTROL_STRT_ACQSTN_OFST)
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#define CONTROL_STP_ACQSTN_OFST (1)
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#define CONTROL_STP_ACQSTN_MSK (0x00000001 << CONTROL_STP_ACQSTN_OFST)
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#define CONTROL_CRE_RST_OFST (10)
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#define CONTROL_CRE_RST_MSK (0x00000001 << CONTROL_CRE_RST_OFST)
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#define CONTROL_PRPHRL_RST_OFST (11) // Only GBE10?
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#define CONTROL_PRPHRL_RST_MSK (0x00000001 << CONTROL_PRPHRL_RST_OFST)
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#define CONTROL_CLR_ACQSTN_FIFO_OFST (15)
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#define CONTROL_CLR_ACQSTN_FIFO_MSK (0x00000001 << CONTROL_CLR_ACQSTN_FIFO_OFST)
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#define CONTROL_TIMING_SOURCE_EXT_OFST (17)
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#define CONTROL_TIMING_SOURCE_EXT_MSK (0x00000001 << CONTROL_TIMING_SOURCE_EXT_OFST)
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#define CONTROL_PWR_CHIP_OFST (31)
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#define CONTROL_PWR_CHIP_MSK (0x00000001 << CONTROL_PWR_CHIP_OFST)
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/** DTA Offset Register */
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#define DTA_OFFSET_REG (0x24 * REG_OFFSET + BASE_CONTROL)
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@ -114,143 +116,138 @@
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/* ASIC Config register */
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#define ASIC_CONFIG_REG (0x00 * REG_OFFSET + BASE_ASIC)
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#define ASIC_CONFIG_RUN_MODE_OFST (0)
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#define ASIC_CONFIG_RUN_MODE_MSK (0x00000003 << ASIC_CONFIG_RUN_MODE_OFST)
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#define ASIC_CONFIG_RUN_MODE_INT_BURST_VAL \
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((0x1 << ASIC_CONFIG_RUN_MODE_OFST) & ASIC_CONFIG_RUN_MODE_MSK)
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#define ASIC_CONFIG_RUN_MODE_CONT_VAL \
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((0x2 << ASIC_CONFIG_RUN_MODE_OFST) & ASIC_CONFIG_RUN_MODE_MSK)
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#define ASIC_CONFIG_RUN_MODE_EXT_BURST_VAL \
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((0x3 << ASIC_CONFIG_RUN_MODE_OFST) & ASIC_CONFIG_RUN_MODE_MSK)
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#define ASIC_CONFIG_GAIN_OFST (4)
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#define ASIC_CONFIG_GAIN_MSK (0x00000003 << ASIC_CONFIG_GAIN_OFST)
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#define ASIC_CONFIG_DYNAMIC_GAIN_VAL \
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((0x0 << ASIC_CONFIG_GAIN_OFST) & ASIC_CONFIG_GAIN_MSK)
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#define ASIC_CONFIG_FIX_GAIN_1_VAL \
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((0x1 << ASIC_CONFIG_GAIN_OFST) & ASIC_CONFIG_GAIN_MSK)
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#define ASIC_CONFIG_FIX_GAIN_2_VAL \
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((0x2 << ASIC_CONFIG_GAIN_OFST) & ASIC_CONFIG_GAIN_MSK)
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#define ASIC_CONFIG_RESERVED_VAL \
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((0x3 << ASIC_CONFIG_GAIN_OFST) & ASIC_CONFIG_GAIN_MSK)
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#define ASIC_CONFIG_CURRENT_SRC_EN_OFST (7)
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#define ASIC_CONFIG_CURRENT_SRC_EN_MSK \
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(0x00000001 << ASIC_CONFIG_CURRENT_SRC_EN_OFST)
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#define ASIC_CONFIG_RST_DAC_OFST (15)
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#define ASIC_CONFIG_RST_DAC_MSK (0x00000001 << ASIC_CONFIG_RST_DAC_OFST)
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#define ASIC_CONFIG_DONE_OFST (31)
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#define ASIC_CONFIG_DONE_MSK (0x00000001 << ASIC_CONFIG_DONE_OFST)
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#define ASIC_CONFIG_RUN_MODE_OFST (0)
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#define ASIC_CONFIG_RUN_MODE_MSK (0x00000003 << ASIC_CONFIG_RUN_MODE_OFST)
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#define ASIC_CONFIG_RUN_MODE_INT_BURST_VAL ((0x1 << ASIC_CONFIG_RUN_MODE_OFST) & ASIC_CONFIG_RUN_MODE_MSK)
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#define ASIC_CONFIG_RUN_MODE_CONT_VAL ((0x2 << ASIC_CONFIG_RUN_MODE_OFST) & ASIC_CONFIG_RUN_MODE_MSK)
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#define ASIC_CONFIG_RUN_MODE_EXT_BURST_VAL ((0x3 << ASIC_CONFIG_RUN_MODE_OFST) & ASIC_CONFIG_RUN_MODE_MSK)
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#define ASIC_CONFIG_GAIN_OFST (4)
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#define ASIC_CONFIG_GAIN_MSK (0x00000003 << ASIC_CONFIG_GAIN_OFST)
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#define ASIC_CONFIG_DYNAMIC_GAIN_VAL ((0x0 << ASIC_CONFIG_GAIN_OFST) & ASIC_CONFIG_GAIN_MSK)
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#define ASIC_CONFIG_FIX_GAIN_1_VAL ((0x1 << ASIC_CONFIG_GAIN_OFST) & ASIC_CONFIG_GAIN_MSK)
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#define ASIC_CONFIG_FIX_GAIN_2_VAL ((0x2 << ASIC_CONFIG_GAIN_OFST) & ASIC_CONFIG_GAIN_MSK)
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#define ASIC_CONFIG_RESERVED_VAL ((0x3 << ASIC_CONFIG_GAIN_OFST) & ASIC_CONFIG_GAIN_MSK)
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#define ASIC_CONFIG_CURRENT_SRC_EN_OFST (7)
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#define ASIC_CONFIG_CURRENT_SRC_EN_MSK (0x00000001 << ASIC_CONFIG_CURRENT_SRC_EN_OFST)
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#define ASIC_CONFIG_RST_DAC_OFST (15)
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#define ASIC_CONFIG_RST_DAC_MSK (0x00000001 << ASIC_CONFIG_RST_DAC_OFST)
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#define ASIC_CONFIG_DONE_OFST (31)
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#define ASIC_CONFIG_DONE_MSK (0x00000001 << ASIC_CONFIG_DONE_OFST)
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/* ASIC Internal Frames Register */
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#define ASIC_INT_FRAMES_REG (0x01 * REG_OFFSET + BASE_ASIC)
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#define ASIC_INT_FRAMES_REG (0x01 * REG_OFFSET + BASE_ASIC)
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#define ASIC_INT_FRAMES_OFST (0)
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#define ASIC_INT_FRAMES_MSK (0x00000FFF << ASIC_INT_FRAMES_OFST)
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#define ASIC_INT_FRAMES_OFST (0)
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#define ASIC_INT_FRAMES_MSK (0x00000FFF << ASIC_INT_FRAMES_OFST)
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/* ASIC Period 64bit Register */
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#define ASIC_INT_PERIOD_LSB_REG (0x02 * REG_OFFSET + BASE_ASIC)
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#define ASIC_INT_PERIOD_MSB_REG (0x03 * REG_OFFSET + BASE_ASIC)
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#define ASIC_INT_PERIOD_LSB_REG (0x02 * REG_OFFSET + BASE_ASIC)
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#define ASIC_INT_PERIOD_MSB_REG (0x03 * REG_OFFSET + BASE_ASIC)
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/* ASIC Exptime 64bit Register */
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#define ASIC_INT_EXPTIME_LSB_REG (0x04 * REG_OFFSET + BASE_ASIC)
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#define ASIC_INT_EXPTIME_MSB_REG (0x05 * REG_OFFSET + BASE_ASIC)
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#define ASIC_INT_EXPTIME_LSB_REG (0x04 * REG_OFFSET + BASE_ASIC)
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#define ASIC_INT_EXPTIME_MSB_REG (0x05 * REG_OFFSET + BASE_ASIC)
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/* Packetizer -------------------------------------------------------------*/
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/* Packetizer Config Register */
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#define PKT_CONFIG_REG (0x00 * REG_OFFSET + BASE_PKT)
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#define PKT_CONFIG_REG (0x00 * REG_OFFSET + BASE_PKT)
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#define PKT_CONFIG_NRXR_MAX_OFST (0)
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#define PKT_CONFIG_NRXR_MAX_MSK (0x0000003F << PKT_CONFIG_NRXR_MAX_OFST)
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#define PKT_CONFIG_RXR_START_ID_OFST (8)
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#define PKT_CONFIG_RXR_START_ID_MSK (0x0000003F << PKT_CONFIG_RXR_START_ID_OFST)
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#define PKT_CONFIG_NRXR_MAX_OFST (0)
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#define PKT_CONFIG_NRXR_MAX_MSK (0x0000003F << PKT_CONFIG_NRXR_MAX_OFST)
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#define PKT_CONFIG_RXR_START_ID_OFST (8)
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#define PKT_CONFIG_RXR_START_ID_MSK (0x0000003F << PKT_CONFIG_RXR_START_ID_OFST)
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/* Module Coordinates Register */
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#define COORD_0_REG (0x02 * REG_OFFSET + BASE_PKT)
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#define COORD_ROW_OFST (0)
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#define COORD_ROW_MSK (0x0000FFFF << COORD_ROW_OFST)
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#define COORD_COL_OFST (16)
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#define COORD_COL_MSK (0x0000FFFF << COORD_COL_OFST)
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#define COORD_0_REG (0x02 * REG_OFFSET + BASE_PKT)
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#define COORD_ROW_OFST (0)
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#define COORD_ROW_MSK (0x0000FFFF << COORD_ROW_OFST)
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#define COORD_COL_OFST (16)
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#define COORD_COL_MSK (0x0000FFFF << COORD_COL_OFST)
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/* Module ID Register */
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#define COORD_1_REG (0x03 * REG_OFFSET + BASE_PKT)
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#define COORD_RESERVED_OFST (0)
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#define COORD_RESERVED_MSK (0x0000FFFF << COORD_RESERVED_OFST)
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#define COORD_ID_OFST (16) // Not connected in firmware TODO
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#define COORD_ID_MSK \
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(0x0000FFFF << COORD_ID_OFST) // Not connected in firmware TODO
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#define COORD_1_REG (0x03 * REG_OFFSET + BASE_PKT)
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#define COORD_RESERVED_OFST (0)
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#define COORD_RESERVED_MSK (0x0000FFFF << COORD_RESERVED_OFST)
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#define COORD_ID_OFST (16) // Not connected in firmware TODO
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#define COORD_ID_MSK (0x0000FFFF << COORD_ID_OFST) // Not connected in firmware TODO
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/* Flow control registers --------------------------------------------------*/
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/* Flow status Register*/
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#define FLOW_STATUS_REG (0x00 * REG_OFFSET + BASE_FLOW_CONTROL)
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#define FLOW_STATUS_REG (0x00 * REG_OFFSET + BASE_FLOW_CONTROL)
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#define FLOW_STATUS_RUN_BUSY_OFST (0)
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#define FLOW_STATUS_RUN_BUSY_MSK (0x00000001 << FLOW_STATUS_RUN_BUSY_OFST)
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#define FLOW_STATUS_WAIT_FOR_TRGGR_OFST (3)
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#define FLOW_STATUS_WAIT_FOR_TRGGR_MSK \
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(0x00000001 << FLOW_STATUS_WAIT_FOR_TRGGR_OFST)
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#define FLOW_STATUS_DLY_BFRE_TRGGR_OFST (4)
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#define FLOW_STATUS_DLY_BFRE_TRGGR_MSK \
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(0x00000001 << FLOW_STATUS_DLY_BFRE_TRGGR_OFST)
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#define FLOW_STATUS_FIFO_FULL_OFST (5)
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#define FLOW_STATUS_FIFO_FULL_MSK (0x00000001 << FLOW_STATUS_FIFO_FULL_OFST)
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#define FLOW_STATUS_DLY_AFTR_TRGGR_OFST (15)
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#define FLOW_STATUS_DLY_AFTR_TRGGR_MSK \
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(0x00000001 << FLOW_STATUS_DLY_AFTR_TRGGR_OFST)
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#define FLOW_STATUS_CSM_BUSY_OFST (17)
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#define FLOW_STATUS_CSM_BUSY_MSK (0x00000001 << FLOW_STATUS_CSM_BUSY_OFST)
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#define FLOW_STATUS_RUN_BUSY_OFST (0)
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#define FLOW_STATUS_RUN_BUSY_MSK (0x00000001 << FLOW_STATUS_RUN_BUSY_OFST)
|
||||
#define FLOW_STATUS_WAIT_FOR_TRGGR_OFST (3)
|
||||
#define FLOW_STATUS_WAIT_FOR_TRGGR_MSK (0x00000001 << FLOW_STATUS_WAIT_FOR_TRGGR_OFST)
|
||||
#define FLOW_STATUS_DLY_BFRE_TRGGR_OFST (4)
|
||||
#define FLOW_STATUS_DLY_BFRE_TRGGR_MSK (0x00000001 << FLOW_STATUS_DLY_BFRE_TRGGR_OFST)
|
||||
#define FLOW_STATUS_FIFO_FULL_OFST (5)
|
||||
#define FLOW_STATUS_FIFO_FULL_MSK (0x00000001 << FLOW_STATUS_FIFO_FULL_OFST)
|
||||
#define FLOW_STATUS_DLY_AFTR_TRGGR_OFST (15)
|
||||
#define FLOW_STATUS_DLY_AFTR_TRGGR_MSK (0x00000001 << FLOW_STATUS_DLY_AFTR_TRGGR_OFST)
|
||||
#define FLOW_STATUS_CSM_BUSY_OFST (17)
|
||||
#define FLOW_STATUS_CSM_BUSY_MSK (0x00000001 << FLOW_STATUS_CSM_BUSY_OFST)
|
||||
|
||||
/* Delay left 64bit Register */
|
||||
#define GET_DELAY_LSB_REG (0x02 * REG_OFFSET + BASE_FLOW_CONTROL)
|
||||
#define GET_DELAY_MSB_REG (0x03 * REG_OFFSET + BASE_FLOW_CONTROL)
|
||||
#define GET_DELAY_LSB_REG (0x02 * REG_OFFSET + BASE_FLOW_CONTROL)
|
||||
#define GET_DELAY_MSB_REG (0x03 * REG_OFFSET + BASE_FLOW_CONTROL)
|
||||
|
||||
/* Triggers left 64bit Register */
|
||||
#define GET_CYCLES_LSB_REG (0x04 * REG_OFFSET + BASE_FLOW_CONTROL)
|
||||
#define GET_CYCLES_MSB_REG (0x05 * REG_OFFSET + BASE_FLOW_CONTROL)
|
||||
#define GET_CYCLES_LSB_REG (0x04 * REG_OFFSET + BASE_FLOW_CONTROL)
|
||||
#define GET_CYCLES_MSB_REG (0x05 * REG_OFFSET + BASE_FLOW_CONTROL)
|
||||
|
||||
/* Frames left 64bit Register */
|
||||
#define GET_FRAMES_LSB_REG (0x06 * REG_OFFSET + BASE_FLOW_CONTROL)
|
||||
#define GET_FRAMES_MSB_REG (0x07 * REG_OFFSET + BASE_FLOW_CONTROL)
|
||||
#define GET_FRAMES_LSB_REG (0x06 * REG_OFFSET + BASE_FLOW_CONTROL)
|
||||
#define GET_FRAMES_MSB_REG (0x07 * REG_OFFSET + BASE_FLOW_CONTROL)
|
||||
|
||||
/* Period left 64bit Register */
|
||||
#define GET_PERIOD_LSB_REG (0x08 * REG_OFFSET + BASE_FLOW_CONTROL)
|
||||
#define GET_PERIOD_MSB_REG (0x09 * REG_OFFSET + BASE_FLOW_CONTROL)
|
||||
#define GET_PERIOD_LSB_REG (0x08 * REG_OFFSET + BASE_FLOW_CONTROL)
|
||||
#define GET_PERIOD_MSB_REG (0x09 * REG_OFFSET + BASE_FLOW_CONTROL)
|
||||
|
||||
/* Time from Start 64 bit register */
|
||||
#define TIME_FROM_START_LSB_REG (0x0A * REG_OFFSET + BASE_FLOW_CONTROL)
|
||||
#define TIME_FROM_START_MSB_REG (0x0B * REG_OFFSET + BASE_FLOW_CONTROL)
|
||||
#define TIME_FROM_START_LSB_REG (0x0A * REG_OFFSET + BASE_FLOW_CONTROL)
|
||||
#define TIME_FROM_START_MSB_REG (0x0B * REG_OFFSET + BASE_FLOW_CONTROL)
|
||||
|
||||
/* Get Frames from Start 64 bit register (frames from last reset using
|
||||
* CONTROL_CRST) */
|
||||
#define FRAMES_FROM_START_LSB_REG (0x0C * REG_OFFSET + BASE_FLOW_CONTROL)
|
||||
#define FRAMES_FROM_START_MSB_REG (0x0D * REG_OFFSET + BASE_FLOW_CONTROL)
|
||||
#define FRAMES_FROM_START_LSB_REG (0x0C * REG_OFFSET + BASE_FLOW_CONTROL)
|
||||
#define FRAMES_FROM_START_MSB_REG (0x0D * REG_OFFSET + BASE_FLOW_CONTROL)
|
||||
|
||||
/* Measurement Time 64 bit register (timestamp at a frame start until reset)*/
|
||||
#define START_FRAME_TIME_LSB_REG (0x0E * REG_OFFSET + BASE_FLOW_CONTROL)
|
||||
#define START_FRAME_TIME_MSB_REG (0x0F * REG_OFFSET + BASE_FLOW_CONTROL)
|
||||
#define START_FRAME_TIME_LSB_REG (0x0E * REG_OFFSET + BASE_FLOW_CONTROL)
|
||||
#define START_FRAME_TIME_MSB_REG (0x0F * REG_OFFSET + BASE_FLOW_CONTROL)
|
||||
|
||||
/* Delay 64bit Write-register */
|
||||
#define SET_DELAY_LSB_REG (0x22 * REG_OFFSET + BASE_FLOW_CONTROL)
|
||||
#define SET_DELAY_MSB_REG (0x23 * REG_OFFSET + BASE_FLOW_CONTROL)
|
||||
#define SET_DELAY_LSB_REG (0x22 * REG_OFFSET + BASE_FLOW_CONTROL)
|
||||
#define SET_DELAY_MSB_REG (0x23 * REG_OFFSET + BASE_FLOW_CONTROL)
|
||||
|
||||
/* Cylces (also #bursts) 64bit Write-register */
|
||||
#define SET_CYCLES_LSB_REG (0x24 * REG_OFFSET + BASE_FLOW_CONTROL)
|
||||
#define SET_CYCLES_MSB_REG (0x25 * REG_OFFSET + BASE_FLOW_CONTROL)
|
||||
#define SET_CYCLES_LSB_REG (0x24 * REG_OFFSET + BASE_FLOW_CONTROL)
|
||||
#define SET_CYCLES_MSB_REG (0x25 * REG_OFFSET + BASE_FLOW_CONTROL)
|
||||
|
||||
/* Frames 64bit Write-register */
|
||||
#define SET_FRAMES_LSB_REG (0x26 * REG_OFFSET + BASE_FLOW_CONTROL)
|
||||
#define SET_FRAMES_MSB_REG (0x27 * REG_OFFSET + BASE_FLOW_CONTROL)
|
||||
#define SET_FRAMES_LSB_REG (0x26 * REG_OFFSET + BASE_FLOW_CONTROL)
|
||||
#define SET_FRAMES_MSB_REG (0x27 * REG_OFFSET + BASE_FLOW_CONTROL)
|
||||
|
||||
/* Period (also burst period) 64bit Write-register */
|
||||
#define SET_PERIOD_LSB_REG (0x28 * REG_OFFSET + BASE_FLOW_CONTROL)
|
||||
#define SET_PERIOD_MSB_REG (0x29 * REG_OFFSET + BASE_FLOW_CONTROL)
|
||||
#define SET_PERIOD_LSB_REG (0x28 * REG_OFFSET + BASE_FLOW_CONTROL)
|
||||
#define SET_PERIOD_MSB_REG (0x29 * REG_OFFSET + BASE_FLOW_CONTROL)
|
||||
|
||||
/* External Signal register */
|
||||
#define EXT_SIGNAL_REG (0x30 * REG_OFFSET + BASE_FLOW_CONTROL)
|
||||
#define EXT_SIGNAL_REG (0x30 * REG_OFFSET + BASE_FLOW_CONTROL)
|
||||
|
||||
#define EXT_SIGNAL_OFST (0)
|
||||
#define EXT_SIGNAL_MSK (0x00000001 << EXT_SIGNAL_OFST)
|
||||
#define EXT_SIGNAL_OFST (0)
|
||||
#define EXT_SIGNAL_MSK (0x00000001 << EXT_SIGNAL_OFST)
|
||||
|
||||
/* Trigger Delay 64 bit register */
|
||||
#define SET_TRIGGER_DELAY_LSB_REG (0x32 * REG_OFFSET + BASE_FLOW_CONTROL)
|
||||
#define SET_TRIGGER_DELAY_MSB_REG (0x33 * REG_OFFSET + BASE_FLOW_CONTROL)
|
||||
#define SET_TRIGGER_DELAY_LSB_REG (0x32 * REG_OFFSET + BASE_FLOW_CONTROL)
|
||||
#define SET_TRIGGER_DELAY_MSB_REG (0x33 * REG_OFFSET + BASE_FLOW_CONTROL)
|
||||
|
||||
|
||||
/* UDP datagram registers --------------------------------------------------*/
|
||||
#define RXR_ENDPOINTS_MAX (32)
|
||||
#define RXR_ENDPOINT_OFST (0x10)
|
||||
|
||||
// clang-format on
|
||||
@ -1290,44 +1290,42 @@ enum timingMode getTiming() {
|
||||
return AUTO_TIMING;
|
||||
}
|
||||
|
||||
int configureMAC() {
|
||||
/* configure mac */
|
||||
void setNumberofUDPInterfaces(int val) {
|
||||
uint32_t addr = CONFIG_REG;
|
||||
|
||||
uint32_t srcip = udpDetails.srcip;
|
||||
uint32_t dstip = udpDetails.dstip;
|
||||
uint64_t srcmac = udpDetails.srcmac;
|
||||
uint64_t dstmac = udpDetails.dstmac;
|
||||
int srcport = udpDetails.srcport;
|
||||
int dstport = udpDetails.dstport;
|
||||
|
||||
LOG(logINFOBLUE, ("Configuring MAC\n"));
|
||||
char src_mac[50], src_ip[INET_ADDRSTRLEN], dst_mac[50],
|
||||
dst_ip[INET_ADDRSTRLEN];
|
||||
getMacAddressinString(src_mac, 50, srcmac);
|
||||
getMacAddressinString(dst_mac, 50, dstmac);
|
||||
getIpAddressinString(src_ip, srcip);
|
||||
getIpAddressinString(dst_ip, dstip);
|
||||
|
||||
LOG(logINFO, ("\tSource IP : %s\n"
|
||||
"\tSource MAC : %s\n"
|
||||
"\tSource Port : %d\n"
|
||||
"\tDest IP : %s\n"
|
||||
"\tDest MAC : %s\n"
|
||||
"\tDest Port : %d\n",
|
||||
src_ip, src_mac, srcport, dst_ip, dst_mac, dstport));
|
||||
|
||||
#ifdef VIRTUAL
|
||||
if (setUDPDestinationDetails(0, dst_ip, dstport) == FAIL) {
|
||||
LOG(logERROR, ("could not set udp destination IP and port\n"));
|
||||
return FAIL;
|
||||
// 2 interfaces (enable veto)
|
||||
if (val > 1) {
|
||||
LOG(logINFOBLUE,
|
||||
("Setting #Interfaces: 2 (enabling veto streaming)\n"));
|
||||
bus_w(addr, bus_r(addr) | CONFIG_VETO_ENBL_MSK);
|
||||
}
|
||||
return OK;
|
||||
#endif
|
||||
// 1 interface (disable veto)
|
||||
else {
|
||||
LOG(logINFOBLUE,
|
||||
("Setting #Interfaces: 1 (disabling veto streaming)\n"));
|
||||
bus_w(addr, bus_r(addr) & ~CONFIG_VETO_ENBL_MSK);
|
||||
}
|
||||
LOG(logDEBUG, ("config reg:0x%x\n", bus_r(addr)));
|
||||
}
|
||||
|
||||
int getNumberofUDPInterfaces() {
|
||||
LOG(logDEBUG, ("config reg:0x%x\n", bus_r(CONFIG_REG)));
|
||||
// return 2 if veto enabled, else 1
|
||||
return ((bus_r(CONFIG_REG) & CONFIG_VETO_ENBL_MSK) ? 2 : 1);
|
||||
}
|
||||
|
||||
void setupHeader(int iRxEntry, int vetoInterface, uint32_t destip,
|
||||
uint64_t destmac, uint32_t destport, uint64_t sourcemac,
|
||||
uint32_t sourceip, uint32_t sourceport) {
|
||||
|
||||
// start addr
|
||||
uint32_t addr = BASE_UDP_RAM;
|
||||
// calculate rxr endpoint offset
|
||||
// addr += (iRxEntry * RXR_ENDPOINT_OFST);//TODO: is there round robin
|
||||
// already implemented?
|
||||
if (vetoInterface == 1) {
|
||||
iRxEntry += RXR_ENDPOINTS_MAX;
|
||||
}
|
||||
addr += (iRxEntry * RXR_ENDPOINT_OFST);
|
||||
// get struct memory
|
||||
udp_header *udp =
|
||||
(udp_header *)(Nios_getBaseAddress() + addr / (sizeof(u_int32_t)));
|
||||
@ -1335,21 +1333,21 @@ int configureMAC() {
|
||||
|
||||
// mac addresses
|
||||
// msb (32) + lsb (16)
|
||||
udp->udp_destmac_msb = ((dstmac >> 16) & BIT32_MASK);
|
||||
udp->udp_destmac_lsb = ((dstmac >> 0) & BIT16_MASK);
|
||||
udp->udp_destmac_msb = ((destmac >> 16) & BIT32_MASK);
|
||||
udp->udp_destmac_lsb = ((destmac >> 0) & BIT16_MASK);
|
||||
// msb (16) + lsb (32)
|
||||
udp->udp_srcmac_msb = ((srcmac >> 32) & BIT16_MASK);
|
||||
udp->udp_srcmac_lsb = ((srcmac >> 0) & BIT32_MASK);
|
||||
udp->udp_srcmac_msb = ((sourcemac >> 32) & BIT16_MASK);
|
||||
udp->udp_srcmac_lsb = ((sourcemac >> 0) & BIT32_MASK);
|
||||
|
||||
// ip addresses
|
||||
udp->ip_srcip_msb = ((srcip >> 16) & BIT16_MASK);
|
||||
udp->ip_srcip_lsb = ((srcip >> 0) & BIT16_MASK);
|
||||
udp->ip_destip_msb = ((dstip >> 16) & BIT16_MASK);
|
||||
udp->ip_destip_lsb = ((dstip >> 0) & BIT16_MASK);
|
||||
udp->ip_srcip_msb = ((sourceip >> 16) & BIT16_MASK);
|
||||
udp->ip_srcip_lsb = ((sourceip >> 0) & BIT16_MASK);
|
||||
udp->ip_destip_msb = ((destip >> 16) & BIT16_MASK);
|
||||
udp->ip_destip_lsb = ((destip >> 0) & BIT16_MASK);
|
||||
|
||||
// source port
|
||||
udp->udp_srcport = srcport;
|
||||
udp->udp_destport = dstport;
|
||||
udp->udp_srcport = sourceport;
|
||||
udp->udp_destport = destport;
|
||||
|
||||
// other defines
|
||||
udp->udp_ethertype = 0x800;
|
||||
@ -1361,12 +1359,6 @@ int configureMAC() {
|
||||
// total length is redefined in firmware
|
||||
|
||||
calcChecksum(udp);
|
||||
|
||||
// TODO?
|
||||
cleanFifos();
|
||||
resetCore();
|
||||
// alignDeserializer();
|
||||
return OK;
|
||||
}
|
||||
|
||||
void calcChecksum(udp_header *udp) {
|
||||
@ -1401,6 +1393,88 @@ void calcChecksum(udp_header *udp) {
|
||||
udp->ip_checksum = checksum;
|
||||
}
|
||||
|
||||
int configureMAC() {
|
||||
|
||||
uint32_t srcip = udpDetails.srcip;
|
||||
uint32_t srcip2 = udpDetails.srcip2;
|
||||
uint32_t dstip = udpDetails.dstip;
|
||||
uint32_t dstip2 = udpDetails.dstip2;
|
||||
uint64_t srcmac = udpDetails.srcmac;
|
||||
uint64_t srcmac2 = udpDetails.srcmac2;
|
||||
uint64_t dstmac = udpDetails.dstmac;
|
||||
uint64_t dstmac2 = udpDetails.dstmac2;
|
||||
int srcport = udpDetails.srcport;
|
||||
int srcport2 = udpDetails.srcport2;
|
||||
int dstport = udpDetails.dstport;
|
||||
int dstport2 = udpDetails.dstport2;
|
||||
|
||||
LOG(logINFOBLUE, ("Configuring MAC\n"));
|
||||
char src_mac[50], src_ip[INET_ADDRSTRLEN], dst_mac[50],
|
||||
dst_ip[INET_ADDRSTRLEN];
|
||||
getMacAddressinString(src_mac, 50, srcmac);
|
||||
getMacAddressinString(dst_mac, 50, dstmac);
|
||||
getIpAddressinString(src_ip, srcip);
|
||||
getIpAddressinString(dst_ip, dstip);
|
||||
char src_mac2[50], src_ip2[INET_ADDRSTRLEN], dst_mac2[50],
|
||||
dst_ip2[INET_ADDRSTRLEN];
|
||||
getMacAddressinString(src_mac2, 50, srcmac2);
|
||||
getMacAddressinString(dst_mac2, 50, dstmac2);
|
||||
getIpAddressinString(src_ip2, srcip2);
|
||||
getIpAddressinString(dst_ip2, dstip2);
|
||||
|
||||
int numInterfaces = getNumberofUDPInterfaces();
|
||||
LOG(logINFO, ("\t#Interfaces : %d\n", numInterfaces));
|
||||
|
||||
LOG(logINFO, ("\tData Interface \n"));
|
||||
LOG(logINFO, ("\tSource IP : %s\n"
|
||||
"\tSource MAC : %s\n"
|
||||
"\tSource Port : %d\n"
|
||||
"\tDest IP : %s\n"
|
||||
"\tDest MAC : %s\n"
|
||||
"\tDest Port : %d\n",
|
||||
src_ip, src_mac, srcport, dst_ip, dst_mac, dstport));
|
||||
|
||||
LOG(logINFO, ("\tVeto Interface (%s)\n",
|
||||
(numInterfaces == 2 ? "enabled" : "disabled")));
|
||||
LOG(logINFO, ("\tSource IP2 : %s\n"
|
||||
"\tSource MAC2 : %s\n"
|
||||
"\tSource Port2: %d\n"
|
||||
"\tDest IP2 : %s\n"
|
||||
"\tDest MAC2 : %s\n"
|
||||
"\tDest Port2 : %d\n",
|
||||
src_ip2, src_mac2, srcport2, dst_ip2, dst_mac2, dstport2));
|
||||
|
||||
#ifdef VIRTUAL
|
||||
if (setUDPDestinationDetails(0, dst_ip, dstport) == FAIL) {
|
||||
LOG(logERROR, ("could not set udp destination IP and port\n"));
|
||||
return FAIL;
|
||||
}
|
||||
if (numInterfaces == 2 &&
|
||||
setUDPDestinationDetails(1, dst_ip2, dstport2) == FAIL) {
|
||||
LOG(logERROR,
|
||||
("could not set udp destination IP and port for interface 2\n"));
|
||||
return FAIL;
|
||||
}
|
||||
return OK;
|
||||
#endif
|
||||
// default one rxr entry (others not yet implemented in client yet)
|
||||
int iRxEntry = 0;
|
||||
|
||||
// data
|
||||
setupHeader(iRxEntry, 0, dstip, dstmac, dstport, srcmac, srcip, srcport);
|
||||
|
||||
// veto
|
||||
if (numInterfaces == 2) {
|
||||
setupHeader(iRxEntry, 1, dstip2, dstmac2, dstport2, srcmac2, srcip2,
|
||||
srcport2);
|
||||
}
|
||||
|
||||
cleanFifos();
|
||||
resetCore();
|
||||
// alignDeserializer();
|
||||
return OK;
|
||||
}
|
||||
|
||||
int setDetectorPosition(int pos[]) {
|
||||
memcpy(detPos, pos, sizeof(detPos));
|
||||
|
||||
@ -2142,6 +2216,9 @@ int startStateMachine() {
|
||||
if (createUDPSocket(0) != OK) {
|
||||
return FAIL;
|
||||
}
|
||||
if (getNumberofUDPInterfaces() == 2 && createUDPSocket(1) != OK) {
|
||||
return FAIL;
|
||||
}
|
||||
LOG(logINFOBLUE, ("Starting State Machine\n"));
|
||||
// set status to running
|
||||
virtual_status = 1;
|
||||
@ -2181,6 +2258,7 @@ void *start_timer(void *arg) {
|
||||
return NULL;
|
||||
}
|
||||
|
||||
int numInterfaces = getNumberofUDPInterfaces();
|
||||
int numRepeats = getNumTriggers();
|
||||
if (getTiming() == AUTO_TIMING) {
|
||||
if (burstMode == BURST_OFF) {
|
||||
@ -2196,6 +2274,8 @@ void *start_timer(void *arg) {
|
||||
int imagesize = NCHAN * NCHIP * 2;
|
||||
int datasize = imagesize;
|
||||
int packetsize = datasize + sizeof(sls_detector_header);
|
||||
int vetodatasize = VETO_DATA_SIZE;
|
||||
int vetopacketsize = vetodatasize + sizeof(sls_detector_header);
|
||||
|
||||
// Generate data
|
||||
char imageData[imagesize];
|
||||
@ -2203,6 +2283,11 @@ void *start_timer(void *arg) {
|
||||
for (int i = 0; i < imagesize; i += sizeof(uint16_t)) {
|
||||
*((uint16_t *)(imageData + i)) = i;
|
||||
}
|
||||
char vetoData[vetodatasize];
|
||||
memset(vetoData, 0, sizeof(vetodatasize));
|
||||
for (int i = 0; i < vetodatasize; i += sizeof(uint8_t)) {
|
||||
*((uint16_t *)(vetoData + i)) = i;
|
||||
}
|
||||
|
||||
{
|
||||
int frameHeaderNr = 0;
|
||||
@ -2227,6 +2312,7 @@ void *start_timer(void *arg) {
|
||||
clock_gettime(CLOCK_REALTIME, &begin);
|
||||
usleep(expUs);
|
||||
|
||||
// first interface
|
||||
char packetData[packetsize];
|
||||
memset(packetData, 0, packetsize);
|
||||
// set header
|
||||
@ -2235,19 +2321,38 @@ void *start_timer(void *arg) {
|
||||
header->detType = (uint16_t)myDetectorType;
|
||||
header->version = SLS_DETECTOR_HEADER_VERSION - 1;
|
||||
header->frameNumber = frameHeaderNr;
|
||||
++frameHeaderNr;
|
||||
header->packetNumber = 0;
|
||||
header->modId = 0;
|
||||
header->row = detPos[X];
|
||||
header->column = detPos[Y];
|
||||
|
||||
// fill data
|
||||
memcpy(packetData + sizeof(sls_detector_header), imageData,
|
||||
datasize);
|
||||
|
||||
// send 1 packet = 1 frame
|
||||
sendUDPPacket(0, packetData, packetsize);
|
||||
|
||||
// second interface (veto)
|
||||
char packetData2[packetsize];
|
||||
memset(packetData2, 0, packetsize);
|
||||
if (numInterfaces == 2) {
|
||||
// set header
|
||||
sls_detector_header *header =
|
||||
(sls_detector_header *)(packetData2);
|
||||
header->detType = (uint16_t)myDetectorType;
|
||||
header->version = SLS_DETECTOR_HEADER_VERSION - 1;
|
||||
header->frameNumber = frameHeaderNr;
|
||||
header->packetNumber = 0;
|
||||
header->modId = 0;
|
||||
header->row = detPos[X];
|
||||
header->column = detPos[Y];
|
||||
// fill data
|
||||
memcpy(packetData2 + sizeof(sls_detector_header), vetoData,
|
||||
vetodatasize);
|
||||
// send 1 packet = 1 frame
|
||||
sendUDPPacket(1, packetData2, vetopacketsize);
|
||||
}
|
||||
++frameHeaderNr;
|
||||
|
||||
clock_gettime(CLOCK_REALTIME, &end);
|
||||
LOG(logINFO,
|
||||
("Sent frame: %d (bursts: %d)\n", frameNr, repeatNr));
|
||||
@ -2275,6 +2380,9 @@ void *start_timer(void *arg) {
|
||||
}
|
||||
|
||||
closeUDPSocket(0);
|
||||
if (numInterfaces == 2) {
|
||||
closeUDPSocket(1);
|
||||
}
|
||||
|
||||
virtual_status = 0;
|
||||
if (isControlServer) {
|
||||
|
||||
@ -52,12 +52,11 @@
|
||||
#define DEFAULT_SYSTEM_C3 (5) //(144444448) // str_clk, 144 MHz
|
||||
|
||||
/* Firmware Definitions */
|
||||
#define IP_HEADER_SIZE (20)
|
||||
#define FIXED_PLL_FREQUENCY (20000000) // 20MHz
|
||||
#define INT_SYSTEM_C0_FREQUENCY (144000000) // 144 MHz
|
||||
#define READOUT_PLL_VCO_FREQ_HZ (866666688) // 866 MHz
|
||||
#define SYSTEM_PLL_VCO_FREQ_HZ (722222224) // 722 MHz
|
||||
|
||||
#define VETO_DATA_SIZE (160)
|
||||
/** Other Definitions */
|
||||
#define BIT16_MASK (0xFFFF)
|
||||
|
||||
@ -156,4 +155,5 @@ typedef struct udp_header_struct {
|
||||
uint16_t udp_checksum;
|
||||
uint16_t udp_destport;
|
||||
} udp_header;
|
||||
#define IP_HEADER_SIZE (20)
|
||||
#define UDP_IP_HEADER_LENGTH_BYTES (28)
|
||||
Reference in New Issue
Block a user