mirror of
https://github.com/slsdetectorgroup/slsDetectorPackage.git
synced 2025-06-13 05:17:13 +02:00
@ -67,9 +67,6 @@ exposed to Python through pybind11.
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.. autoclass:: readoutMode
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:undoc-members:
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.. autoclass:: masterFlags
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:undoc-members:
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.. autoclass:: burstMode
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:undoc-members:
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@ -219,7 +219,7 @@ The enums can be found in slsdet.enums
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>>> [e for e in dir(slsdet.enums) if not e.startswith('_')]
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['burstMode', 'clockIndex', 'dacIndex',
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'detectorSettings', 'detectorType', 'dimension', 'externalSignalFlag',
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'fileFormat', 'frameDiscardPolicy', 'masterFlags',
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'fileFormat', 'frameDiscardPolicy',
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'readoutMode', 'runStatus', 'speedLevel', 'timingMode',
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'timingSourceType']
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@ -12,7 +12,6 @@ dacIndex = _slsdet.slsDetectorDefs.dacIndex
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detectorSettings = _slsdet.slsDetectorDefs.detectorSettings
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clockIndex = _slsdet.slsDetectorDefs.clockIndex
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readoutMode = _slsdet.slsDetectorDefs.readoutMode
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masterFlags = _slsdet.slsDetectorDefs.masterFlags
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burstMode = _slsdet.slsDetectorDefs.burstMode
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timingSourceType = _slsdet.slsDetectorDefs.timingSourceType
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M3_GainCaps = _slsdet.slsDetectorDefs.M3_GainCaps
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@ -255,12 +255,6 @@ void init_enums(py::module &m) {
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.value("QUARTER_SPEED", slsDetectorDefs::speedLevel::QUARTER_SPEED)
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.export_values();
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py::enum_<slsDetectorDefs::masterFlags>(Defs, "masterFlags")
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.value("NO_MASTER", slsDetectorDefs::masterFlags::NO_MASTER)
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.value("IS_MASTER", slsDetectorDefs::masterFlags::IS_MASTER)
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.value("IS_SLAVE", slsDetectorDefs::masterFlags::IS_SLAVE)
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.export_values();
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py::enum_<slsDetectorDefs::burstMode>(Defs, "burstMode")
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.value("BURST_INTERNAL", slsDetectorDefs::burstMode::BURST_INTERNAL)
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.value("BURST_EXTERNAL", slsDetectorDefs::burstMode::BURST_EXTERNAL)
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Binary file not shown.
@ -251,12 +251,12 @@ int Beb_IsTransmitting(int *retval, int tengiga, int waitForDelay) {
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int maxtimer = (MAX(MAX(l_txndelaycounter, l_framedelaycounter),
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MAX(r_txndelaycounter, r_framedelaycounter))) /
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100; // counter values in 10 ns
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printf("Will wait for %d us\n", maxtimer);
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printf("Beb: Will wait for %d us\n", maxtimer);
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usleep(maxtimer);
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}
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// wait for 1 ms
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else {
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printf("Will wait for 1 ms\n");
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printf("Beb: Will wait for 1 ms\n");
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usleep(1 * 1000);
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}
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@ -1109,7 +1109,7 @@ int Beb_StopAcquisition() {
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// open file pointer
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int fd = Beb_open(&csp0base, XPAR_CMD_GENERATOR);
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if (fd < 0) {
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LOG(logERROR, ("Beb Stop Acquisition FAIL\n"));
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LOG(logERROR, ("Beb Reset FAIL\n"));
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return 0;
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} else {
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// find value
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@ -1126,7 +1126,7 @@ int Beb_StopAcquisition() {
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Beb_Write32(csp0base, (RIGHT_OFFSET + STOP_ACQ_OFFSET),
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(valuer & (~STOP_ACQ_BIT)));
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LOG(logINFO, ("Beb Stop Acquisition OK\n"));
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LOG(logINFO, ("Beb: Reset done\n"));
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// close file pointer
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Beb_close(fd, csp0base);
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}
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@ -709,6 +709,32 @@ int Feb_Control_AcquisitionInProgress() {
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return STATUS_IDLE;
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}
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int Feb_Control_ProcessingInProgress() {
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unsigned int regr = 0, regl = 0;
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// deactivated should return end of processing
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if (!Feb_Control_activated)
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return IDLE;
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if (!Feb_Interface_ReadRegister(Feb_Control_rightAddress, FEB_REG_STATUS,
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®r)) {
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LOG(logERROR, ("Could not read right FEB_REG_STATUS to get feb "
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"processing status\n"));
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return STATUS_ERROR;
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}
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if (!Feb_Interface_ReadRegister(Feb_Control_leftAddress, FEB_REG_STATUS,
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®l)) {
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LOG(logERROR, ("Could not read left FEB_REG_STATUS to get feb "
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"processing status\n"));
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return STATUS_ERROR;
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}
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// processing done
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if ((regr | regl) & FEB_REG_STATUS_ACQ_DONE_MSK) {
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return STATUS_IDLE;
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}
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// processing running
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return STATUS_RUNNING;
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}
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int Feb_Control_AcquisitionStartedBit() {
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unsigned int status_reg_r = 0, status_reg_l = 0;
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// deactivated should return acquisition started/ready
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@ -817,7 +843,7 @@ int Feb_Control_StartDAQOnlyNWaitForFinish(int sleep_time_us) {
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}
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int Feb_Control_Reset() {
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LOG(logINFO, ("Reset daq\n"));
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LOG(logINFO, ("Feb: Reset daq\n"));
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if (Feb_Control_activated) {
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if (!Feb_Interface_WriteRegister(Feb_Control_AddressToAll(),
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DAQ_REG_CTRL, 0, 0, 0) ||
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@ -996,7 +1022,48 @@ int Feb_Control_StartAcquisition() {
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return 1;
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}
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int Feb_Control_StopAcquisition() { return Feb_Control_Reset(); }
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int Feb_Control_StopAcquisition() {
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if (Feb_Control_activated) {
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// sends last frames from fifo
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unsigned int orig_value = 0;
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if (!Feb_Interface_ReadRegister(Feb_Control_AddressToAll(),
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DAQ_REG_CTRL, &orig_value)) {
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LOG(logERROR, ("Could not read DAQ_REG_CTRL to stop acquisition "
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"(send complete frames)\n"));
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return 0;
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}
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if (!Feb_Interface_WriteRegister(Feb_Control_AddressToAll(),
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DAQ_REG_CTRL,
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orig_value | DAQ_CTRL_STOP, 0, 0)) {
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LOG(logERROR, ("Could not send last frames.\n"));
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return 0;
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}
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LOG(logINFO, ("Feb: Command to Flush out images from fifo\n"));
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// wait for feb processing to be done
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int is_processing = Feb_Control_ProcessingInProgress();
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int check_error = 0;
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while (is_processing != STATUS_IDLE) {
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usleep(500);
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is_processing = Feb_Control_ProcessingInProgress();
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// check error only 5 times (ensuring it is not something that
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// happens sometimes)
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if (is_processing == STATUS_ERROR) {
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if (check_error == 5)
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break;
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check_error++;
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} // reset check_error for next time
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else
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check_error = 0;
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}
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LOG(logINFO, ("Feb: Processing done (to stop acq)\n"));
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return 0;
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}
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return 1;
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}
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int Feb_Control_IsReadyForTrigger(int *readyForTrigger) {
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unsigned int addr[2] = {Feb_Control_leftAddress, Feb_Control_rightAddress};
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@ -40,6 +40,7 @@ unsigned int *Feb_Control_GetTrimbits();
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// acquisition
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int Feb_Control_AcquisitionInProgress();
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int Feb_Control_ProcessingInProgress();
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int Feb_Control_AcquisitionStartedBit();
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int Feb_Control_WaitForStartedFlag(int sleep_time_us, int prev_flag);
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int Feb_Control_WaitForFinishedFlag(int sleep_time_us, int tempLock);
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@ -30,10 +30,13 @@
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#define DAQ_REG_RO_OFFSET 20
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#define DAQ_REG_STATUS (DAQ_REG_RO_OFFSET + 0) // also pg and fifo status register
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#define FEB_REG_STATUS (DAQ_REG_RO_OFFSET + 3)
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#define FEB_REG_STATUS_WAIT_FOR_TRGGR_OFST (5)
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#define FEB_REG_STATUS_WAIT_FOR_TRGGR_MSK (0x00000001 << FEB_REG_STATUS_WAIT_FOR_TRGGR_OFST)
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#define FEB_REG_STATUS_ACQ_DONE_OFST (6)
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#define FEB_REG_STATUS_ACQ_DONE_MSK (0x00000001 << FEB_REG_STATUS_ACQ_DONE_OFST)
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#define FEB_REG_STATUS_TEMP_OFST (16)
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#define FEB_REG_STATUS_TEMP_MSK (0x0000FFFF << FEB_REG_STATUS_TEMP_OFST)
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@ -44,7 +47,8 @@
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#define DAQ_CTRL_RESET 0x80000000
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#define DAQ_CTRL_START 0x40000000
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#define ACQ_CTRL_START 0x50000000 // this is 0x10000000 (acq) | 0x40000000 (daq)
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#define DAQ_CTRL_STOP 0x00000000
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#define DAQ_CTRL_STOP 0x08000000 // sends last complete frame
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#define DAQ_CTRL_DONE 0x00000040 // data processing done in feb
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// direct chip commands to the DAQ_REG_CHIP_CMDS register
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#define DAQ_SET_STATIC_BIT 0x00000001
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Binary file not shown.
@ -46,7 +46,6 @@ int on_dst = 0;
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int dst_requested[32] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
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enum masterFlags masterMode = IS_SLAVE;
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int top = 0;
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int master = 0;
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int normal = 0;
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@ -1413,6 +1412,8 @@ int setHighVoltage(int val) {
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/* parameters - timing, extsig */
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int isMaster() { return master; }
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void setTiming(enum timingMode arg) {
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int ret = 0;
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switch (arg) {
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@ -2387,19 +2388,43 @@ int stopStateMachine() {
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return OK;
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#else
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sharedMemory_lockLocalLink();
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if ((Feb_Control_StopAcquisition() != STATUS_IDLE) ||
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(!Beb_StopAcquisition())) {
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// sends last frames from fifo and wait for feb processing done
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if ((Feb_Control_StopAcquisition() != STATUS_IDLE)) {
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LOG(logERROR, ("failed to stop acquisition\n"));
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sharedMemory_unlockLocalLink();
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return FAIL;
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}
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sharedMemory_unlockLocalLink();
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// wait for beb to finish sending packets
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int isTransmitting = 1;
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while (isTransmitting) {
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// wait for beb to send out all packets
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if (Beb_IsTransmitting(&isTransmitting, send_to_ten_gig, 1) == FAIL) {
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LOG(logERROR, ("failed to stop beb acquisition\n"));
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return FAIL;
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}
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if (isTransmitting) {
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printf("Transmitting...\n");
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}
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}
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LOG(logINFO, ("Beb: Detector has sent all data (stop)\n"));
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// reset feb and beb
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sharedMemory_lockLocalLink();
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Feb_Control_Reset();
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sharedMemory_unlockLocalLink();
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if (!Beb_StopAcquisition()) {
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LOG(logERROR, ("failed to stop acquisition\n"));
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return FAIL;
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}
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// ensure all have same starting frame numbers
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uint64_t retval = 0;
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if (Beb_GetNextFrameNumber(&retval, send_to_ten_gig) == -2) {
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Beb_SetNextFrameNumber(retval + 1);
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}
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LOG(logINFOBLUE, ("Stopping state machine complete\n\n"));
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return OK;
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#endif
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}
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@ -2510,6 +2535,21 @@ void readFrame(int *ret, char *mess) {
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// wait for detector to send
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int isTransmitting = 1;
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while (isTransmitting) {
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// wait for feb processing to be done
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sharedMemory_lockLocalLink();
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int i = Feb_Control_ProcessingInProgress();
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sharedMemory_unlockLocalLink();
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if (i == STATUS_ERROR) {
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strcpy(mess, "Could not read feb processing done register\n");
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*ret = (int)FAIL;
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return;
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}
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if (i == RUNNING) {
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LOG(logINFOBLUE, ("Status: TRANSMITTING (feb processing)\n"));
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isTransmitting = 1;
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}
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// wait for beb to send out all packets
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if (Beb_IsTransmitting(&isTransmitting, send_to_ten_gig, 1) == FAIL) {
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strcpy(mess, "Could not read delay counters\n");
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*ret = (int)FAIL;
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@ -2519,7 +2559,7 @@ void readFrame(int *ret, char *mess) {
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printf("Transmitting...\n");
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}
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}
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LOG(logINFO, ("Detector has sent all data\n"));
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LOG(logINFO, ("Beb: Detector has sent all data (acquire)\n"));
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LOG(logINFOGREEN, ("Acquisition successfully finished\n"));
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#endif
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}
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|
Binary file not shown.
Binary file not shown.
@ -55,7 +55,7 @@ int ipPacketSize = 0;
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int udpPacketSize = 0;
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||||
|
||||
// master slave configuration (for 25um)
|
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int masterflags = NO_MASTER;
|
||||
int master = 0;
|
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int masterdefaultdelay = 62;
|
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int patternphase = 0;
|
||||
int adcphase = 0;
|
||||
@ -364,6 +364,8 @@ void initStopServer() {
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||||
#ifdef VIRTUAL
|
||||
sharedMemory_setStop(0);
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||||
#endif
|
||||
// to get master from file
|
||||
readConfigFile();
|
||||
}
|
||||
|
||||
/* set up detector */
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||||
@ -621,14 +623,12 @@ int readConfigFile() {
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||||
// key is master/ slave flag
|
||||
if (!strcasecmp(key, "masterflags")) {
|
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if (!strcasecmp(value, "is_master")) {
|
||||
masterflags = IS_MASTER;
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master = 1;
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LOG(logINFOBLUE, ("\tMaster\n"));
|
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} else if (!strcasecmp(value, "is_slave")) {
|
||||
masterflags = IS_SLAVE;
|
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LOG(logINFOBLUE, ("\tSlave\n"));
|
||||
} else if (!strcasecmp(value, "no_master")) {
|
||||
masterflags = NO_MASTER;
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LOG(logINFOBLUE, ("\tNo Master\n"));
|
||||
} else if ((!strcasecmp(value, "is_slave")) ||
|
||||
(!strcasecmp(value, "no_master"))) {
|
||||
master = 0;
|
||||
LOG(logINFOBLUE, ("\tSlave or No Master\n"));
|
||||
} else {
|
||||
LOG(logERROR,
|
||||
("\tCould not scan masterflags %s value from config file\n",
|
||||
@ -705,7 +705,7 @@ void setMasterSlaveConfiguration() {
|
||||
return;
|
||||
|
||||
// master configuration
|
||||
if (masterflags == IS_MASTER) {
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if (master) {
|
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// master default delay set, so reset delay
|
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setDelayAfterTrigger(0);
|
||||
|
||||
@ -876,7 +876,7 @@ int setDelayAfterTrigger(int64_t val) {
|
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return FAIL;
|
||||
}
|
||||
LOG(logINFO, ("Setting delay after trigger %lld ns\n", (long long int)val));
|
||||
if (masterflags == IS_MASTER) {
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||||
if (master) {
|
||||
val += masterdefaultdelay;
|
||||
LOG(logINFO, ("\tActual Delay (master): %lld\n", (long long int)val));
|
||||
}
|
||||
@ -900,7 +900,7 @@ int setDelayAfterTrigger(int64_t val) {
|
||||
int64_t getDelayAfterTrigger() {
|
||||
int64_t retval =
|
||||
get64BitReg(SET_DELAY_LSB_REG, SET_DELAY_MSB_REG) / (1E-9 * CLK_FREQ);
|
||||
if (masterflags == IS_MASTER) {
|
||||
if (master) {
|
||||
LOG(logDEBUG1,
|
||||
("\tActual Delay read (master): %lld\n", (long long int)retval));
|
||||
retval -= masterdefaultdelay;
|
||||
@ -924,7 +924,7 @@ int64_t getPeriodLeft() {
|
||||
int64_t getDelayAfterTriggerLeft() {
|
||||
int64_t retval =
|
||||
get64BitReg(GET_DELAY_LSB_REG, GET_DELAY_MSB_REG) / (1E-9 * CLK_FREQ);
|
||||
if (masterflags == IS_MASTER) {
|
||||
if (master) {
|
||||
LOG(logDEBUG1,
|
||||
("\tGetting Actual delay (master): %lld\n", (long long int)retval));
|
||||
retval -= masterdefaultdelay;
|
||||
@ -1201,6 +1201,8 @@ int setHighVoltage(int val) {
|
||||
|
||||
/* parameters - timing, extsig */
|
||||
|
||||
int isMaster() { return master; }
|
||||
|
||||
void setTiming(enum timingMode arg) {
|
||||
u_int32_t addr = EXT_SIGNAL_REG;
|
||||
switch (arg) {
|
||||
@ -1451,7 +1453,7 @@ int configureMAC() {
|
||||
setExpTime(900 * 1000);
|
||||
|
||||
// take an image
|
||||
if (masterflags == IS_MASTER)
|
||||
if (master)
|
||||
usleep(1 * 1000 * 1000); // required to ensure master starts
|
||||
// acquisition only after slave has changed
|
||||
// to basic parameters and is waiting
|
||||
|
Binary file not shown.
Binary file not shown.
Binary file not shown.
@ -1395,12 +1395,13 @@ int setHighVoltage(int val) {
|
||||
return highvoltage;
|
||||
}
|
||||
|
||||
/* parameters - timing */
|
||||
|
||||
int isMaster() {
|
||||
return !((bus_r(SYSTEM_STATUS_REG) & SYSTEM_STATUS_SLV_BRD_DTCT_MSK) >>
|
||||
SYSTEM_STATUS_SLV_BRD_DTCT_OFST);
|
||||
}
|
||||
|
||||
/* parameters - timing */
|
||||
void setTiming(enum timingMode arg) {
|
||||
|
||||
if (!isMaster() && arg == AUTO_TIMING)
|
||||
|
@ -347,6 +347,9 @@ int getADC(enum ADCINDEX ind);
|
||||
int setHighVoltage(int val);
|
||||
|
||||
// parameters - timing, extsig
|
||||
#if defined(MYTHEN3D) || defined(EIGERD) || defined(GOTTHARDD)
|
||||
int isMaster();
|
||||
#endif
|
||||
#ifdef GOTTHARD2D
|
||||
void updatingRegisters();
|
||||
#endif
|
||||
@ -354,7 +357,6 @@ void setTiming(enum timingMode arg);
|
||||
enum timingMode getTiming();
|
||||
#ifdef MYTHEN3D
|
||||
void setInitialExtSignals();
|
||||
int isMaster();
|
||||
int setGainCaps(int caps);
|
||||
int getGainCaps();
|
||||
int setChipStatusRegister(int csr);
|
||||
|
@ -8156,7 +8156,7 @@ int get_master(int file_des) {
|
||||
|
||||
LOG(logDEBUG1, ("Getting master\n"));
|
||||
|
||||
#ifndef MYTHEN3D
|
||||
#if !defined(MYTHEN3D) && !defined(EIGERD) && !defined(GOTTHARDD)
|
||||
functionNotImplemented();
|
||||
#else
|
||||
retval = isMaster();
|
||||
|
@ -488,12 +488,14 @@ class Detector {
|
||||
void stopReceiver();
|
||||
|
||||
/** Non blocking: start detector acquisition. Status changes to RUNNING or
|
||||
* WAITING and automatically returns to idle at the end of acquisition. */
|
||||
* WAITING and automatically returns to idle at the end of acquisition.
|
||||
[Mythen3] Master starts acquisition first */
|
||||
void startDetector();
|
||||
|
||||
/** [Mythen3] Non blocking: start detector readout of counters in chip.
|
||||
* Status changes to TRANSMITTING and automatically returns to idle at the
|
||||
* end of readout. */
|
||||
* end of readout.
|
||||
[Eiger] Master stops acquisition last */
|
||||
void startDetectorReadout();
|
||||
|
||||
/** Non blocking: Abort detector acquisition. Status changes to IDLE or
|
||||
@ -1310,6 +1312,7 @@ class Detector {
|
||||
* (internal gating). Gate index: 0-2, -1 for all */
|
||||
Result<std::array<ns, 3>> getGateDelayForAllGates(Positions pos = {}) const;
|
||||
|
||||
/** [Eiger][Mythen3][Gotthard1] via stop server **/
|
||||
Result<bool> getMaster(Positions pos = {}) const;
|
||||
|
||||
// TODO! check if we really want to expose this !!!!!
|
||||
|
@ -677,16 +677,16 @@ void Detector::startDetector() {
|
||||
auto detector_type = getDetectorType().squash();
|
||||
if (detector_type == defs::MYTHEN3 && size() > 1) {
|
||||
auto is_master = getMaster();
|
||||
std::vector<int> master;
|
||||
int masterPosition = 0;
|
||||
std::vector<int> slaves;
|
||||
for (int i = 0; i < size(); ++i) {
|
||||
if (is_master[i])
|
||||
master.push_back(i);
|
||||
masterPosition = i;
|
||||
else
|
||||
slaves.push_back(i);
|
||||
}
|
||||
pimpl->Parallel(&Module::startAcquisition, slaves);
|
||||
pimpl->Parallel(&Module::startAcquisition, master);
|
||||
pimpl->Parallel(&Module::startAcquisition, {masterPosition});
|
||||
} else {
|
||||
pimpl->Parallel(&Module::startAcquisition, {});
|
||||
}
|
||||
|
@ -1999,7 +1999,7 @@ std::array<time::ns, 3> Module::getGateDelayForAllGates() const {
|
||||
return sendToDetector<std::array<time::ns, 3>>(F_GET_GATE_DELAY_ALL_GATES);
|
||||
}
|
||||
|
||||
bool Module::isMaster() const { return sendToDetector<int>(F_GET_MASTER); }
|
||||
bool Module::isMaster() const { return sendToDetectorStop<int>(F_GET_MASTER); }
|
||||
|
||||
int Module::getChipStatusRegister() const {
|
||||
return sendToDetector<int>(F_GET_CSR);
|
||||
|
@ -375,9 +375,6 @@ typedef struct {
|
||||
/** chip speed */
|
||||
enum speedLevel { FULL_SPEED, HALF_SPEED, QUARTER_SPEED };
|
||||
|
||||
/** hierarchy in multi-detector structure, if any */
|
||||
enum masterFlags { NO_MASTER, IS_MASTER, IS_SLAVE };
|
||||
|
||||
/**
|
||||
* burst mode for gotthard2
|
||||
*/
|
||||
@ -394,14 +391,14 @@ typedef struct {
|
||||
*/
|
||||
enum timingSourceType { TIMING_INTERNAL, TIMING_EXTERNAL };
|
||||
|
||||
//gain caps Mythen3
|
||||
// gain caps Mythen3
|
||||
enum M3_GainCaps {
|
||||
M3_C10pre= 1<<7,
|
||||
M3_C15sh = 1<<10,
|
||||
M3_C30sh = 1<<11,
|
||||
M3_C50sh = 1<<12,
|
||||
M3_C225ACsh = 1<<13,
|
||||
M3_C15pre = 1<<14,
|
||||
M3_C10pre = 1 << 7,
|
||||
M3_C15sh = 1 << 10,
|
||||
M3_C30sh = 1 << 11,
|
||||
M3_C50sh = 1 << 12,
|
||||
M3_C225ACsh = 1 << 13,
|
||||
M3_C15pre = 1 << 14,
|
||||
};
|
||||
|
||||
#ifdef __cplusplus
|
||||
@ -636,9 +633,6 @@ typedef struct {
|
||||
|
||||
#ifdef __cplusplus
|
||||
|
||||
|
||||
|
||||
|
||||
// TODO! discuss this
|
||||
#include <vector> //hmm... but currently no way around
|
||||
namespace sls {
|
||||
|
@ -9,4 +9,5 @@
|
||||
#define APIJUNGFRAU 0x210621
|
||||
#define APIMYTHEN3 0x210621
|
||||
#define APIMOENCH 0x210621
|
||||
#define APIEIGER 0x210625
|
||||
|
||||
#define APIEIGER 0x210701
|
||||
|
Reference in New Issue
Block a user