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https://github.com/slsdetectorgroup/slsDetectorPackage.git
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@ -2,11 +2,10 @@
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// Copyright (C) 2021 Contributors to the SLS Detector Package
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#pragma once
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#define CTRL_REG (0x8000)
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#define POWER_VIO_OFST (0)
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#define POWER_VIO_MSK (0x00000001 << POWER_VIO_OFST)
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#define POWER_VIO_OFST (0)
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#define POWER_VIO_MSK (0x00000001 << POWER_VIO_OFST)
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#define POWER_VCC_A_OFST (1)
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#define POWER_VCC_A_MSK (0x00000001 << POWER_VCC_A_OFST)
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#define POWER_VCC_B_OFST (2)
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@ -18,20 +17,20 @@
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#define STATUS_REG (0x8004)
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#define PATTERN_RUNNING_OFST (0)
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#define PATTERN_RUNNING_MSK (0x00000001 << PATTERN_RUNNING_OFST)
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#define RX_BUSY_OFST (1)
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#define RX_BUSY_MSK (0x00000001 << RX_BUSY_OFST)
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#define PROCESSING_BUSY_OFST (2)
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#define PROCESSING_BUSY_MSK (0x00000001 << PROCESSING_BUSY_OFST)
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#define UDP_GEN_BUSY_OFST (3)
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#define UDP_GEN_BUSY_MSK (0x00000001 << UDP_GEN_BUSY_OFST)
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#define NETWORK_BUSY_OFST (4)
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#define NETWORK_BUSY_MSK (0x00000001 << NETWORK_BUSY_OFST)
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#define PATTERN_RUNNING_OFST (0)
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#define PATTERN_RUNNING_MSK (0x00000001 << PATTERN_RUNNING_OFST)
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#define RX_BUSY_OFST (1)
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#define RX_BUSY_MSK (0x00000001 << RX_BUSY_OFST)
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#define PROCESSING_BUSY_OFST (2)
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#define PROCESSING_BUSY_MSK (0x00000001 << PROCESSING_BUSY_OFST)
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#define UDP_GEN_BUSY_OFST (3)
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#define UDP_GEN_BUSY_MSK (0x00000001 << UDP_GEN_BUSY_OFST)
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#define NETWORK_BUSY_OFST (4)
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#define NETWORK_BUSY_MSK (0x00000001 << NETWORK_BUSY_OFST)
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#define WAIT_FOR_TRIGGER_OFST (5)
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#define WAIT_FOR_TRIGGER_MSK (0x00000001 << WAIT_FOR_TRIGGER_OFST)
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#define RX_NOT_GOOD_OFST (6)
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#define RX_NOT_GOOD_MSK (0x00000001 << RX_NOT_GOOD_OFST)
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#define RX_NOT_GOOD_OFST (6)
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#define RX_NOT_GOOD_MSK (0x00000001 << RX_NOT_GOOD_OFST)
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#define STATUS_REG2 (0x8008)
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@ -39,8 +38,8 @@
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#define FPGACOMPDATE_OFST (0)
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#define FPGACOMPDATE_MSK (0x00ffffff << FPGACOMPDATE_OFST)
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#define FPGADETTYPE_OFST (24)
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#define FPGADETTYPE_MSK (0x000000ff << FPGADETTYPE_OFST)
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#define FPGADETTYPE_OFST (24)
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#define FPGADETTYPE_MSK (0x000000ff << FPGADETTYPE_OFST)
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#define FPGA_GIT_HEAD (0x8010)
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@ -51,8 +50,8 @@
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#define APICOMPDATE_OFST (0)
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#define APICOMPDATE_MSK (0x00ffffff << APICOMPDATE_OFST)
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#define APIDETTYPE_OFST (24)
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#define APIDETTYPE_MSK (0x000000ff << APIDETTYPE_OFST)
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#define APIDETTYPE_OFST (24)
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#define APIDETTYPE_MSK (0x000000ff << APIDETTYPE_OFST)
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#define A_FIFO_OVERFLOW_STATUS_REG (0x9000)
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@ -104,22 +103,23 @@
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#define FIFO_TO_GB_CONTROL_REG (0xA000)
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#define ENABLED_CHANNELS_ADC_OFST (0)
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#define ENABLED_CHANNELS_ADC_MSK (0x000000ff << ENABLED_CHANNELS_ADC_OFST)
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#define ENABLED_CHANNELS_D_OFST (8)
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#define ENABLED_CHANNELS_D_MSK (0x00000001 << ENABLED_CHANNELS_D_OFST)
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#define ENABLED_CHANNELS_X_OFST (9)
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#define ENABLED_CHANNELS_X_MSK (0x0000000f << ENABLED_CHANNELS_X_OFST)
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#define RO_MODE_ADC_OFST (13)
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#define RO_MODE_ADC_MSK (0x00000001 << RO_MODE_ADC_OFST)
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#define RO_MODE_D_OFST (14)
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#define RO_MODE_D_MSK (0x00000001 << RO_MODE_D_OFST)
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#define RO_MODE_X_OFST (15)
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#define RO_MODE_X_MSK (0x00000001 << RO_MODE_X_OFST)
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#define ENABLED_CHANNELS_ADC_OFST (0)
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#define ENABLED_CHANNELS_ADC_MSK (0x000000ff << ENABLED_CHANNELS_ADC_OFST)
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#define ENABLED_CHANNELS_D_OFST (8)
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#define ENABLED_CHANNELS_D_MSK (0x00000001 << ENABLED_CHANNELS_D_OFST)
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#define ENABLED_CHANNELS_X_OFST (9)
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#define ENABLED_CHANNELS_X_MSK (0x0000000f << ENABLED_CHANNELS_X_OFST)
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#define RO_MODE_ADC_OFST (13)
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#define RO_MODE_ADC_MSK (0x00000001 << RO_MODE_ADC_OFST)
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#define RO_MODE_D_OFST (14)
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#define RO_MODE_D_MSK (0x00000001 << RO_MODE_D_OFST)
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#define RO_MODE_X_OFST (15)
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#define RO_MODE_X_MSK (0x00000001 << RO_MODE_X_OFST)
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#define COUNT_FRAMES_FROM_UPDATE_OFST (16)
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#define COUNT_FRAMES_FROM_UPDATE_MSK (0x00000001 << COUNT_FRAMES_FROM_UPDATE_OFST)
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#define START_STREAMING_P_OFST (17)
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#define START_STREAMING_P_MSK (0x00000001 << START_STREAMING_P_OFST)
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#define COUNT_FRAMES_FROM_UPDATE_MSK \
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(0x00000001 << COUNT_FRAMES_FROM_UPDATE_OFST)
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#define START_STREAMING_P_OFST (17)
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#define START_STREAMING_P_MSK (0x00000001 << START_STREAMING_P_OFST)
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#define STREAM_BUFFER_CLEAR_OFST (18)
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#define STREAM_BUFFER_CLEAR_MSK (0x00000001 << STREAM_BUFFER_CLEAR_OFST)
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@ -148,26 +148,26 @@
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#define PKTPACKETLENGTHREG (0xA020)
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#define PACKETLENGTH1G_OFST (0)
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#define PACKETLENGTH1G_MSK (0x0000ffff << PACKETLENGTH1G_OFST)
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#define PACKETLENGTH1G_OFST (0)
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#define PACKETLENGTH1G_MSK (0x0000ffff << PACKETLENGTH1G_OFST)
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#define PACKETLENGTH10G_OFST (16)
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#define PACKETLENGTH10G_MSK (0x0000ffff << PACKETLENGTH10G_OFST)
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#define PKTNOPACKETSREG (0xA024)
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#define NOPACKETS1G_OFST (0)
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#define NOPACKETS1G_MSK (0x0000003f << NOPACKETS1G_OFST)
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#define NOPACKETS1G_OFST (0)
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#define NOPACKETS1G_MSK (0x0000003f << NOPACKETS1G_OFST)
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#define NOPACKETS10G_OFST (16)
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#define NOPACKETS10G_MSK (0x0000003f << NOPACKETS10G_OFST)
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#define PKTCTRLREG (0xA028)
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#define NOSERVERS_OFST (0)
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#define NOSERVERS_MSK (0x0000003f << NOSERVERS_OFST)
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#define NOSERVERS_OFST (0)
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#define NOSERVERS_MSK (0x0000003f << NOSERVERS_OFST)
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#define SERVERSTART_OFST (8)
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#define SERVERSTART_MSK (0x0000001f << SERVERSTART_OFST)
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#define ETHINTERF_OFST (16)
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#define ETHINTERF_MSK (0x00000001 << ETHINTERF_OFST)
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#define ETHINTERF_OFST (16)
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#define ETHINTERF_MSK (0x00000001 << ETHINTERF_OFST)
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#define PKTCOORDREG1 (0xA02C)
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@ -183,23 +183,23 @@
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#define FLOW_STATUS_REG (0xB000)
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#define RSM_BUSY_OFST (0)
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#define RSM_BUSY_MSK (0x00000001 << RSM_BUSY_OFST)
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#define RSM_BUSY_OFST (0)
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#define RSM_BUSY_MSK (0x00000001 << RSM_BUSY_OFST)
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#define RSM_TRG_WAIT_OFST (3)
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#define RSM_TRG_WAIT_MSK (0x00000001 << RSM_TRG_WAIT_OFST)
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#define CSM_BUSY_OFST (17)
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#define CSM_BUSY_MSK (0x00000001 << CSM_BUSY_OFST)
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#define CSM_BUSY_OFST (17)
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#define CSM_BUSY_MSK (0x00000001 << CSM_BUSY_OFST)
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#define FLOW_CONTROL_REG (0xB004)
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#define START_F_OFST (0)
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#define START_F_MSK (0x00000001 << START_F_OFST)
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#define STOP_F_OFST (1)
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#define STOP_F_MSK (0x00000001 << STOP_F_OFST)
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#define RST_F_OFST (2)
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#define RST_F_MSK (0x00000001 << RST_F_OFST)
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#define SW_TRIGGER_F_OFST (3)
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#define SW_TRIGGER_F_MSK (0x00000001 << SW_TRIGGER_F_OFST)
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#define START_F_OFST (0)
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#define START_F_MSK (0x00000001 << START_F_OFST)
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#define STOP_F_OFST (1)
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#define STOP_F_MSK (0x00000001 << STOP_F_OFST)
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#define RST_F_OFST (2)
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#define RST_F_MSK (0x00000001 << RST_F_OFST)
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#define SW_TRIGGER_F_OFST (3)
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#define SW_TRIGGER_F_MSK (0x00000001 << SW_TRIGGER_F_OFST)
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#define TRIGGER_ENABLE_OFST (4)
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#define TRIGGER_ENABLE_MSK (0x00000001 << TRIGGER_ENABLE_OFST)
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@ -265,10 +265,10 @@
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#define PATTERN_CNTRL_REG (0xB120)
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#define PATTERN_CNTRL_WR_OFST (0)
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#define PATTERN_CNTRL_WR_MSK (0x00000001 << PATTERN_CNTRL_WR_OFST)
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#define PATTERN_CNTRL_RD_OFST (1)
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#define PATTERN_CNTRL_RD_MSK (0x00000001 << PATTERN_CNTRL_RD_OFST)
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#define PATTERN_CNTRL_WR_OFST (0)
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#define PATTERN_CNTRL_WR_MSK (0x00000001 << PATTERN_CNTRL_WR_OFST)
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#define PATTERN_CNTRL_RD_OFST (1)
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#define PATTERN_CNTRL_RD_MSK (0x00000001 << PATTERN_CNTRL_RD_OFST)
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#define PATTERN_CNTRL_ADDR_OFST (16)
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#define PATTERN_CNTRL_ADDR_MSK (0x00001fff << PATTERN_CNTRL_ADDR_OFST)
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#define PATTERN_LIMIT_STRT_OFST (0)
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#define PATTERN_LIMIT_STRT_MSK (0x00001fff << PATTERN_LIMIT_STRT_OFST)
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#define PATTERN_LIMIT_STP_OFST (16)
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#define PATTERN_LIMIT_STP_MSK (0x00001fff << PATTERN_LIMIT_STP_OFST)
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#define PATTERN_LIMIT_STP_OFST (16)
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#define PATTERN_LIMIT_STP_MSK (0x00001fff << PATTERN_LIMIT_STP_OFST)
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#define PATTERN_LOOP_0_ADDR_REG (0xB128)
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#define PATTERN_LOOP_0_ADDR_STRT_OFST (0)
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#define PATTERN_LOOP_0_ADDR_STRT_MSK (0x00001fff << PATTERN_LOOP_0_ADDR_STRT_OFST)
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#define PATTERN_LOOP_0_ADDR_STRT_MSK \
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(0x00001fff << PATTERN_LOOP_0_ADDR_STRT_OFST)
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#define PATTERN_LOOP_0_ADDR_STP_OFST (16)
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#define PATTERN_LOOP_0_ADDR_STP_MSK (0x00001fff << PATTERN_LOOP_0_ADDR_STP_OFST)
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@ -300,7 +301,8 @@
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#define PATTERN_LOOP_1_ADDR_REG (0xB13C)
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#define PATTERN_LOOP_1_ADDR_STRT_OFST (0)
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#define PATTERN_LOOP_1_ADDR_STRT_MSK (0x00001fff << PATTERN_LOOP_1_ADDR_STRT_OFST)
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#define PATTERN_LOOP_1_ADDR_STRT_MSK \
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(0x00001fff << PATTERN_LOOP_1_ADDR_STRT_OFST)
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#define PATTERN_LOOP_1_ADDR_STP_OFST (16)
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#define PATTERN_LOOP_1_ADDR_STP_MSK (0x00001fff << PATTERN_LOOP_1_ADDR_STP_OFST)
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@ -318,7 +320,8 @@
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#define PATTERN_LOOP_2_ADDR_REG (0xB150)
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#define PATTERN_LOOP_2_ADDR_STRT_OFST (0)
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#define PATTERN_LOOP_2_ADDR_STRT_MSK (0x00001fff << PATTERN_LOOP_2_ADDR_STRT_OFST)
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#define PATTERN_LOOP_2_ADDR_STRT_MSK \
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(0x00001fff << PATTERN_LOOP_2_ADDR_STRT_OFST)
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#define PATTERN_LOOP_2_ADDR_STP_OFST (16)
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#define PATTERN_LOOP_2_ADDR_STP_MSK (0x00001fff << PATTERN_LOOP_2_ADDR_STP_OFST)
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@ -336,7 +339,8 @@
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#define PATTERN_LOOP_3_ADDR_REG (0xB164)
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#define PATTERN_LOOP_3_ADDR_STRT_OFST (0)
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#define PATTERN_LOOP_3_ADDR_STRT_MSK (0x00001fff << PATTERN_LOOP_3_ADDR_STRT_OFST)
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#define PATTERN_LOOP_3_ADDR_STRT_MSK \
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(0x00001fff << PATTERN_LOOP_3_ADDR_STRT_OFST)
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#define PATTERN_LOOP_3_ADDR_STP_OFST (16)
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#define PATTERN_LOOP_3_ADDR_STP_MSK (0x00001fff << PATTERN_LOOP_3_ADDR_STP_OFST)
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@ -354,7 +358,8 @@
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#define PATTERN_LOOP_4_ADDR_REG (0xB178)
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#define PATTERN_LOOP_4_ADDR_STRT_OFST (0)
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#define PATTERN_LOOP_4_ADDR_STRT_MSK (0x00001fff << PATTERN_LOOP_4_ADDR_STRT_OFST)
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#define PATTERN_LOOP_4_ADDR_STRT_MSK \
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(0x00001fff << PATTERN_LOOP_4_ADDR_STRT_OFST)
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#define PATTERN_LOOP_4_ADDR_STP_OFST (16)
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#define PATTERN_LOOP_4_ADDR_STP_MSK (0x00001fff << PATTERN_LOOP_4_ADDR_STP_OFST)
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@ -372,7 +377,8 @@
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#define PATTERN_LOOP_5_ADDR_REG (0xB18C)
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#define PATTERN_LOOP_5_ADDR_STRT_OFST (0)
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#define PATTERN_LOOP_5_ADDR_STRT_MSK (0x00001fff << PATTERN_LOOP_5_ADDR_STRT_OFST)
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#define PATTERN_LOOP_5_ADDR_STRT_MSK \
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(0x00001fff << PATTERN_LOOP_5_ADDR_STRT_OFST)
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#define PATTERN_LOOP_5_ADDR_STP_OFST (16)
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#define PATTERN_LOOP_5_ADDR_STP_MSK (0x00001fff << PATTERN_LOOP_5_ADDR_STP_OFST)
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#define DBITFIFOCTRLREG (0xB1A4)
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#define DBITRD_OFST (0)
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#define DBITRD_MSK (0x00000001 << DBITRD_OFST)
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#define DBITRST_OFST (1)
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#define DBITRST_MSK (0x00000001 << DBITRST_OFST)
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#define DBITFULL_OFST (2)
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#define DBITFULL_MSK (0x00000001 << DBITFULL_OFST)
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#define DBITEMPTY_OFST (3)
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#define DBITEMPTY_MSK (0x00000001 << DBITEMPTY_OFST)
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#define DBITRD_OFST (0)
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#define DBITRD_MSK (0x00000001 << DBITRD_OFST)
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#define DBITRST_OFST (1)
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#define DBITRST_MSK (0x00000001 << DBITRST_OFST)
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#define DBITFULL_OFST (2)
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#define DBITFULL_MSK (0x00000001 << DBITFULL_OFST)
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#define DBITEMPTY_OFST (3)
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#define DBITEMPTY_MSK (0x00000001 << DBITEMPTY_OFST)
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#define DBITUNDERFLOW_OFST (4)
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#define DBITUNDERFLOW_MSK (0x00000001 << DBITUNDERFLOW_OFST)
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#define DBITOVERFLOW_OFST (5)
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#define DBITOVERFLOW_MSK (0x00000001 << DBITOVERFLOW_OFST)
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#define DBITOVERFLOW_OFST (5)
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#define DBITOVERFLOW_MSK (0x00000001 << DBITOVERFLOW_OFST)
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#define DBITFIFODATAREG1 (0xB1A8)
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@ -414,14 +420,14 @@
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#define MATTERHORNSPICTRL (0xB1B8)
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#define CONFIGSTART_P_OFST (0)
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#define CONFIGSTART_P_MSK (0x00000001 << CONFIGSTART_P_OFST)
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#define PERIPHERYRST_P_OFST (1)
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#define PERIPHERYRST_P_MSK (0x00000001 << PERIPHERYRST_P_OFST)
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#define STARTREAD_P_OFST (2)
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#define STARTREAD_P_MSK (0x00000001 << STARTREAD_P_OFST)
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#define BUSY_OFST (3)
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#define BUSY_MSK (0x00000001 << BUSY_OFST)
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#define CONFIGSTART_P_OFST (0)
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#define CONFIGSTART_P_MSK (0x00000001 << CONFIGSTART_P_OFST)
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#define PERIPHERYRST_P_OFST (1)
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#define PERIPHERYRST_P_MSK (0x00000001 << PERIPHERYRST_P_OFST)
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#define STARTREAD_P_OFST (2)
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#define STARTREAD_P_MSK (0x00000001 << STARTREAD_P_OFST)
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#define BUSY_OFST (3)
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#define BUSY_MSK (0x00000001 << BUSY_OFST)
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#define READOUTFROMASIC_OFST (4)
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#define READOUTFROMASIC_MSK (0x00000001 << READOUTFROMASIC_OFST)
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@ -441,28 +447,28 @@
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#define LINKDOWNLATCHEDOUT_OFST (0)
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#define LINKDOWNLATCHEDOUT_MSK (0x00000001 << LINKDOWNLATCHEDOUT_OFST)
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#define TXUSERCLKACTIVE_OFST (1)
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#define TXUSERCLKACTIVE_MSK (0x00000001 << TXUSERCLKACTIVE_OFST)
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#define RXUSERCLKACTIVE_OFST (2)
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#define RXUSERCLKACTIVE_MSK (0x00000001 << RXUSERCLKACTIVE_OFST)
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#define RXCOMMADET_OFST (3)
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#define RXCOMMADET_MSK (0x0000000f << RXCOMMADET_OFST)
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#define RXBYTEREALIGN_OFST (7)
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#define RXBYTEREALIGN_MSK (0x0000000f << RXBYTEREALIGN_OFST)
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#define RXBYTEISALIGNED_OFST (11)
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#define RXBYTEISALIGNED_MSK (0x0000000f << RXBYTEISALIGNED_OFST)
|
||||
#define GTWIZRXCDRSTABLE_OFST (15)
|
||||
#define GTWIZRXCDRSTABLE_MSK (0x00000001 << GTWIZRXCDRSTABLE_OFST)
|
||||
#define RESETTXDONE_OFST (16)
|
||||
#define RESETTXDONE_MSK (0x00000001 << RESETTXDONE_OFST)
|
||||
#define RESETRXDONE_OFST (17)
|
||||
#define RESETRXDONE_MSK (0x00000001 << RESETRXDONE_OFST)
|
||||
#define RXPMARESETDONE_OFST (18)
|
||||
#define RXPMARESETDONE_MSK (0x0000000f << RXPMARESETDONE_OFST)
|
||||
#define TXPMARESETDONE_OFST (22)
|
||||
#define TXPMARESETDONE_MSK (0x0000000f << TXPMARESETDONE_OFST)
|
||||
#define GTTPOWERGOOD_OFST (26)
|
||||
#define GTTPOWERGOOD_MSK (0x0000000f << GTTPOWERGOOD_OFST)
|
||||
#define TXUSERCLKACTIVE_OFST (1)
|
||||
#define TXUSERCLKACTIVE_MSK (0x00000001 << TXUSERCLKACTIVE_OFST)
|
||||
#define RXUSERCLKACTIVE_OFST (2)
|
||||
#define RXUSERCLKACTIVE_MSK (0x00000001 << RXUSERCLKACTIVE_OFST)
|
||||
#define RXCOMMADET_OFST (3)
|
||||
#define RXCOMMADET_MSK (0x0000000f << RXCOMMADET_OFST)
|
||||
#define RXBYTEREALIGN_OFST (7)
|
||||
#define RXBYTEREALIGN_MSK (0x0000000f << RXBYTEREALIGN_OFST)
|
||||
#define RXBYTEISALIGNED_OFST (11)
|
||||
#define RXBYTEISALIGNED_MSK (0x0000000f << RXBYTEISALIGNED_OFST)
|
||||
#define GTWIZRXCDRSTABLE_OFST (15)
|
||||
#define GTWIZRXCDRSTABLE_MSK (0x00000001 << GTWIZRXCDRSTABLE_OFST)
|
||||
#define RESETTXDONE_OFST (16)
|
||||
#define RESETTXDONE_MSK (0x00000001 << RESETTXDONE_OFST)
|
||||
#define RESETRXDONE_OFST (17)
|
||||
#define RESETRXDONE_MSK (0x00000001 << RESETRXDONE_OFST)
|
||||
#define RXPMARESETDONE_OFST (18)
|
||||
#define RXPMARESETDONE_MSK (0x0000000f << RXPMARESETDONE_OFST)
|
||||
#define TXPMARESETDONE_OFST (22)
|
||||
#define TXPMARESETDONE_MSK (0x0000000f << TXPMARESETDONE_OFST)
|
||||
#define GTTPOWERGOOD_OFST (26)
|
||||
#define GTTPOWERGOOD_MSK (0x0000000f << GTTPOWERGOOD_OFST)
|
||||
|
||||
#define TRANSCEIVERSTATUS2 (0xB81C)
|
||||
|
||||
@ -471,22 +477,22 @@
|
||||
|
||||
#define TRANSCEIVERCONTROL (0xB820)
|
||||
|
||||
#define GTWIZRESETALL_OFST (0)
|
||||
#define GTWIZRESETALL_MSK (0x00000001 << GTWIZRESETALL_OFST)
|
||||
#define GTWIZRESETALL_OFST (0)
|
||||
#define GTWIZRESETALL_MSK (0x00000001 << GTWIZRESETALL_OFST)
|
||||
#define RESETTXPLLANDDATAPATH_OFST (1)
|
||||
#define RESETTXPLLANDDATAPATH_MSK (0x00000001 << RESETTXPLLANDDATAPATH_OFST)
|
||||
#define RESETTXDATAPATHIN_OFST (2)
|
||||
#define RESETTXDATAPATHIN_MSK (0x00000001 << RESETTXDATAPATHIN_OFST)
|
||||
#define RESETTXDATAPATHIN_OFST (2)
|
||||
#define RESETTXDATAPATHIN_MSK (0x00000001 << RESETTXDATAPATHIN_OFST)
|
||||
#define RESETRXPLLANDDATAPATH_OFST (3)
|
||||
#define RESETRXPLLANDDATAPATH_MSK (0x00000001 << RESETRXPLLANDDATAPATH_OFST)
|
||||
#define RESETRXDATAPATHIN_OFST (4)
|
||||
#define RESETRXDATAPATHIN_MSK (0x00000001 << RESETRXDATAPATHIN_OFST)
|
||||
#define RXPOLARITY_OFST (5)
|
||||
#define RXPOLARITY_MSK (0x0000000f << RXPOLARITY_OFST)
|
||||
#define RXERRORCNTRESET_OFST (9)
|
||||
#define RXERRORCNTRESET_MSK (0x0000000f << RXERRORCNTRESET_OFST)
|
||||
#define RXMSBLSBINVERT_OFST (13)
|
||||
#define RXMSBLSBINVERT_MSK (0x0000000f << RXMSBLSBINVERT_OFST)
|
||||
#define RESETRXDATAPATHIN_OFST (4)
|
||||
#define RESETRXDATAPATHIN_MSK (0x00000001 << RESETRXDATAPATHIN_OFST)
|
||||
#define RXPOLARITY_OFST (5)
|
||||
#define RXPOLARITY_MSK (0x0000000f << RXPOLARITY_OFST)
|
||||
#define RXERRORCNTRESET_OFST (9)
|
||||
#define RXERRORCNTRESET_MSK (0x0000000f << RXERRORCNTRESET_OFST)
|
||||
#define RXMSBLSBINVERT_OFST (13)
|
||||
#define RXMSBLSBINVERT_MSK (0x0000000f << RXMSBLSBINVERT_OFST)
|
||||
|
||||
#define TRANSCEIVERERRCNT_REG0 (0xB824)
|
||||
|
||||
|
||||
@ -10,4 +10,4 @@
|
||||
#define APICTB "developer 0x250131"
|
||||
#define APIMYTHEN3 "developer 0x250131"
|
||||
#define APIXILINXCTB "developer 0x250213"
|
||||
#define APIJUNGFRAU "developer 0x250224"
|
||||
#define APIJUNGFRAU "developer 0x250224"
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user