mirror of
https://github.com/slsdetectorgroup/slsDetectorPackage.git
synced 2025-04-24 23:30:03 +02:00
commit
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serverBin/ctbDetectorServer_developer
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serverBin/ctbDetectorServer_developer
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../slsDetectorServers/ctbDetectorServer/bin/ctbDetectorServer_developer
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../slsDetectorServers/ctbDetectorServer/bin/ctbDetectorServerv5.0.0-rc2
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serverBin/eigerDetectorServer_developer
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../slsDetectorServers/eigerDetectorServer/bin/eigerDetectorServer_developer
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../slsDetectorServers/eigerDetectorServer/bin/eigerDetectorServerv5.0.0-rc2
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serverBin/gotthard2DetectorServer_developer
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../slsDetectorServers/gotthard2DetectorServer/bin/gotthard2DetectorServer_developer
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../slsDetectorServers/gotthard2DetectorServer/bin/gotthard2DetectorServerv5.0.0-rc2
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serverBin/gotthardDetectorServer_developer
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../slsDetectorServers/gotthardDetectorServer/bin/gotthardDetectorServer_developer
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../slsDetectorServers/gotthardDetectorServer/bin/gotthardDetectorServerv5.0.0-rc2
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serverBin/jungfrauDetectorServer_developer
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../slsDetectorServers/jungfrauDetectorServer/bin/jungfrauDetectorServer_developer
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../slsDetectorServers/jungfrauDetectorServer/bin/jungfrauDetectorServerv5.0.0-rc2
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serverBin/moenchDetectorServer_developer
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../slsDetectorServers/moenchDetectorServer/bin/moenchDetectorServer_developer
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../slsDetectorServers/moenchDetectorServer/bin/moenchDetectorServerv5.0.0-rc2
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serverBin/mythen3DetectorServer_developer
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../slsDetectorServers/mythen3DetectorServer/bin/mythen3DetectorServer_developer
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../slsDetectorServers/mythen3DetectorServer/bin/mythen3DetectorServerv5.0.0-rc2
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@ -148,6 +148,16 @@
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#define DTA_OFFSET_REG (0x24 * REG_OFFSET + BASE_CONTROL)
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/* Formatting for adif core -----------------------------------------------*/
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#define ADIF_CONFIG_REG (0x00 * REG_OFFSET + BASE_ADIF)
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#define ADIF_ADDTNL_OFST_OFST (0)
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#define ADIF_ADDTNL_OFST_MSK (0x00000003 << ADIF_ADDTNL_OFST_OFST)
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#define ADIF_PIPELINE_OFST (4)
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#define ADIF_PIPELINE_MSK (0x0000000F << ADIF_PIPELINE_OFST)
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/* Formatting for data core -----------------------------------------------*/
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#define FMT_CONFIG_REG (0x00 * REG_OFFSET + BASE_FMT)
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@ -418,6 +418,7 @@ void setupDetector() {
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setHighVoltage(DEFAULT_HIGH_VOLTAGE);
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setDefaultDacs();
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setASICDefaults();
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setADIFDefaults();
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// dynamic range
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setDynamicRange(DEFAULT_DYNAMIC_RANGE);
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@ -514,6 +515,17 @@ void setASICDefaults() {
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bus_w(ASIC_RDO_CONFIG_REG, val);
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}
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void setADIFDefaults() {
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uint32_t addr = ADIF_CONFIG_REG;
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bus_w(addr, ((bus_r(addr) & ~ADIF_ADDTNL_OFST_MSK) & ~ADIF_PIPELINE_MSK));
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bus_w(addr,
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(bus_r(addr) | ((DEFAULT_ADIF_PIPELINE_VAL << ADIF_PIPELINE_OFST) &
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ADIF_PIPELINE_MSK)));
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bus_w(addr,
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(bus_r(addr) | ((DEFAULT_ADIF_ADD_OFST_VAL << ADIF_ADDTNL_OFST_OFST) &
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ADIF_ADDTNL_OFST_MSK)));
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}
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/* firmware functions (resets) */
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void cleanFifos() {
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@ -1025,9 +1037,24 @@ int setTrimbits(int *trimbits) {
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LOG(logINFO, ("Trimbits validated\n"));
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trimmingPrint = logDEBUG5;
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// remember previous run clock
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uint32_t prevRunClk = clkDivider[SYSTEM_C0];
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// set to trimming clock
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if (setClockDivider(SYSTEM_C0, DEFAULT_TRIMMING_RUN_CLKDIV) == FAIL) {
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LOG(logERROR,
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("Could not start trimming. Could not set to trimming clock\n"));
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return FAIL;
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}
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// trimming
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int error = 0;
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uint64_t patword = 0;
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int iaddr = 0;
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for (int ichip = 0; ichip < NCHIP; ichip++) {
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if (error != 0) {
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break;
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}
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LOG(logDEBUG1, (" Chip %d\n", ichip));
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iaddr = 0;
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patword = 0;
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@ -1118,8 +1145,8 @@ int setTrimbits(int *trimbits) {
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if (iaddr >= MAX_PATTERN_LENGTH) {
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LOG(logERROR, ("Addr 0x%x is past max_address_length 0x%x!\n",
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iaddr, MAX_PATTERN_LENGTH));
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trimmingPrint = logINFO;
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return FAIL;
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error = 1;
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break;
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}
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// set pattern wait address
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@ -1141,12 +1168,25 @@ int setTrimbits(int *trimbits) {
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startPattern();
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}
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// copy trimbits locally
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for (int ichan = 0; ichan < ((detectorModules)->nchan); ++ichan) {
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detectorChans[ichan] = trimbits[ichan];
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if (error == 0) {
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// copy trimbits locally
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for (int ichan = 0; ichan < ((detectorModules)->nchan); ++ichan) {
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detectorChans[ichan] = trimbits[ichan];
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}
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LOG(logINFO, ("All trimbits have been loaded\n"));
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}
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trimmingPrint = logINFO;
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LOG(logINFO, ("All trimbits have been loaded\n"));
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// set back to previous clock
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if (setClockDivider(SYSTEM_C0, prevRunClk) == FAIL) {
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LOG(logERROR, ("Could not set to previous run clock after trimming\n"));
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return FAIL;
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}
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if (error != 0) {
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return FAIL;
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}
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return OK;
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}
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@ -39,14 +39,17 @@
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#define DEFAULT_TIMING_MODE (AUTO_TIMING)
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#define DEFAULT_READOUT_C0 (10) //(100000000) // rdo_clk, 100 MHz
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#define DEFAULT_READOUT_C1 (10) //(100000000) // smp sample clk (x2), 100 MHz
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#define DEFAULT_SYSTEM_C0 (20) // (50000000) // run_clk, 50 MHz
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#define DEFAULT_SYSTEM_C0 (10) //(100000000) // run_clk, 100 MHz
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#define DEFAULT_SYSTEM_C1 (10) //(100000000) // sync_clk, 100 MHz
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#define DEFAULT_SYSTEM_C2 (10) //(100000000) // str_clk, 100 MHz
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#define DEFAULT_SYSTEM_C3 (5) //(200000000) // smp_clk, 200 MHz
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// (DEFAULT_SYSTEM_C3 only for timing receiver) should not be changed
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#define DEFAULT_TRIMMING_RUN_CLKDIV (40) // (25000000) // 25 MHz
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#define DEFAULT_ASIC_LATCHING_NUM_PULSES (10)
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#define DEFAULT_MSTR_OTPT_P1_NUM_PULSES (20)
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#define DEFAULT_ADIF_PIPELINE_VAL (8)
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#define DEFAULT_ADIF_ADD_OFST_VAL (0)
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/* Firmware Definitions */
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#define MAX_TIMESLOT_VAL (0xFFFFFF)
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@ -120,6 +120,7 @@ int setDefaultDacs();
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#endif
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#ifdef MYTHEN3D
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void setASICDefaults();
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void setADIFDefaults();
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#endif
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#if defined(GOTTHARD2D) || defined(EIGERD)
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int readConfigFile();
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@ -8,5 +8,5 @@
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#define APIGOTTHARD2 0x201009
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#define APIJUNGFRAU 0x201009
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#define APIMYTHEN3 0x201009
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#define APIMOENCH 0x201008
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#define APIMOENCH 0x201009
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#define APIEIGER 0x201009
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