Merge pull request #200 from slsdetectorgroup/m3clk

M3clk
This commit is contained in:
Dhanya Thattil 2020-10-09 17:09:05 +02:00 committed by GitHub
commit e4226d34dc
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31 changed files with 69 additions and 15 deletions

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../slsDetectorServers/ctbDetectorServer/bin/ctbDetectorServer_developer

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../slsDetectorServers/ctbDetectorServer/bin/ctbDetectorServerv5.0.0-rc2

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../slsDetectorServers/eigerDetectorServer/bin/eigerDetectorServer_developer

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../slsDetectorServers/eigerDetectorServer/bin/eigerDetectorServerv5.0.0-rc2

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../slsDetectorServers/gotthard2DetectorServer/bin/gotthard2DetectorServer_developer

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../slsDetectorServers/gotthard2DetectorServer/bin/gotthard2DetectorServerv5.0.0-rc2

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../slsDetectorServers/gotthardDetectorServer/bin/gotthardDetectorServer_developer

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../slsDetectorServers/gotthardDetectorServer/bin/gotthardDetectorServerv5.0.0-rc2

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../slsDetectorServers/jungfrauDetectorServer/bin/jungfrauDetectorServer_developer

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../slsDetectorServers/jungfrauDetectorServer/bin/jungfrauDetectorServerv5.0.0-rc2

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../slsDetectorServers/moenchDetectorServer/bin/moenchDetectorServer_developer

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../slsDetectorServers/moenchDetectorServer/bin/moenchDetectorServerv5.0.0-rc2

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../slsDetectorServers/mythen3DetectorServer/bin/mythen3DetectorServer_developer

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../slsDetectorServers/mythen3DetectorServer/bin/mythen3DetectorServerv5.0.0-rc2

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@ -148,6 +148,16 @@
#define DTA_OFFSET_REG (0x24 * REG_OFFSET + BASE_CONTROL)
/* Formatting for adif core -----------------------------------------------*/
#define ADIF_CONFIG_REG (0x00 * REG_OFFSET + BASE_ADIF)
#define ADIF_ADDTNL_OFST_OFST (0)
#define ADIF_ADDTNL_OFST_MSK (0x00000003 << ADIF_ADDTNL_OFST_OFST)
#define ADIF_PIPELINE_OFST (4)
#define ADIF_PIPELINE_MSK (0x0000000F << ADIF_PIPELINE_OFST)
/* Formatting for data core -----------------------------------------------*/
#define FMT_CONFIG_REG (0x00 * REG_OFFSET + BASE_FMT)

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@ -418,6 +418,7 @@ void setupDetector() {
setHighVoltage(DEFAULT_HIGH_VOLTAGE);
setDefaultDacs();
setASICDefaults();
setADIFDefaults();
// dynamic range
setDynamicRange(DEFAULT_DYNAMIC_RANGE);
@ -514,6 +515,17 @@ void setASICDefaults() {
bus_w(ASIC_RDO_CONFIG_REG, val);
}
void setADIFDefaults() {
uint32_t addr = ADIF_CONFIG_REG;
bus_w(addr, ((bus_r(addr) & ~ADIF_ADDTNL_OFST_MSK) & ~ADIF_PIPELINE_MSK));
bus_w(addr,
(bus_r(addr) | ((DEFAULT_ADIF_PIPELINE_VAL << ADIF_PIPELINE_OFST) &
ADIF_PIPELINE_MSK)));
bus_w(addr,
(bus_r(addr) | ((DEFAULT_ADIF_ADD_OFST_VAL << ADIF_ADDTNL_OFST_OFST) &
ADIF_ADDTNL_OFST_MSK)));
}
/* firmware functions (resets) */
void cleanFifos() {
@ -1025,9 +1037,24 @@ int setTrimbits(int *trimbits) {
LOG(logINFO, ("Trimbits validated\n"));
trimmingPrint = logDEBUG5;
// remember previous run clock
uint32_t prevRunClk = clkDivider[SYSTEM_C0];
// set to trimming clock
if (setClockDivider(SYSTEM_C0, DEFAULT_TRIMMING_RUN_CLKDIV) == FAIL) {
LOG(logERROR,
("Could not start trimming. Could not set to trimming clock\n"));
return FAIL;
}
// trimming
int error = 0;
uint64_t patword = 0;
int iaddr = 0;
for (int ichip = 0; ichip < NCHIP; ichip++) {
if (error != 0) {
break;
}
LOG(logDEBUG1, (" Chip %d\n", ichip));
iaddr = 0;
patword = 0;
@ -1118,8 +1145,8 @@ int setTrimbits(int *trimbits) {
if (iaddr >= MAX_PATTERN_LENGTH) {
LOG(logERROR, ("Addr 0x%x is past max_address_length 0x%x!\n",
iaddr, MAX_PATTERN_LENGTH));
trimmingPrint = logINFO;
return FAIL;
error = 1;
break;
}
// set pattern wait address
@ -1141,12 +1168,25 @@ int setTrimbits(int *trimbits) {
startPattern();
}
// copy trimbits locally
for (int ichan = 0; ichan < ((detectorModules)->nchan); ++ichan) {
detectorChans[ichan] = trimbits[ichan];
if (error == 0) {
// copy trimbits locally
for (int ichan = 0; ichan < ((detectorModules)->nchan); ++ichan) {
detectorChans[ichan] = trimbits[ichan];
}
LOG(logINFO, ("All trimbits have been loaded\n"));
}
trimmingPrint = logINFO;
LOG(logINFO, ("All trimbits have been loaded\n"));
// set back to previous clock
if (setClockDivider(SYSTEM_C0, prevRunClk) == FAIL) {
LOG(logERROR, ("Could not set to previous run clock after trimming\n"));
return FAIL;
}
if (error != 0) {
return FAIL;
}
return OK;
}

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@ -39,14 +39,17 @@
#define DEFAULT_TIMING_MODE (AUTO_TIMING)
#define DEFAULT_READOUT_C0 (10) //(100000000) // rdo_clk, 100 MHz
#define DEFAULT_READOUT_C1 (10) //(100000000) // smp sample clk (x2), 100 MHz
#define DEFAULT_SYSTEM_C0 (20) // (50000000) // run_clk, 50 MHz
#define DEFAULT_SYSTEM_C0 (10) //(100000000) // run_clk, 100 MHz
#define DEFAULT_SYSTEM_C1 (10) //(100000000) // sync_clk, 100 MHz
#define DEFAULT_SYSTEM_C2 (10) //(100000000) // str_clk, 100 MHz
#define DEFAULT_SYSTEM_C3 (5) //(200000000) // smp_clk, 200 MHz
// (DEFAULT_SYSTEM_C3 only for timing receiver) should not be changed
#define DEFAULT_TRIMMING_RUN_CLKDIV (40) // (25000000) // 25 MHz
#define DEFAULT_ASIC_LATCHING_NUM_PULSES (10)
#define DEFAULT_MSTR_OTPT_P1_NUM_PULSES (20)
#define DEFAULT_ADIF_PIPELINE_VAL (8)
#define DEFAULT_ADIF_ADD_OFST_VAL (0)
/* Firmware Definitions */
#define MAX_TIMESLOT_VAL (0xFFFFFF)

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@ -120,6 +120,7 @@ int setDefaultDacs();
#endif
#ifdef MYTHEN3D
void setASICDefaults();
void setADIFDefaults();
#endif
#if defined(GOTTHARD2D) || defined(EIGERD)
int readConfigFile();

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@ -8,5 +8,5 @@
#define APIGOTTHARD2 0x201009
#define APIJUNGFRAU 0x201009
#define APIMYTHEN3 0x201009
#define APIMOENCH 0x201008
#define APIMOENCH 0x201009
#define APIEIGER 0x201009