mirror of
https://github.com/slsdetectorgroup/slsDetectorPackage.git
synced 2025-06-23 18:17:59 +02:00
created AD9252 for old gotthard modules in use, it runs in both roi and non roi for old and new modules, data needs to be checked by Jiaguo to confirm some parts of the code that has FIXME to be checked later
This commit is contained in:
1
slsDetectorServers/gotthardDetectorServer/AD9252.h
Symbolic link
1
slsDetectorServers/gotthardDetectorServer/AD9252.h
Symbolic link
@ -0,0 +1 @@
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../slsDetectorServer/AD9252.h
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@ -14,6 +14,15 @@
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#define GAIN_CONFGAIN_MDM_GAIN_VAL ((0x2 << GAIN_CONFGAIN_OFST) & GAIN_CONFGAIN_MSK)
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#define GAIN_CONFGAIN_VRY_HGH_GAIN_VAL ((0x1 << GAIN_CONFGAIN_OFST) & GAIN_CONFGAIN_MSK)
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/** Flow Control register */
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//#define FLOW_CONTROL_REG (0x11 << MEM_MAP_SHIFT)
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/** Flow Status register */
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//#define FLOW_STATUS_REG (0x12 << MEM_MAP_SHIFT)
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/** Frame register */
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//#define FRAME_REG (0x13 << MEM_MAP_SHIFT)
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/** Multi Purpose register */
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#define MULTI_PURPOSE_REG (0x14 << MEM_MAP_SHIFT)
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@ -58,6 +67,9 @@
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#define DAQ_PCKT_LNGTH_NO_ROI_VAL ((0x0013f << DAQ_PCKT_LNGTH_OFST) & DAQ_PCKT_LNGTH_MSK)
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#define DAQ_PCKT_LNGTH_ROI_VAL ((0x0007f << DAQ_PCKT_LNGTH_OFST) & DAQ_PCKT_LNGTH_MSK)
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/** Time From Start register */
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//#define TIME_FROM_START_REG (0x16 << MEM_MAP_SHIFT)
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/** DAC Control register */
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#define DAC_CNTRL_REG (0x17 << MEM_MAP_SHIFT)
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@ -106,6 +118,9 @@
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#define ADC_SYNC_ENET_DELAY_ROI_VAL ((0x1b << ADC_SYNC_ENET_DELAY_OFST) & ADC_SYNC_ENET_DELAY_MSK)
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//FIXME: try with just 0x8 and 0x1.. it is anded with 0000 in firmware anyway
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/** Time From Start register */
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//#define MU_TIME_REG (0x1a << MEM_MAP_SHIFT)
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/** Temperatre SPI In register */
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#define TEMP_SPI_IN_REG (0x1b << MEM_MAP_SHIFT)
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@ -132,6 +147,9 @@
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/** SPI Configure register */
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#define ENET_CONF_REG (0x1e << MEM_MAP_SHIFT)
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/** Write TSE Shadow register */
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//#define WRITE_TSE_SHADOW_REG (0x1f << MEM_MAP_SHIFT)
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/** High Voltage register */
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#define HV_REG (0x20 << MEM_MAP_SHIFT)
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@ -160,22 +178,6 @@
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#define FIX_PATT_VAL (0xACDC1980)
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/** Config register */
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#define CONFIG_REG (0x26 << MEM_MAP_SHIFT)
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#define CONFIG_SLAVE_OFST (0) // Not used in FW & SW
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#define CONFIG_SLAVE_MSK (0x00000001 << CONFIG_SLAVE_OFST)
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#define CONFIG_MASTER_OFST (1) // Not used in FW & SW
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#define CONFIG_MASTER_MSK (0x00000001 << CONFIG_MASTER_OFST)
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#define CONFIG_TM_GT_ENBL_OFST (2) // Not used in FW & SW
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#define CONFIG_TM_GT_ENBL_MSK (0x00000001 << CONFIG_TM_GT_ENBL_OFST)
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#define CONFIG_CPU_RDT_OFST (12)
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#define CONFIG_CPU_RDT_MSK (0x00000001 << CONFIG_CPU_RDT_OFST)
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#define CONFIG_CNTNS_RDT_OFST (23) // Not used in FW & SW
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#define CONFIG_CNTNS_RDT_MSK (0x00000001 << CONFIG_CNTNS_RDT_OFST)
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#define CONFIG_ACCMLT_CNTS_OFST (24) // Not used in FW & SW
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#define CONFIG_ACCMLT_CNTS_MSK (0x00000001 << CONFIG_ACCMLT_CNTS_OFST)
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/** 16 bit Control register */
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#define CONTROL_REG (0x24 << MEM_MAP_SHIFT)
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@ -235,6 +237,22 @@
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#define STATUS_RN_FNSHD_MSK (0x00000001 << STATUS_RN_FNSHD_OFST)
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#define STATUS_IDLE_MSK (0x0000FFFF << 0)
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/** Config register */
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#define CONFIG_REG (0x26 << MEM_MAP_SHIFT)
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#define CONFIG_SLAVE_OFST (0) // Not used in FW & SW
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#define CONFIG_SLAVE_MSK (0x00000001 << CONFIG_SLAVE_OFST)
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#define CONFIG_MASTER_OFST (1) // Not used in FW & SW
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#define CONFIG_MASTER_MSK (0x00000001 << CONFIG_MASTER_OFST)
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#define CONFIG_TM_GT_ENBL_OFST (2) // Not used in FW & SW
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#define CONFIG_TM_GT_ENBL_MSK (0x00000001 << CONFIG_TM_GT_ENBL_OFST)
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#define CONFIG_CPU_RDT_OFST (12)
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#define CONFIG_CPU_RDT_MSK (0x00000001 << CONFIG_CPU_RDT_OFST)
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#define CONFIG_CNTNS_RDT_OFST (23) // Not used in FW & SW
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#define CONFIG_CNTNS_RDT_MSK (0x00000001 << CONFIG_CNTNS_RDT_OFST)
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#define CONFIG_ACCMLT_CNTS_OFST (24) // Not used in FW & SW
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#define CONFIG_ACCMLT_CNTS_MSK (0x00000001 << CONFIG_ACCMLT_CNTS_OFST)
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/** External Signal register */
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#define EXT_SIGNAL_REG (0x27 << MEM_MAP_SHIFT)
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@ -243,10 +261,13 @@
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#define EXT_SIGNAL_OFF_VAL ((0x0 << EXT_SIGNAL_OFST) & EXT_SIGNAL_MSK)
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#define EXT_SIGNAL_TRGGR_IN_RSNG_VAL ((0x3 << EXT_SIGNAL_OFST) & EXT_SIGNAL_MSK)
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#define EXT_SIGNAL_TRGGR_IN_FLLNG_VAL ((0x4 << EXT_SIGNAL_OFST) & EXT_SIGNAL_MSK)
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/*
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#define FPGA_SVN_REG 0x29<<11
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#define LOOK_AT_ME_REG 0x28<<11
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*/
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/** Look at me register */
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//#define LOOK_AT_ME_REG (0x28 << MEM_MAP_SHIFT)
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/** FPGA SVN register */
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//#define FPGA_SVN_REG (0x29 << MEM_MAP_SHIFT)
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/** Chip of Interest register */
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#define CHIP_OF_INTRST_REG (0x2a << MEM_MAP_SHIFT)
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@ -255,6 +276,9 @@
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#define CHIP_OF_INTRST_NUM_CHNNLS_OFST (16)
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#define CHIP_OF_INTRST_NUM_CHNNLS_MSK (0x0000FFFF << CHIP_OF_INTRST_NUM_CHNNLS_OFST)
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/** Out MUX register */
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//#define OUT_MUX_REG (0x2b << MEM_MAP_SHIFT)
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/** Board Version register */
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#define BOARD_REVISION_REG (0x2c << MEM_MAP_SHIFT)
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@ -265,14 +289,27 @@
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//#define DETECTOR_TYPE_GOTTHARD_VAL (??)
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#define DETECTOR_TYPE_MOENCH_VAL (2)
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/** Memory Test register */
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//#define MEMORY_TEST_REG (0x2d << MEM_MAP_SHIFT)
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/** Hit Threshold register */
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//#define HIT_THRESHOLD_REG (0x2e << MEM_MAP_SHIFT)
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/** Hit Count register */
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//#define HIT_COUNT_REG (0x2f << MEM_MAP_SHIFT)
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/* 16 bit Fifo Data register */
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#define FIFO_DATA_REG (0x50 << MEM_MAP_SHIFT) // Not used in FW and SW (16bit)
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/*
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#define MOD_DACS1_REG 0x65<<11
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#define MOD_DACS2_REG 0x66<<11
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#define MOD_DACS3_REG 0x67<<11
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*/
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/** Dacs Set 1 register */
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//#define DACS_SET_1_REG (0x65 << MEM_MAP_SHIFT)
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/** Dacs Set 2 register */
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//#define DACS_SET_2_REG (0x66 << MEM_MAP_SHIFT)
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/** Dacs Set 3 register */
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//#define DACS_SET_3_REG (0x67 << MEM_MAP_SHIFT)
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/* Set Delay 64 bit register */
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#define SET_DELAY_LSB_REG (0x68 << MEM_MAP_SHIFT)
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#define SET_DELAY_MSB_REG (0x69 << MEM_MAP_SHIFT)
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@ -314,8 +351,12 @@
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#define GET_EXPTIME_MSB_REG (0x7b << MEM_MAP_SHIFT)
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/* Set Gates 64 bit register */
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//#define SET_GATES_LSB_REG (0x7c << MEM_MAP_SHIFT) // Not used in SW and FW
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//#define SET_GATES_MSB_REG (0x7d << MEM_MAP_SHIFT) // Not used in SW and FW
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//#define SET_GATES_LSB_REG (0x7c << MEM_MAP_SHIFT)
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//#define SET_GATES_MSB_REG (0x7d << MEM_MAP_SHIFT)
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/* Set Gates 64 bit register */
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//#define GET_GATES_LSB_REG (0x7e << MEM_MAP_SHIFT)
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//#define GET_GATES_MSB_REG (0x7f << MEM_MAP_SHIFT)
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/* Dark Image starting address */
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#define DARK_IMAGE_REG (0x81 << MEM_MAP_SHIFT)
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@ -6,6 +6,7 @@
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#ifndef VIRTUAL
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#include "AD9257.h" // commonServerFunctions.h, blackfin.h, ansi.h
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#include "AD9252.h" // old board compatibility
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#else
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#include "blackfin.h"
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#include <pthread.h>
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@ -371,11 +372,14 @@ void setupDetector() {
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// Initialization
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setPhaseShiftOnce();
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//prepareADC(); /* TODO: check if need to replace with configureADC from firmwarE_funcs.c? */
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if (getBoardRevision() == 1)
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prepareADC9252(); /* FIXME: (also check with commenting out #define GOTTHARDD in ad9257.h), check if need to replace with configureADC from firmwarE_funcs.c? */
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else
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prepareADC9257();
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configureADC();
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setROIADC(-1); // set adcsyncreg, daqreg, chipofinterestreg, cleanfifos,
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setGbitReadout();
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//initDac(0); /*FIXME: if it doesnt work, switch to the old dac*/
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initDac(0); /*FIXME: if it doesnt work, switch to the old dac*/
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// master, slave (25um)
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setMasterSlaveConfiguration();
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@ -1123,6 +1127,29 @@ enum detectorSettings getSettings(){
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/* parameters - dac, adc, hv */
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void initDac(int dacnum) { // FIXME: if needed
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#ifdef VIRTUAL
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return;
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#endif
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FILE_LOG(logINFOBLUE, ("Initializing dac %d\n",dacnum));
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u_int32_t codata;
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int csdx = dacnum / NDAC + DAC_CNTRL_CS_OFST; // old board (16 dacs),so can be DAC_SERIAL_CS_OUT_OFST or +1
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int dacchannel = 0xf; // all channels
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int dacvalue = 0x6; // can be any random value (just writing to power up)
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FILE_LOG(logINFO, ("\tWrite to Input Register\n"
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"\tChip select bit: %d\n"
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"\tDac Channel: 0x%x\n"
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"\tDac Value: 0x%x\n",
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csdx, dacchannel, dacvalue));
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codata = LTC2620_DAC_CMD_WRITE + // command to write to input register
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((dacchannel << LTC2620_DAC_ADDR_OFST) & LTC2620_DAC_ADDR_MSK) + // all channels
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((dacvalue << LTC2620_DAC_DATA_OFST) & LTC2620_DAC_DATA_MSK); // any random value
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serializeToSPI(DAC_CNTRL_REG, codata, (0x1 << csdx), LTC2620_DAC_NUMBITS,
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DAC_CNTRL_CLK_MSK, DAQ_CNTRL_DGTL_MSK, DAQ_CNTRL_DGTL_OFST);
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}
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int voltageToDac(int value){
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int vmin = 0;
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int vmax = 2500;
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@ -1146,7 +1173,62 @@ int dacToVoltage(unsigned int digital){
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return v;
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}
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void setDAC(enum DACINDEX ind, int val, int mV, int retval[]){
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void setDAC(enum DACINDEX ind, int val, int mV, int retval[]) {
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int dacmV = val;
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//if set and mv, convert to dac
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if (val > 0) {
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if (mV)
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val = voltageToDac(val); //gives -1 on error
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else
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dacmV = dacToVoltage(val); //gives -1 on error
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}
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if ( (val >= 0) || (val == -100)) {
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#ifdef VIRTUAL
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dacValues[ind] = val;
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#else
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u_int32_t codata;
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int csdx = ind / NDAC + DAC_CNTRL_CS_MSK; // old board (16 dacs),so can be DAC_SERIAL_CS_OUT_OFST or +1
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int dacchannel = ind % NDAC; // 0-8, dac channel number (also for dacnum 9-15 in old board)
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FILE_LOG(logINFO, ("Setting DAC %d: %d dac (%d mV)\n",ind, val, dacmV));
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// command
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if (val >= 0) {
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FILE_LOG(logDEBUG1,("\tWrite to Input Register and Update\n"));
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codata = LTC2620_DAC_CMD_SET;
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} else if (val == -100) {
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FILE_LOG(logDEBUG1, ("\tPOWER DOWN\n"));
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codata = LTC2620_DAC_CMD_POWER_DOWN;
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}
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// address
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FILE_LOG(logDEBUG1, ("\tChip select bit:%d\n"
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"\tDac Channel:0x%x\n"
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"\tDac Value:0x%x\n",
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csdx, dacchannel, val));
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codata += ((dacchannel << LTC2620_DAC_ADDR_OFST) & LTC2620_DAC_ADDR_MSK) +
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((val << LTC2620_DAC_DATA_OFST) & LTC2620_DAC_DATA_MSK);
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// to spi
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serializeToSPI(DAC_CNTRL_REG, codata, (0x1 << csdx), LTC2620_DAC_NUMBITS,
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DAC_CNTRL_CLK_MSK, DAQ_CNTRL_DGTL_MSK, DAQ_CNTRL_DGTL_OFST);
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dacValues[ind] = val;
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/* if (ind == VREF_COMP) { // FIXME:??
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bus_w (VREF_COMP_MOD_REG, (bus_r(VREF_COMP_MOD_REG) &~ (VREF_COMP_MOD_MSK)) // reset
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| ((val << VREF_COMP_MOD_OFST) & VREF_COMP_MOD_MSK)); // or it with value
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}*/
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#endif
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}
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retval[0] = dacValues[ind];
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retval[1] = dacToVoltage(retval[0]);
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FILE_LOG(logDEBUG1, ("Getting DAC %d : %d dac (%d mV)\n",ind, retval[0], retval[1]));
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}
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/*
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void setDAC(enum DACINDEX ind, int val, int mV, int retval[]) {
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int dacmV = val;
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//if set and mv, convert to dac
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@ -1235,7 +1317,7 @@ u_int32_t putout(char *s) {
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bus_w(DAC_CNTRL_REG, pat);
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return OK;
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}
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*/
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int getADC(enum ADCINDEX ind){
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#ifdef VIRTUAL
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@ -1523,8 +1605,8 @@ int configureMAC(uint32_t destip, uint64_t destmac, uint64_t sourcemac, uint32_t
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FILE_LOG(logDEBUG1, ("\tWrite back released. MultiPurpose reg: 0x%x\n", bus_r(addr)));
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// nreset phy /*FIXME: is this needed ?? */
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bus_w(addr, bus_r(addr) | ENT_RSTN_MSK);
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FILE_LOG(logDEBUG1, ("\tNreset phy. MultiPurpose reg: 0x%x\n", bus_r(addr)));
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/* bus_w(addr, bus_r(addr) | ENT_RSTN_MSK);
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FILE_LOG(logDEBUG1, ("\tNreset phy. MultiPurpose reg: 0x%x\n", bus_r(addr)));*/
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FILE_LOG(logDEBUG1, ("\tConfiguring MAC CONF\n"));
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mac_conf *mac_conf_regs = (mac_conf*)(CSP0BASE + ENET_CONF_REG * 2); // direct write
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@ -1586,7 +1668,8 @@ int configureMAC(uint32_t destip, uint64_t destmac, uint64_t sourcemac, uint32_t
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mac_conf_regs->cdone = 0xFFFFFFFF;
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// write shadow regs /* FIXME: Only INT_RSTN_MSK | WRT_BCK_MSK */
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bus_w(addr, bus_r(addr) | (INT_RSTN_MSK | ENT_RSTN_MSK| WRT_BCK_MSK));
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/*bus_w(addr, bus_r(addr) | (INT_RSTN_MSK | ENT_RSTN_MSK| WRT_BCK_MSK));*/
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bus_w(addr, bus_r(addr) | (INT_RSTN_MSK | WRT_BCK_MSK));
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FILE_LOG(logDEBUG1, ("\tWrite shadow regs with int reset. MultiPurpose reg: 0x%x\n", bus_r(addr)));
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usleep(100000);
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@ -1596,7 +1679,8 @@ int configureMAC(uint32_t destip, uint64_t destmac, uint64_t sourcemac, uint32_t
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FILE_LOG(logDEBUG1, ("\tWrite back released. MultiPurpose reg: 0x%x\n", bus_r(addr)));
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// sw1 /* FIXME: Only SW1_MSK */
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bus_w(addr, bus_r(addr) | (INT_RSTN_MSK | ENT_RSTN_MSK | SW1_MSK));
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/*bus_w(addr, bus_r(addr) | (INT_RSTN_MSK | ENT_RSTN_MSK | SW1_MSK));*/
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bus_w(addr, bus_r(addr) | SW1_MSK);
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FILE_LOG(logDEBUG1, ("\tSw1. MultiPurpose reg: 0x%x\n", bus_r(addr)));
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usleep(1000 * 1000);
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@ -51,6 +51,19 @@ enum DACINDEX {VREF_DS, VCASCN_PB, VCASCP_PB, VOUT_CM, VCASC_OUT, VIN
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#define DEFAULT_PHASE_SHIFT (120)
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#define DEFAULT_TX_UDP_PORT (0xE185)
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/* LTC2620 DAC DEFINES *///FIXME: if neeeded
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#define LTC2620_DAC_CMD_OFST (20)
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#define LTC2620_DAC_CMD_MSK (0x0000000F << LTC2620_DAC_CMD_OFST)
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#define LTC2620_DAC_ADDR_OFST (16)
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#define LTC2620_DAC_ADDR_MSK (0x0000000F << LTC2620_DAC_ADDR_OFST)
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#define LTC2620_DAC_DATA_OFST (4)
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#define LTC2620_DAC_DATA_MSK (0x00000FFF << LTC2620_DAC_DATA_OFST)
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#define LTC2620_DAC_CMD_WRITE (0x00000000 << LTC2620_DAC_CMD_OFST)
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#define LTC2620_DAC_CMD_SET (0x00000003 << LTC2620_DAC_CMD_OFST)
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#define LTC2620_DAC_CMD_POWER_DOWN (0x00000004 << LTC2620_DAC_CMD_OFST)
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#define LTC2620_DAC_NUMBITS (24)
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/** ENEt conf structs */
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typedef struct mac_header_struct{
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u_int8_t mac_dest_mac2;
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