* ctb, moench and jungfrau: pll reset at start not happening as no defines
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Dhanya Thattil 2022-09-29 14:03:26 +02:00 committed by GitHub
parent bac32dcba9
commit d9e34e1657
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8 changed files with 22 additions and 20 deletions

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@ -100,6 +100,7 @@ This document describes the differences between v7.0.0 and v6.x.x
- jungfrau reset core and usleep removed (fix for 6.1.1 is now fixed in firmware)
- g2 change clkdivs 2 3 4 to defaults for burst and cw mode.
- ctb and moench: allowing 1g non blocking acquire to send data
- ctb, moench, jungfrau (pll reset at start fixed, before no defines)
2. Resolved Issues
==================

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@ -488,7 +488,13 @@ void setupDetector() {
#endif
setupUDPCommParameters();
// altera pll
ALTERA_PLL_SetDefines(PLL_CNTRL_REG, PLL_PARAM_REG,
PLL_CNTRL_RCNFG_PRMTR_RST_MSK, PLL_CNTRL_WR_PRMTR_MSK,
PLL_CNTRL_PLL_RST_MSK, PLL_CNTRL_ADDR_MSK,
PLL_CNTRL_ADDR_OFST);
ALTERA_PLL_ResetPLLAndReconfiguration();
resetCore();
resetPeripheral();
cleanFifos();
@ -548,12 +554,6 @@ void setupDetector() {
INA226_CalibrateCurrentRegister(I2C_POWER_VD_DEVICE_ID);
setVchip(VCHIP_MIN_MV);
// altera pll
ALTERA_PLL_SetDefines(PLL_CNTRL_REG, PLL_PARAM_REG,
PLL_CNTRL_RCNFG_PRMTR_RST_MSK, PLL_CNTRL_WR_PRMTR_MSK,
PLL_CNTRL_PLL_RST_MSK, PLL_CNTRL_ADDR_MSK,
PLL_CNTRL_ADDR_OFST);
setADCInvertRegister(0); // depends on chip
LOG(logINFOBLUE, ("Setting Default parameters\n"));

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@ -428,7 +428,13 @@ void setupDetector() {
setupUDPCommParameters();
#endif
// altera pll
ALTERA_PLL_SetDefines(
PLL_CNTRL_REG, PLL_PARAM_REG, PLL_CNTRL_RCNFG_PRMTR_RST_MSK,
PLL_CNTRL_WR_PRMTR_MSK, PLL_CNTRL_PLL_RST_MSK, PLL_CNTRL_ADDR_MSK,
PLL_CNTRL_ADDR_OFST, PLL_CNTRL_DBIT_WR_PRMTR_MSK, DBIT_CLK_INDEX);
ALTERA_PLL_ResetPLL();
resetCore();
resetPeripheral();
cleanFifos();
@ -456,12 +462,6 @@ void setupDetector() {
LTC2620_Configure();
resetToDefaultDacs(0);
// altera pll
ALTERA_PLL_SetDefines(
PLL_CNTRL_REG, PLL_PARAM_REG, PLL_CNTRL_RCNFG_PRMTR_RST_MSK,
PLL_CNTRL_WR_PRMTR_MSK, PLL_CNTRL_PLL_RST_MSK, PLL_CNTRL_ADDR_MSK,
PLL_CNTRL_ADDR_OFST, PLL_CNTRL_DBIT_WR_PRMTR_MSK, DBIT_CLK_INDEX);
/* Only once at server startup */
bus_w(DAQ_REG, 0x0);

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@ -503,7 +503,13 @@ void setupDetector() {
#endif
setupUDPCommParameters();
// altera pll
ALTERA_PLL_SetDefines(PLL_CNTRL_REG, PLL_PARAM_REG,
PLL_CNTRL_RCNFG_PRMTR_RST_MSK, PLL_CNTRL_WR_PRMTR_MSK,
PLL_CNTRL_PLL_RST_MSK, PLL_CNTRL_ADDR_MSK,
PLL_CNTRL_ADDR_OFST);
ALTERA_PLL_ResetPLLAndReconfiguration();
resetCore();
resetPeripheral();
cleanFifos();
@ -536,11 +542,6 @@ void setupDetector() {
LTC2620_Configure();
resetToDefaultDacs(0);
// altera pll
ALTERA_PLL_SetDefines(PLL_CNTRL_REG, PLL_PARAM_REG,
PLL_CNTRL_RCNFG_PRMTR_RST_MSK, PLL_CNTRL_WR_PRMTR_MSK,
PLL_CNTRL_PLL_RST_MSK, PLL_CNTRL_ADDR_MSK,
PLL_CNTRL_ADDR_OFST);
// not using setADCInvertRegister command (as it xors the default)
bus_w(ADC_PORT_INVERT_REG, ADC_PORT_INVERT_VAL);

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@ -5,10 +5,10 @@
#define APILIB 0x220609
#define APIRECEIVER 0x220609
#define APIGUI 0x220609
#define APICTB 0x220916
#define APIGOTTHARD 0x220916
#define APIGOTTHARD2 0x220916
#define APIJUNGFRAU 0x220916
#define APIMYTHEN3 0x220916
#define APIMOENCH 0x220916
#define APIEIGER 0x220916
#define APICTB 0x220929
#define APIMOENCH 0x220929
#define APIJUNGFRAU 0x220929