mirror of
https://github.com/slsdetectorgroup/slsDetectorPackage.git
synced 2026-08-06 11:22:26 +02:00
minor refactoring
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@@ -368,6 +368,9 @@
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#define DAQ_CMP_RST_MSK (0x00000001 << DAQ_CMP_RST_OFST)
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#define DAQ_CHIP_VRSN_OFST (5)
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#define DAQ_CHIP_VRSN_MSK (0x00000007 << DAQ_CHIP_VRSN_OFST)
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#define DAQ_CHIP_VRSN_v1_0_VAL (0x0)
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#define DAQ_CHIP_VRSN_v1_1_VAL (0x1)
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#define DAQ_CHIP_VRSN_v1_2_VAL (0x2)
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#define DAQ_STRG_CELL_SLCT_OFST (8)
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#define DAQ_STRG_CELL_SLCT_MSK (0x0000000F << DAQ_STRG_CELL_SLCT_OFST)
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#define DAQ_FRCE_SWTCH_GAIN_OFST (12)
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@@ -372,7 +372,6 @@ int setChipVersionIntFromConfigFile(int val, char *mess) {
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}
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int setChipVersionStringFromConfigFile(char *cval, char *mess) {
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enum CHIPINDEX ind = NUM_CHIP_INDICES;
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if (findChipIndex(&ind, cval, mess) == FAIL) {
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return FAIL;
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@@ -409,21 +408,21 @@ int validateChipIndex(enum CHIPINDEX ind, char *mess) {
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}
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int setChipVersionInFPGA(char *mess) {
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int val = 0;
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uint32_t val = 0;
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switch (chipIndex) {
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case v1_0:
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LOG(logINFO, ("Setting Chip Version 1.0 in FPGA\n"));
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val = 0;
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val = DAQ_CHIP_VRSN_v1_0_VAL;
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break;
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case v1_1:
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LOG(logINFO, ("Setting Chip Version 1.1 in FPGA\n"));
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val = 1;
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val = DAQ_CHIP_VRSN_v1_1_VAL;
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break;
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case v1_2_NORMAL:
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case v1_2_LOW_NOISE:
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case v1_2_HDR:
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LOG(logINFO, ("Setting Chip Version 1.2 in FPGA\n"));
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val = 2;
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val = DAQ_CHIP_VRSN_v1_2_VAL;
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break;
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default:
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sprintf(mess, "Unknown chip index %d\n", (int)chipIndex);
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