minor refactoring
Build on RHEL9 / build (push) Failing after 3m0s
Build on RHEL8 / build (push) Failing after 4m50s

This commit is contained in:
2026-07-30 00:02:00 +02:00
parent f9ee8f9cda
commit d5bf77ee19
2 changed files with 7 additions and 5 deletions
@@ -368,6 +368,9 @@
#define DAQ_CMP_RST_MSK (0x00000001 << DAQ_CMP_RST_OFST)
#define DAQ_CHIP_VRSN_OFST (5)
#define DAQ_CHIP_VRSN_MSK (0x00000007 << DAQ_CHIP_VRSN_OFST)
#define DAQ_CHIP_VRSN_v1_0_VAL (0x0)
#define DAQ_CHIP_VRSN_v1_1_VAL (0x1)
#define DAQ_CHIP_VRSN_v1_2_VAL (0x2)
#define DAQ_STRG_CELL_SLCT_OFST (8)
#define DAQ_STRG_CELL_SLCT_MSK (0x0000000F << DAQ_STRG_CELL_SLCT_OFST)
#define DAQ_FRCE_SWTCH_GAIN_OFST (12)
@@ -372,7 +372,6 @@ int setChipVersionIntFromConfigFile(int val, char *mess) {
}
int setChipVersionStringFromConfigFile(char *cval, char *mess) {
enum CHIPINDEX ind = NUM_CHIP_INDICES;
if (findChipIndex(&ind, cval, mess) == FAIL) {
return FAIL;
@@ -409,21 +408,21 @@ int validateChipIndex(enum CHIPINDEX ind, char *mess) {
}
int setChipVersionInFPGA(char *mess) {
int val = 0;
uint32_t val = 0;
switch (chipIndex) {
case v1_0:
LOG(logINFO, ("Setting Chip Version 1.0 in FPGA\n"));
val = 0;
val = DAQ_CHIP_VRSN_v1_0_VAL;
break;
case v1_1:
LOG(logINFO, ("Setting Chip Version 1.1 in FPGA\n"));
val = 1;
val = DAQ_CHIP_VRSN_v1_1_VAL;
break;
case v1_2_NORMAL:
case v1_2_LOW_NOISE:
case v1_2_HDR:
LOG(logINFO, ("Setting Chip Version 1.2 in FPGA\n"));
val = 2;
val = DAQ_CHIP_VRSN_v1_2_VAL;
break;
default:
sprintf(mess, "Unknown chip index %d\n", (int)chipIndex);