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https://github.com/slsdetectorgroup/slsDetectorPackage.git
synced 2025-06-21 00:58:01 +02:00
jungfrau server: changes for new firmware, aligning adc deserializer. ctb serveR: removed unnecessary pll reset and polling mode for pll
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@ -205,13 +205,8 @@ void AD9257_Configure(){
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AD9257_Set(AD9257_OUT_MODE_REG, AD9257_OUT_BINARY_OFST_VAL);
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//output clock phase
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//if defined(GOTTHARDD) || defined(JUNGFRAUD)
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#ifdef GOTTHARDD
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#if defined(GOTTHARDD) || defined(JUNGFRAUD)
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FILE_LOG(logINFO, ("\tOutput clock phase is at default: 180\n"));
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#elif JUNGFRAUD
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// This is not required (by default it is 180) (like gotthard)
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FILE_LOG(logINFO, ("\tOutput clock phase: 180\n"));
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AD9257_Set(AD9257_OUT_PHASE_REG, AD9257_OUT_CLK_180_VAL);
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#else
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FILE_LOG(logINFO, ("\tOutput clock phase: 60\n"));
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AD9257_Set(AD9257_OUT_PHASE_REG, AD9257_OUT_CLK_60_VAL);
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@ -225,9 +225,6 @@ int ALTERA_PLL_SetOuputFrequency (int clkIndex, int pllVCOFreqMhz, int value) {
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// write frequency (post-scale output counter C)
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ALTERA_PLL_SetPllReconfigReg(ALTERA_PLL_C_COUNTER_REG, val);
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// reset only PLL
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ALTERA_PLL_ResetPLL();
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return (pllVCOFreqMhz / (low_count + high_count));
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}
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@ -280,7 +280,7 @@ extern void eraseFlash(); // programfpga.h
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extern int startWritingFPGAprogram(FILE** filefp); // programfpga.h
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extern void stopWritingFPGAprogram(FILE* filefp); // programfpga.h
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extern int writeFPGAProgram(char* fpgasrc, size_t fsize, FILE* filefp); // programfpga.h
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void setUnknowns();
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void alignDeserializer();
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// eiger specific - iodelay, pulse, rate, temp, activate, delay nw parameter
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#elif EIGERD
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