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jungfrau server: changes for new firmware, aligning adc deserializer. ctb serveR: removed unnecessary pll reset and polling mode for pll

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This commit is contained in:
maliakal_d 2019-03-22 15:09:29 +01:00
parent 5bf37a4f0d
commit cd5aea895b
11 changed files with 45 additions and 66 deletions
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10
slsDetectorServers/ctbDetectorServer/gitInfo.txt
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@ -1,9 +1,9 @@
Path: slsDetectorPackage/slsDetectorServers/ctbDetectorServer
URL: origin git@github.com:slsdetectorgroup/slsDetectorPackage.git
Repository Root: origin git@github.com:slsdetectorgroup/slsDetectorPackage.git
Repsitory UUID: 050854de36f01379e974005e204b6563ffbc7004
Revision: 43
Branch: refactor
Repsitory UUID: 5bf37a4f0d840820e676f11419e98c0203d700eb
Revision: 44
Branch: jungfrau
Last Changed Author: Dhanya_Thattil
Last Changed Rev: 4458
Last Changed Date: 2019-03-21 14:00:57.000000002 +0100 ../slsDetectorServer/ALTERA_PLL.h
Last Changed Rev: 4472
Last Changed Date: 2019-03-22 14:25:24.000000002 +0100 ../slsDetectorServer/ALTERA_PLL.h

8
slsDetectorServers/ctbDetectorServer/gitInfoCtb.h
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@ -1,6 +1,6 @@
#define GITURL "git@github.com:slsdetectorgroup/slsDetectorPackage.git"
#define GITREPUUID "050854de36f01379e974005e204b6563ffbc7004"
#define GITREPUUID "5bf37a4f0d840820e676f11419e98c0203d700eb"
#define GITAUTH "Dhanya_Thattil"
#define GITREV 0x4458
#define GITDATE 0x20190321
#define GITBRANCH "refactor"
#define GITREV 0x4472
#define GITDATE 0x20190322
#define GITBRANCH "jungfrau"

9
slsDetectorServers/ctbDetectorServer/slsDetectorFunctionList.c
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@ -822,7 +822,7 @@ int getSpeed(enum speedVariable ind) {
switch(ind) {
case ADC_PHASE:
case PHASE_SHIFT:
return getPhase(RUN_CLK);
return getPhase(ADC_CLK);
case DBIT_PHASE:
return getPhase(DBIT_CLK);
case ADC_CLOCK:
@ -1648,13 +1648,6 @@ void configurePhase(enum CLKINDEX ind, int val) {
FILE_LOG(logINFO, ("Configuring Phase of C%d(%s) to %d\n", ind, clock_names[ind], val));
// reset only pll
ALTERA_PLL_ResetPLL();
// set mode register to polling mode
ALTERA_PLL_SetModePolling();
int phase = 0;
int maxShifts = ((ind == ADC_CLK) ? MAX_PHASE_SHIFTS_ADC_CLK : MAX_PHASE_SHIFTS_DBIT_CLK);

2
slsDetectorServers/ctbDetectorServer/slsDetectorServer_defs.h
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@ -52,7 +52,7 @@ enum DACINDEX {D0, D1, D2, D3, D4, D5, D6, D7, D8, D9,
/** Default Parameters */
#define DEFAULT_DATA_BYTES (NCHIP * NCHAN * NUM_BITS_PER_PIXEL)
#define DEFAULT_NUM_SAMPLES (1)
#define DEFAULT_NUM_FRAMES (100 * 1000 * 1000)
#define DEFAULT_NUM_FRAMES (1)
#define DEFAULT_EXPTIME (0)
#define DEFAULT_NUM_CYCLES (1)
#define DEFAULT_PERIOD (1 * 1000 * 1000) //ns

34
slsDetectorServers/jungfrauDetectorServer/RegisterDefs.h
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@ -250,7 +250,7 @@
#define PLL_CNTRL_ADDR_OFST (16)
#define PLL_CNTRL_ADDR_MSK (0x0000003F << PLL_CNTRL_ADDR_OFST)
/* Sample Register (Obsolete) FIXME: what is it now? */
/* Sample Register */
#define SAMPLE_REG (0x59 << MEM_MAP_SHIFT)
#define SAMPLE_ADC_SAMPLE_SEL_OFST (0)
@ -417,25 +417,25 @@
/* FIXME UNKNOWN 0 */
#define UNKNOWN_0_REG (0xF0 << MEM_MAP_SHIFT)
#define UNKNOWN_0_UNKNOWN_OFST (31)
#define UNKNOWN_0_UNKNOWN_MSK (0x00000001 << UNKNOWN_0_UNKNOWN_OFST)
/* ADC 0 Deserializer Control */
#define ADC_DSRLZR_0_REG (0xF0 << MEM_MAP_SHIFT)
#define ADC_DSRLZR_0_RFRSH_ALGNMNT_OFST (31) /* Refresh alignment */
#define ADC_DSRLZR_0_RFRSH_ALGNMNT_MSK (0x00000001 << ADC_DSRLZR_0_RFRSH_ALGNMNT_OFST)
/* FIXME UNKNOWN 1 */
#define UNKNOWN_1_REG (0xF1 << MEM_MAP_SHIFT)
#define UNKNOWN_1_UNKNOWN_OFST (31)
#define UNKNOWN_1_UNKNOWN_MSK (0x00000001 << UNKNOWN_1_UNKNOWN_OFST)
/* ADC 0 Deserializer Control */
#define ADC_DSRLZR_1_REG (0xF1 << MEM_MAP_SHIFT)
#define ADC_DSRLZR_1_RFRSH_ALGNMNT_OFST (31)
#define ADC_DSRLZR_1_RFRSH_ALGNMNT_MSK (0x00000001 << ADC_DSRLZR_1_RFRSH_ALGNMNT_OFST)
/* FIXME UNKNOWN 2 */
#define UNKNOWN_2_REG (0xF2 << MEM_MAP_SHIFT)
#define UNKNOWN_2_UNKNOWN_OFST (31)
#define UNKNOWN_2_UNKNOWN_MSK (0x00000001 << UNKNOWN_2_UNKNOWN_OFST)
/* ADC 0 Deserializer Control */
#define ADC_DSRLZR_2_REG (0xF2 << MEM_MAP_SHIFT)
#define ADC_DSRLZR_2_RFRSH_ALGNMNT_OFST (31)
#define ADC_DSRLZR_2_RFRSH_ALGNMNT_MSK (0x00000001 << ADC_DSRLZR_2_RFRSH_ALGNMNT_OFST)
/* FIXME UNKNOWN 3 */
#define UNKNOWN_3_REG (0xF3 << MEM_MAP_SHIFT)
#define UNKNOWN_3_UNKNOWN_OFST (31)
#define UNKNOWN_3_UNKNOWN_MSK (0x00000001 << UNKNOWN_3_UNKNOWN_OFST)
/* ADC 0 Deserializer Control */
#define ADC_DSRLZR_3_REG (0xF3 << MEM_MAP_SHIFT)
#define ADC_DSRLZR_3_RFRSH_ALGNMNT_OFST (31)
#define ADC_DSRLZR_3_RFRSH_ALGNMNT_MSK (0x00000001 << ADC_DSRLZR_3_RFRSH_ALGNMNT_OFST)

32
slsDetectorServers/jungfrauDetectorServer/slsDetectorFunctionList.c
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@ -424,7 +424,7 @@ void setupDetector() {
cleanFifos();
resetCore();
setUnknowns();
alignDeserializer();
configureASICTimer();
@ -489,8 +489,6 @@ void resetCore() {
FILE_LOG(logINFO, ("Resetting Core\n"));
bus_w(CONTROL_REG, bus_r(CONTROL_REG) | CONTROL_CORE_RST_MSK);
bus_w(CONTROL_REG, bus_r(CONTROL_REG) & ~CONTROL_CORE_RST_MSK);
//FIXME: usleep required??
usleep(1000 * 1000);
}
@ -1085,11 +1083,7 @@ int configureMAC(uint32_t destip, uint64_t destmac, uint64_t sourcemac, uint32_t
FILE_LOG(logDEBUG1, ("Read from TX_IP_CHECKSUM_REG: 0x%08x\n", bus_r(TX_IP_CHECKSUM_REG)));
cleanFifos();
resetCore();
//FIXME: usleep(500 * 1000); /* todo maybe without */
usleep(1000 * 1000);
setUnknowns();
alignDeserializer();
return OK;
}
@ -1342,20 +1336,20 @@ int setTemperatureEvent(int val) {
return ((bus_r(TEMP_CTRL_REG) & TEMP_CTRL_OVR_TMP_EVNT_MSK) >> TEMP_CTRL_OVR_TMP_EVNT_OFST);
}
void setUnknowns() {
// set unknowns
bus_w(UNKNOWN_0_REG, bus_r(UNKNOWN_0_REG) | UNKNOWN_0_UNKNOWN_MSK);
bus_w(UNKNOWN_1_REG, bus_r(UNKNOWN_1_REG) | UNKNOWN_1_UNKNOWN_MSK);
bus_w(UNKNOWN_2_REG, bus_r(UNKNOWN_2_REG) | UNKNOWN_2_UNKNOWN_MSK);
bus_w(UNKNOWN_3_REG, bus_r(UNKNOWN_3_REG) | UNKNOWN_3_UNKNOWN_MSK);
void alignDeserializer() {
// refresh alignment
bus_w(ADC_DSRLZR_0_REG, bus_r(ADC_DSRLZR_0_REG) | ADC_DSRLZR_0_RFRSH_ALGNMNT_MSK);
bus_w(ADC_DSRLZR_1_REG, bus_r(ADC_DSRLZR_1_REG) | ADC_DSRLZR_1_RFRSH_ALGNMNT_MSK);
bus_w(ADC_DSRLZR_2_REG, bus_r(ADC_DSRLZR_2_REG) | ADC_DSRLZR_2_RFRSH_ALGNMNT_MSK);
bus_w(ADC_DSRLZR_3_REG, bus_r(ADC_DSRLZR_3_REG) | ADC_DSRLZR_3_RFRSH_ALGNMNT_MSK);
usleep(1 * 1000 * 1000);
// reset unknowns
bus_w(UNKNOWN_0_REG, bus_r(UNKNOWN_0_REG) & (~(UNKNOWN_0_UNKNOWN_MSK)));
bus_w(UNKNOWN_1_REG, bus_r(UNKNOWN_1_REG) & (~(UNKNOWN_1_UNKNOWN_MSK)));
bus_w(UNKNOWN_2_REG, bus_r(UNKNOWN_2_REG) & (~(UNKNOWN_2_UNKNOWN_MSK)));
bus_w(UNKNOWN_3_REG, bus_r(UNKNOWN_3_REG) & (~(UNKNOWN_3_UNKNOWN_MSK)));
// disable the refresh
bus_w(ADC_DSRLZR_0_REG, bus_r(ADC_DSRLZR_0_REG) & (~(ADC_DSRLZR_0_RFRSH_ALGNMNT_MSK)));
bus_w(ADC_DSRLZR_1_REG, bus_r(ADC_DSRLZR_1_REG) & (~(ADC_DSRLZR_1_RFRSH_ALGNMNT_MSK)));
bus_w(ADC_DSRLZR_2_REG, bus_r(ADC_DSRLZR_2_REG) & (~(ADC_DSRLZR_2_RFRSH_ALGNMNT_MSK)));
bus_w(ADC_DSRLZR_3_REG, bus_r(ADC_DSRLZR_3_REG) & (~(ADC_DSRLZR_3_RFRSH_ALGNMNT_MSK)));
}

2
slsDetectorServers/jungfrauDetectorServer/slsDetectorServer_defs.h
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@ -85,7 +85,7 @@ enum NETWORKINDEX { TXN_FRAME };
#define CONFIG_QUARTER_SPEED (CONFIG_TDMA_DISABLE_VAL + CONFIG_QUARTER_SPEED_10MHZ_VAL + CONFIG_OPRTN_MDE_1_X_10GBE_VAL)
#define ADC_OFST_HALF_SPEED_VAL (0x20)//(0x1f) //(0x20)
#define ADC_OFST_QUARTER_SPEED_VAL (0x0f) //(0x0f)
#define ADC_PHASE_HALF_SPEED (0x28)//(0x2D) //45
#define ADC_PHASE_HALF_SPEED (0x2D) //45
#define ADC_PHASE_QUARTER_SPEED (0x2D) //45
#define ADC_PORT_INVERT_VAL (0x5A5A5A5A)//(0x453b2a9c)
#define MAX_PHASE_SHIFTS (160)

2
slsDetectorServers/moenchDetectorServer/slsDetectorFunctionList.c
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@ -798,7 +798,7 @@ int getSpeed(enum speedVariable ind) {
switch(ind) {
case ADC_PHASE:
case PHASE_SHIFT:
return getPhase(RUN_CLK);
return getPhase(ADC_CLK);
case DBIT_PHASE:
return getPhase(DBIT_CLK);
case ADC_CLOCK:

7
slsDetectorServers/slsDetectorServer/AD9257.h
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@ -205,13 +205,8 @@ void AD9257_Configure(){
AD9257_Set(AD9257_OUT_MODE_REG, AD9257_OUT_BINARY_OFST_VAL);
//output clock phase
//if defined(GOTTHARDD) || defined(JUNGFRAUD)
#ifdef GOTTHARDD
#if defined(GOTTHARDD) || defined(JUNGFRAUD)
FILE_LOG(logINFO, ("\tOutput clock phase is at default: 180\n"));
#elif JUNGFRAUD
// This is not required (by default it is 180) (like gotthard)
FILE_LOG(logINFO, ("\tOutput clock phase: 180\n"));
AD9257_Set(AD9257_OUT_PHASE_REG, AD9257_OUT_CLK_180_VAL);
#else
FILE_LOG(logINFO, ("\tOutput clock phase: 60\n"));
AD9257_Set(AD9257_OUT_PHASE_REG, AD9257_OUT_CLK_60_VAL);

3
slsDetectorServers/slsDetectorServer/ALTERA_PLL.h
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@ -225,9 +225,6 @@ int ALTERA_PLL_SetOuputFrequency (int clkIndex, int pllVCOFreqMhz, int value) {
// write frequency (post-scale output counter C)
ALTERA_PLL_SetPllReconfigReg(ALTERA_PLL_C_COUNTER_REG, val);
// reset only PLL
ALTERA_PLL_ResetPLL();
return (pllVCOFreqMhz / (low_count + high_count));
}

2
slsDetectorServers/slsDetectorServer/slsDetectorFunctionList.h
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@ -280,7 +280,7 @@ extern void eraseFlash(); // programfpga.h
extern int startWritingFPGAprogram(FILE** filefp); // programfpga.h
extern void stopWritingFPGAprogram(FILE* filefp); // programfpga.h
extern int writeFPGAProgram(char* fpgasrc, size_t fsize, FILE* filefp); // programfpga.h
void setUnknowns();
void alignDeserializer();
// eiger specific - iodelay, pulse, rate, temp, activate, delay nw parameter
#elif EIGERD