mirror of
https://github.com/slsdetectorgroup/slsDetectorPackage.git
synced 2025-06-19 16:27:13 +02:00
jungfrau server: changes for new firmware, aligning adc deserializer. ctb serveR: removed unnecessary pll reset and polling mode for pll
This commit is contained in:
@ -250,7 +250,7 @@
|
||||
#define PLL_CNTRL_ADDR_OFST (16)
|
||||
#define PLL_CNTRL_ADDR_MSK (0x0000003F << PLL_CNTRL_ADDR_OFST)
|
||||
|
||||
/* Sample Register (Obsolete) FIXME: what is it now? */
|
||||
/* Sample Register */
|
||||
#define SAMPLE_REG (0x59 << MEM_MAP_SHIFT)
|
||||
|
||||
#define SAMPLE_ADC_SAMPLE_SEL_OFST (0)
|
||||
@ -417,25 +417,25 @@
|
||||
|
||||
|
||||
|
||||
/* FIXME UNKNOWN 0 */
|
||||
#define UNKNOWN_0_REG (0xF0 << MEM_MAP_SHIFT)
|
||||
#define UNKNOWN_0_UNKNOWN_OFST (31)
|
||||
#define UNKNOWN_0_UNKNOWN_MSK (0x00000001 << UNKNOWN_0_UNKNOWN_OFST)
|
||||
/* ADC 0 Deserializer Control */
|
||||
#define ADC_DSRLZR_0_REG (0xF0 << MEM_MAP_SHIFT)
|
||||
#define ADC_DSRLZR_0_RFRSH_ALGNMNT_OFST (31) /* Refresh alignment */
|
||||
#define ADC_DSRLZR_0_RFRSH_ALGNMNT_MSK (0x00000001 << ADC_DSRLZR_0_RFRSH_ALGNMNT_OFST)
|
||||
|
||||
/* FIXME UNKNOWN 1 */
|
||||
#define UNKNOWN_1_REG (0xF1 << MEM_MAP_SHIFT)
|
||||
#define UNKNOWN_1_UNKNOWN_OFST (31)
|
||||
#define UNKNOWN_1_UNKNOWN_MSK (0x00000001 << UNKNOWN_1_UNKNOWN_OFST)
|
||||
/* ADC 0 Deserializer Control */
|
||||
#define ADC_DSRLZR_1_REG (0xF1 << MEM_MAP_SHIFT)
|
||||
#define ADC_DSRLZR_1_RFRSH_ALGNMNT_OFST (31)
|
||||
#define ADC_DSRLZR_1_RFRSH_ALGNMNT_MSK (0x00000001 << ADC_DSRLZR_1_RFRSH_ALGNMNT_OFST)
|
||||
|
||||
/* FIXME UNKNOWN 2 */
|
||||
#define UNKNOWN_2_REG (0xF2 << MEM_MAP_SHIFT)
|
||||
#define UNKNOWN_2_UNKNOWN_OFST (31)
|
||||
#define UNKNOWN_2_UNKNOWN_MSK (0x00000001 << UNKNOWN_2_UNKNOWN_OFST)
|
||||
/* ADC 0 Deserializer Control */
|
||||
#define ADC_DSRLZR_2_REG (0xF2 << MEM_MAP_SHIFT)
|
||||
#define ADC_DSRLZR_2_RFRSH_ALGNMNT_OFST (31)
|
||||
#define ADC_DSRLZR_2_RFRSH_ALGNMNT_MSK (0x00000001 << ADC_DSRLZR_2_RFRSH_ALGNMNT_OFST)
|
||||
|
||||
/* FIXME UNKNOWN 3 */
|
||||
#define UNKNOWN_3_REG (0xF3 << MEM_MAP_SHIFT)
|
||||
#define UNKNOWN_3_UNKNOWN_OFST (31)
|
||||
#define UNKNOWN_3_UNKNOWN_MSK (0x00000001 << UNKNOWN_3_UNKNOWN_OFST)
|
||||
/* ADC 0 Deserializer Control */
|
||||
#define ADC_DSRLZR_3_REG (0xF3 << MEM_MAP_SHIFT)
|
||||
#define ADC_DSRLZR_3_RFRSH_ALGNMNT_OFST (31)
|
||||
#define ADC_DSRLZR_3_RFRSH_ALGNMNT_MSK (0x00000001 << ADC_DSRLZR_3_RFRSH_ALGNMNT_OFST)
|
||||
|
||||
|
||||
|
||||
|
@ -424,7 +424,7 @@ void setupDetector() {
|
||||
cleanFifos();
|
||||
resetCore();
|
||||
|
||||
setUnknowns();
|
||||
alignDeserializer();
|
||||
|
||||
|
||||
configureASICTimer();
|
||||
@ -489,8 +489,6 @@ void resetCore() {
|
||||
FILE_LOG(logINFO, ("Resetting Core\n"));
|
||||
bus_w(CONTROL_REG, bus_r(CONTROL_REG) | CONTROL_CORE_RST_MSK);
|
||||
bus_w(CONTROL_REG, bus_r(CONTROL_REG) & ~CONTROL_CORE_RST_MSK);
|
||||
|
||||
//FIXME: usleep required??
|
||||
usleep(1000 * 1000);
|
||||
}
|
||||
|
||||
@ -1085,11 +1083,7 @@ int configureMAC(uint32_t destip, uint64_t destmac, uint64_t sourcemac, uint32_t
|
||||
FILE_LOG(logDEBUG1, ("Read from TX_IP_CHECKSUM_REG: 0x%08x\n", bus_r(TX_IP_CHECKSUM_REG)));
|
||||
cleanFifos();
|
||||
resetCore();
|
||||
|
||||
//FIXME: usleep(500 * 1000); /* todo maybe without */
|
||||
usleep(1000 * 1000);
|
||||
|
||||
setUnknowns();
|
||||
alignDeserializer();
|
||||
return OK;
|
||||
}
|
||||
|
||||
@ -1342,20 +1336,20 @@ int setTemperatureEvent(int val) {
|
||||
return ((bus_r(TEMP_CTRL_REG) & TEMP_CTRL_OVR_TMP_EVNT_MSK) >> TEMP_CTRL_OVR_TMP_EVNT_OFST);
|
||||
}
|
||||
|
||||
void setUnknowns() {
|
||||
// set unknowns
|
||||
bus_w(UNKNOWN_0_REG, bus_r(UNKNOWN_0_REG) | UNKNOWN_0_UNKNOWN_MSK);
|
||||
bus_w(UNKNOWN_1_REG, bus_r(UNKNOWN_1_REG) | UNKNOWN_1_UNKNOWN_MSK);
|
||||
bus_w(UNKNOWN_2_REG, bus_r(UNKNOWN_2_REG) | UNKNOWN_2_UNKNOWN_MSK);
|
||||
bus_w(UNKNOWN_3_REG, bus_r(UNKNOWN_3_REG) | UNKNOWN_3_UNKNOWN_MSK);
|
||||
void alignDeserializer() {
|
||||
// refresh alignment
|
||||
bus_w(ADC_DSRLZR_0_REG, bus_r(ADC_DSRLZR_0_REG) | ADC_DSRLZR_0_RFRSH_ALGNMNT_MSK);
|
||||
bus_w(ADC_DSRLZR_1_REG, bus_r(ADC_DSRLZR_1_REG) | ADC_DSRLZR_1_RFRSH_ALGNMNT_MSK);
|
||||
bus_w(ADC_DSRLZR_2_REG, bus_r(ADC_DSRLZR_2_REG) | ADC_DSRLZR_2_RFRSH_ALGNMNT_MSK);
|
||||
bus_w(ADC_DSRLZR_3_REG, bus_r(ADC_DSRLZR_3_REG) | ADC_DSRLZR_3_RFRSH_ALGNMNT_MSK);
|
||||
|
||||
usleep(1 * 1000 * 1000);
|
||||
|
||||
// reset unknowns
|
||||
bus_w(UNKNOWN_0_REG, bus_r(UNKNOWN_0_REG) & (~(UNKNOWN_0_UNKNOWN_MSK)));
|
||||
bus_w(UNKNOWN_1_REG, bus_r(UNKNOWN_1_REG) & (~(UNKNOWN_1_UNKNOWN_MSK)));
|
||||
bus_w(UNKNOWN_2_REG, bus_r(UNKNOWN_2_REG) & (~(UNKNOWN_2_UNKNOWN_MSK)));
|
||||
bus_w(UNKNOWN_3_REG, bus_r(UNKNOWN_3_REG) & (~(UNKNOWN_3_UNKNOWN_MSK)));
|
||||
// disable the refresh
|
||||
bus_w(ADC_DSRLZR_0_REG, bus_r(ADC_DSRLZR_0_REG) & (~(ADC_DSRLZR_0_RFRSH_ALGNMNT_MSK)));
|
||||
bus_w(ADC_DSRLZR_1_REG, bus_r(ADC_DSRLZR_1_REG) & (~(ADC_DSRLZR_1_RFRSH_ALGNMNT_MSK)));
|
||||
bus_w(ADC_DSRLZR_2_REG, bus_r(ADC_DSRLZR_2_REG) & (~(ADC_DSRLZR_2_RFRSH_ALGNMNT_MSK)));
|
||||
bus_w(ADC_DSRLZR_3_REG, bus_r(ADC_DSRLZR_3_REG) & (~(ADC_DSRLZR_3_RFRSH_ALGNMNT_MSK)));
|
||||
}
|
||||
|
||||
|
||||
|
@ -85,7 +85,7 @@ enum NETWORKINDEX { TXN_FRAME };
|
||||
#define CONFIG_QUARTER_SPEED (CONFIG_TDMA_DISABLE_VAL + CONFIG_QUARTER_SPEED_10MHZ_VAL + CONFIG_OPRTN_MDE_1_X_10GBE_VAL)
|
||||
#define ADC_OFST_HALF_SPEED_VAL (0x20)//(0x1f) //(0x20)
|
||||
#define ADC_OFST_QUARTER_SPEED_VAL (0x0f) //(0x0f)
|
||||
#define ADC_PHASE_HALF_SPEED (0x28)//(0x2D) //45
|
||||
#define ADC_PHASE_HALF_SPEED (0x2D) //45
|
||||
#define ADC_PHASE_QUARTER_SPEED (0x2D) //45
|
||||
#define ADC_PORT_INVERT_VAL (0x5A5A5A5A)//(0x453b2a9c)
|
||||
#define MAX_PHASE_SHIFTS (160)
|
||||
|
Reference in New Issue
Block a user