mirror of
https://github.com/slsdetectorgroup/slsDetectorPackage.git
synced 2025-06-19 00:07:13 +02:00
jungfrau server: changes for new firmware, aligning adc deserializer. ctb serveR: removed unnecessary pll reset and polling mode for pll
This commit is contained in:
@ -1,9 +1,9 @@
|
||||
Path: slsDetectorPackage/slsDetectorServers/ctbDetectorServer
|
||||
URL: origin git@github.com:slsdetectorgroup/slsDetectorPackage.git
|
||||
Repository Root: origin git@github.com:slsdetectorgroup/slsDetectorPackage.git
|
||||
Repsitory UUID: 050854de36f01379e974005e204b6563ffbc7004
|
||||
Revision: 43
|
||||
Branch: refactor
|
||||
Repsitory UUID: 5bf37a4f0d840820e676f11419e98c0203d700eb
|
||||
Revision: 44
|
||||
Branch: jungfrau
|
||||
Last Changed Author: Dhanya_Thattil
|
||||
Last Changed Rev: 4458
|
||||
Last Changed Date: 2019-03-21 14:00:57.000000002 +0100 ../slsDetectorServer/ALTERA_PLL.h
|
||||
Last Changed Rev: 4472
|
||||
Last Changed Date: 2019-03-22 14:25:24.000000002 +0100 ../slsDetectorServer/ALTERA_PLL.h
|
||||
|
@ -1,6 +1,6 @@
|
||||
#define GITURL "git@github.com:slsdetectorgroup/slsDetectorPackage.git"
|
||||
#define GITREPUUID "050854de36f01379e974005e204b6563ffbc7004"
|
||||
#define GITREPUUID "5bf37a4f0d840820e676f11419e98c0203d700eb"
|
||||
#define GITAUTH "Dhanya_Thattil"
|
||||
#define GITREV 0x4458
|
||||
#define GITDATE 0x20190321
|
||||
#define GITBRANCH "refactor"
|
||||
#define GITREV 0x4472
|
||||
#define GITDATE 0x20190322
|
||||
#define GITBRANCH "jungfrau"
|
||||
|
@ -822,7 +822,7 @@ int getSpeed(enum speedVariable ind) {
|
||||
switch(ind) {
|
||||
case ADC_PHASE:
|
||||
case PHASE_SHIFT:
|
||||
return getPhase(RUN_CLK);
|
||||
return getPhase(ADC_CLK);
|
||||
case DBIT_PHASE:
|
||||
return getPhase(DBIT_CLK);
|
||||
case ADC_CLOCK:
|
||||
@ -1648,13 +1648,6 @@ void configurePhase(enum CLKINDEX ind, int val) {
|
||||
|
||||
FILE_LOG(logINFO, ("Configuring Phase of C%d(%s) to %d\n", ind, clock_names[ind], val));
|
||||
|
||||
// reset only pll
|
||||
ALTERA_PLL_ResetPLL();
|
||||
|
||||
// set mode register to polling mode
|
||||
ALTERA_PLL_SetModePolling();
|
||||
|
||||
|
||||
int phase = 0;
|
||||
int maxShifts = ((ind == ADC_CLK) ? MAX_PHASE_SHIFTS_ADC_CLK : MAX_PHASE_SHIFTS_DBIT_CLK);
|
||||
|
||||
|
@ -52,7 +52,7 @@ enum DACINDEX {D0, D1, D2, D3, D4, D5, D6, D7, D8, D9,
|
||||
/** Default Parameters */
|
||||
#define DEFAULT_DATA_BYTES (NCHIP * NCHAN * NUM_BITS_PER_PIXEL)
|
||||
#define DEFAULT_NUM_SAMPLES (1)
|
||||
#define DEFAULT_NUM_FRAMES (100 * 1000 * 1000)
|
||||
#define DEFAULT_NUM_FRAMES (1)
|
||||
#define DEFAULT_EXPTIME (0)
|
||||
#define DEFAULT_NUM_CYCLES (1)
|
||||
#define DEFAULT_PERIOD (1 * 1000 * 1000) //ns
|
||||
|
Reference in New Issue
Block a user