detectors/slsDetectorPackage
25
0
Fork 0
mirror of https://github.com/slsdetectorgroup/slsDetectorPackage.git synced 2025-06-13 13:27:14 +02:00
Code Issues Actions Packages Releases Activity

m3: reset fixed

Browse Source
This commit is contained in:
maliakal_d
2019-11-22 16:40:43 +01:00
parent ba008db29a
commit c4675da0c3
8 changed files with 25 additions and 35 deletions
Download Patch File Download Diff File Expand all files Collapse all files

23
slsDetectorServers/gotthard2DetectorServer/RegisterDefs.h
View File

@ -9,6 +9,8 @@
#define BASE_READOUT_PLL (0x0000) // 0x1804_0000 - 0x1804_07FF
/* Reconfiguration core for system pll */
#define BASE_SYSTEM_PLL (0x0800) // 0x1804_0800 - 0x1804_0FFF
/* Clock Generation */
#define BASE_CLK_GENERATION (0x1000) // 0x1804_1000 - 0x1804_XXXX //TODO
/* Base addresses 0x1806 0000 ---------------------------------------------*/
/* General purpose control and status registers */
@ -19,22 +21,13 @@
#define BASE_UDP_RAM (0x01000) // 0x1806_1000 - 0x1806_1FFF
/* Clock Generation registers ------------------------------------------------------*/
#define PLL_RESET_REG (0x00 * REG_OFFSET + BASE_CLK_GENERATION)
/* Readout PLL registers --------------------------------------------------*/
#define READOUT_PLL_RESET_REG (0x1 * REG_OFFSET + BASE_READOUT_PLL) //TODO
#define READOUT_PLL_RESET_OFST (0)
#define READOUT_PLL_RESET_MSK (0x00000001 << READOUT_PLL_RESET_OFST)
/* System PLL registers --------------------------------------------------*/
#define SYSTEM_PLL_RESET_REG (0x1 * REG_OFFSET + BASE_SYSTEM_PLL) //TODO
#define SYSTEM_PLL_RESET_OFST (0)
#define SYSTEM_PLL_RESET_MSK (0x00000001 << SYSTEM_PLL_RESET_OFST)
#define PLL_RESET_READOUT_OFST (0)
#define PLL_RESET_READOUT_MSK (0x00000001 << PLL_RESET_READOUT_OFST)
#define PLL_RESET_SYSTEM_OFST (1)
#define PLL_RESET_SYSTEM_MSK (0x00000001 << PLL_RESET_SYSTEM_OFST)
/* Control registers --------------------------------------------------*/

BIN
slsDetectorServers/gotthard2DetectorServer/bin/gotthard2DetectorServer_developer
View File

Binary file not shown.

2
slsDetectorServers/gotthard2DetectorServer/slsDetectorFunctionList.c
View File

@ -371,7 +371,7 @@ void setupDetector() {
#ifndef VIRTUAL
// pll defines
ALTERA_PLL_C10_SetDefines(REG_OFFSET, BASE_READOUT_PLL, BASE_SYSTEM_PLL, READOUT_PLL_RESET_REG, SYSTEM_PLL_RESET_REG, READOUT_PLL_RESET_MSK, SYSTEM_PLL_RESET_MSK, READOUT_PLL_VCO_FREQ_HZ, SYSTEM_PLL_VCO_FREQ_HZ);
ALTERA_PLL_C10_SetDefines(REG_OFFSET, BASE_READOUT_PLL, BASE_SYSTEM_PLL, PLL_RESET_REG, PLL_RESET_REG, PLL_RESET_READOUT_MSK, PLL_RESET_SYSTEM_MSK, READOUT_PLL_VCO_FREQ_HZ, SYSTEM_PLL_VCO_FREQ_HZ);
ALTERA_PLL_C10_ResetPLL(READOUT_PLL);
ALTERA_PLL_C10_ResetPLL(SYSTEM_PLL);
// hv

22
slsDetectorServers/mythen3DetectorServer/RegisterDefs.h
View File

@ -8,6 +8,8 @@
#define BASE_READOUT_PLL (0x0000) // 0x1804_0000 - 0x1804_07FF
/* Reconfiguration core for system pll */
#define BASE_SYSTEM_PLL (0x0800) // 0x1804_0800 - 0x1804_0FFF
/* Clock Generation */
#define BASE_CLK_GENERATION (0x1000) // 0x1804_1000 - 0x1804_XXXX //TODO
/* Base addresses 0x1806 0000 ---------------------------------------------*/
/* General purpose control and status registers */
@ -30,21 +32,13 @@
/* Clock Generation registers ------------------------------------------------------*/
#define PLL_RESET_REG (0x00 * REG_OFFSET + BASE_CLK_GENERATION)
/* Readout PLL registers --------------------------------------------------*/
#define READOUT_PLL_RESET_REG (0x1 * REG_OFFSET + BASE_READOUT_PLL) //TODO
#define READOUT_PLL_RESET_OFST (0)
#define READOUT_PLL_RESET_MSK (0x00000001 << READOUT_PLL_RESET_OFST)
/* System PLL registers --------------------------------------------------*/
#define SYSTEM_PLL_RESET_REG (0x1 * REG_OFFSET + BASE_SYSTEM_PLL) //TODO
#define SYSTEM_PLL_RESET_OFST (0)
#define SYSTEM_PLL_RESET_MSK (0x00000001 << SYSTEM_PLL_RESET_OFST)
#define PLL_RESET_READOUT_OFST (0)
#define PLL_RESET_READOUT_MSK (0x00000001 << PLL_RESET_READOUT_OFST)
#define PLL_RESET_SYSTEM_OFST (1)
#define PLL_RESET_SYSTEM_MSK (0x00000001 << PLL_RESET_SYSTEM_OFST)

BIN
slsDetectorServers/mythen3DetectorServer/bin/mythen3DetectorServer_developer
View File

Binary file not shown.

2
slsDetectorServers/mythen3DetectorServer/slsDetectorFunctionList.c
View File

@ -351,7 +351,7 @@ void setupDetector() {
#ifndef VIRTUAL
// pll defines
ALTERA_PLL_C10_SetDefines(REG_OFFSET, BASE_READOUT_PLL, BASE_SYSTEM_PLL, READOUT_PLL_RESET_REG, SYSTEM_PLL_RESET_REG, READOUT_PLL_RESET_MSK, SYSTEM_PLL_RESET_MSK, READOUT_PLL_VCO_FREQ_HZ, SYSTEM_PLL_VCO_FREQ_HZ);
ALTERA_PLL_C10_SetDefines(REG_OFFSET, BASE_READOUT_PLL, BASE_SYSTEM_PLL, PLL_RESET_REG, PLL_RESET_REG, PLL_RESET_READOUT_MSK, PLL_RESET_SYSTEM_MSK, READOUT_PLL_VCO_FREQ_HZ, SYSTEM_PLL_VCO_FREQ_HZ);
ALTERA_PLL_C10_ResetPLL(READOUT_PLL);
ALTERA_PLL_C10_ResetPLL(SYSTEM_PLL);
// hv

9
slsDetectorServers/slsDetectorServer/src/ALTERA_PLL_CYCLONE10.c
View File

@ -88,9 +88,12 @@ void ALTERA_PLL_C10_ResetPLL (int pllIndex) {
uint32_t resetreg = ALTERA_PLL_C10_Reset_Reg[pllIndex];
uint32_t resetmsk = ALTERA_PLL_C10_Reset_Msk[pllIndex];
//FILE_LOG(logINFO, ("Resetting PLL %d\n", pllIndex));
FILE_LOG(logWARNING, ("Reset PLL not implemented!\n"));
// bus_w_csp1(resetreg, bus_r_csp1(resetreg) | resetmsk);
#ifdef MYTHEN3D
FILE_LOG(logINFO, ("Resetting PLL %d\n", pllIndex));
bus_w_csp1(resetreg, bus_r_csp1(resetreg) | resetmsk);
#else
FILE_LOG(logWARNING, ("Resetting PLL %d not implemented!\n", pllIndex));
#endif
usleep(ALTERA_PLL_C10_WAIT_TIME_US);
}

2
slsSupportLib/include/versionAPI.h
View File

@ -7,6 +7,6 @@
#define APIGOTTHARD 0x191111
#define APIJUNGFRAU 0x191111
#define APIEIGER 0x191111
#define APIGOTTHARD2 0x191121
#define APICTB 0x191121
#define APIMYTHEN3 0x191122
#define APIGOTTHARD2 0x191122