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https://github.com/slsdetectorgroup/slsDetectorPackage.git
synced 2025-04-21 11:20:04 +02:00
jungfrau 2.0 calibrated settings
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@ -4,7 +4,7 @@
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#define MIN_REQRD_VRSN_T_RD_API 0x171220
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#define MIN_REQRD_VRSN_T_RD_API 0x171220
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#define REQRD_FRMWRE_VRSN_BOARD2 0x210831 // 1.0 pcb (version = 010)
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#define REQRD_FRMWRE_VRSN_BOARD2 0x210831 // 1.0 pcb (version = 010)
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#define REQRD_FRMWRE_VRSN 0x210622 // 2.0 pcb (version = 011)
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#define REQRD_FRMWRE_VRSN 0x210910 // 2.0 pcb (version = 011)
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#define CTRL_SRVR_INIT_TIME_US (300 * 1000)
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#define CTRL_SRVR_INIT_TIME_US (300 * 1000)
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@ -144,7 +144,7 @@ enum CLKINDEX { RUN_CLK, ADC_CLK, DBIT_CLK, NUM_CLOCKS };
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// 2.0 pcb
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// 2.0 pcb
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#define SAMPLE_ADC_FULL_SPEED \
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#define SAMPLE_ADC_FULL_SPEED \
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(SAMPLE_ADC_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_0_VAL + \
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(SAMPLE_ADC_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_0_VAL + \
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SAMPLE_DGTL_SAMPLE_1_VAL + SAMPLE_DECMT_FACTOR_FULL_VAL) // 0x100
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SAMPLE_DGTL_SAMPLE_1_VAL + SAMPLE_DECMT_FACTOR_FULL_VAL) // 0x0100
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#define SAMPLE_ADC_HALF_SPEED \
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#define SAMPLE_ADC_HALF_SPEED \
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(SAMPLE_ADC_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_1_VAL + \
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(SAMPLE_ADC_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_1_VAL + \
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SAMPLE_DGTL_SAMPLE_3_VAL + SAMPLE_DECMT_FACTOR_HALF_VAL) // 0x1310
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SAMPLE_DGTL_SAMPLE_3_VAL + SAMPLE_DECMT_FACTOR_HALF_VAL) // 0x1310
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@ -159,13 +159,13 @@ enum CLKINDEX { RUN_CLK, ADC_CLK, DBIT_CLK, NUM_CLOCKS };
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(SAMPLE_ADC_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_1_VAL + \
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(SAMPLE_ADC_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_1_VAL + \
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SAMPLE_DGTL_SAMPLE_6_VAL + SAMPLE_DECMT_FACTOR_QUARTER_VAL) // 0x2610
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SAMPLE_DGTL_SAMPLE_6_VAL + SAMPLE_DECMT_FACTOR_QUARTER_VAL) // 0x2610
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#define ADC_PHASE_FULL_SPEED (150) // 2.0 pcb
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#define ADC_PHASE_FULL_SPEED (175) // 2.0 pcb
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#define ADC_PHASE_HALF_SPEED (200) // 2.0 pcb
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#define ADC_PHASE_HALF_SPEED (175) // 2.0 pcb
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#define ADC_PHASE_QUARTER_SPEED (200) // 2.0 pcb
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#define ADC_PHASE_QUARTER_SPEED (175) // 2.0 pcb
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#define ADC_PHASE_HALF_SPEED_BOARD2 (110) // 1.0 pcb (2 resistor network)
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#define ADC_PHASE_HALF_SPEED_BOARD2 (110) // 1.0 pcb (2 resistor network)
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#define ADC_PHASE_QUARTER_SPEED_BOARD2 (220) // 1.0 pcb (2 resistor network)
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#define ADC_PHASE_QUARTER_SPEED_BOARD2 (220) // 1.0 pcb (2 resistor network)
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#define DBIT_PHASE_FULL_SPEED (85) // 2.0 pcb
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#define DBIT_PHASE_FULL_SPEED (100) // 2.0 pcb
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#define DBIT_PHASE_HALF_SPEED (150) // 2.0 pcb
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#define DBIT_PHASE_HALF_SPEED (150) // 2.0 pcb
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#define DBIT_PHASE_QUARTER_SPEED (150) // 2.0 pcb
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#define DBIT_PHASE_QUARTER_SPEED (150) // 2.0 pcb
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#define DBIT_PHASE_HALF_SPEED_BOARD2 (150) // 1.0 pcb (2 resistor network)
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#define DBIT_PHASE_HALF_SPEED_BOARD2 (150) // 1.0 pcb (2 resistor network)
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