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Merge branch 'developer' of github.com:slsdetectorgroup/slsDetectorPackage into developer

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This commit is contained in:
Erik Frojdh
2020-05-06 12:02:54 +02:00
parent c16411ba00 379b9b53b4
commit a12d47da36
95 changed files with 24252 additions and 22210 deletions
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1
CMakeLists.txt
View File

@@ -50,7 +50,6 @@ option(SLS_TUNE_LOCAL "tune to local machine" OFF)
set(ClangFormat_EXCLUDE_PATTERNS "build/"
"libs/"
"slsDetectorCalibration/"
"slsDetectorServers/"
"ctbGui/"
"manual/"
"python/"

2
cmake/clang-format.cmake
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@@ -1,7 +1,7 @@
# A CMake script to find all source files and setup clang-format targets for them
# Find all source files
set(ClangFormat_CXX_FILE_EXTENSIONS ${ClangFormat_CXX_FILE_EXTENSIONS} *.cpp *.h *.cxx *.hxx *.hpp *.cc *.ipp)
set(ClangFormat_CXX_FILE_EXTENSIONS ${ClangFormat_CXX_FILE_EXTENSIONS} *.cpp *.h *.cxx *.hxx *.hpp *.cc *.ipp *.c)
file(GLOB_RECURSE ALL_SOURCE_FILES ${ClangFormat_CXX_FILE_EXTENSIONS})
# Don't include some common build folders

1
ctbGui/patternGenerator/generate.sh
View File

@@ -21,6 +21,7 @@ if [ -f "$infile" ]
then
gcc -DINFILE="\"$infile\"" -DOUTFILE="\"$outfile\"" -DOUTFILEBIN="\"$outfilebin\"" -o $exe generator.c ;
echo compiling
echo gcc -DINFILE="\"$infile\"" -DOUTFILE="\"$outfile\"" -DOUTFILEBIN="\"$outfilebin\"" -o $exe generator.c ;
$exe ;
echo cleaning
rm $exe

2
slsDetectorCalibration/dataStructures/moench04CtbZmq10GbData.h
View File

@@ -156,7 +156,7 @@ class moench04CtbZmq10GbData : public slsDetectorData<uint16_t> {
if (dSamples>isample) {
ptr=data+32*(isample+1)+8*isample;
sample=*((uint64_t*)ptr);
cout << isc << " " << ibit[isc] << " " << isample << hex << sample << dec << endl;
// cout << isc << " " << ibit[isc] << " " << isample << hex << sample << dec << endl;
if (sample & (1<<ibit[isc]))
return 1;
else

2
slsDetectorCalibration/dataStructures/moench04CtbZmqData.h
View File

@@ -120,7 +120,7 @@ class moench04CtbZmqData : public slsDetectorData<uint16_t> {
if (dSamples>isample) {
ptr=data+aoff+8*isample;
sample=*((uint64_t*)ptr);
cout << isc << " " << ibit[isc] << " " << isample << hex << sample << dec << endl;
// cout << isc << " " << ibit[isc] << " " << isample << hex << sample << dec << endl;
if (sample & (1<<ibit[isc]))
return 1;
else

5
slsDetectorCalibration/moenchExecutables/Makefile.zmq
View File

@@ -5,12 +5,15 @@ LDFLAG= -L/usr/lib64/ -lpthread -lm -lstdc++ -lzmq -pthread -lrt -ltiff -O3
#DESTDIR?=../bin
all: moenchZmqProcess
all: moenchZmqProcess moenchZmq04Process
#moenchZmqProcessCtbGui
moenchZmqProcess: moenchZmqProcess.cpp clean
g++ -o moenchZmqProcess moenchZmqProcess.cpp $(LDFLAG) $(INCDIR) $(LIBHDF5) $(LIBRARYCBF) -DNEWZMQ -DINTERP
moenchZmq04Process: moenchZmqProcess.cpp clean
g++ -o moench04ZmqProcess moenchZmqProcess.cpp $(LDFLAG) $(INCDIR) $(LIBHDF5) $(LIBRARYCBF) -DNEWZMQ -DINTERP -DMOENCH04
#moenchZmqProcessCtbGui: moenchZmqProcess.cpp clean
# g++ -o moenchZmqProcessCtbGui moenchZmqProcess.cpp $(LDFLAG) $(INCDIR) $(LIBHDF5) $(LIBRARYCBF) -DNEWZMQ -DINTERP -DCTBGUI

287
slsDetectorCalibration/moenchExecutables/moenchZmqProcess.cpp
View File

@@ -8,7 +8,13 @@
#include "sls_detector_defs.h"
#include "ZmqSocket.h"
#ifndef RECT
#ifndef MOENCH04
#include "moench03T1ZmqDataNew.h"
#endif
#ifdef MOENCH04
#include "moench04CtbZmq10GbData.h"
#endif
#endif
#ifdef RECT
#include "moench03T1ZmqDataNewRect.h"
@@ -73,6 +79,10 @@ int main(int argc, char *argv[]) {
char* socketip2 = 0;
uint32_t portnum2 = 0;
zmqHeader zHeader, outHeader;
zHeader.jsonversion = SLS_DETECTOR_JSON_HEADER_VERSION;
outHeader.jsonversion = SLS_DETECTOR_JSON_HEADER_VERSION;
uint32_t nSigma=5;
int ok;
@@ -124,7 +134,12 @@ int main(int argc, char *argv[]) {
}
//slsDetectorData *det=new moench03T1ZmqDataNew();
#ifndef MOENCH04
moench03T1ZmqDataNew *det=new moench03T1ZmqDataNew();
#endif
#ifdef MOENCH04
moench04CtbZmq10GbData *det=new moench04CtbZmq10GbData();
#endif
cout << endl << " det" <<endl;
int npx, npy;
det->getDetectorSize(npx, npy);
@@ -140,13 +155,15 @@ int main(int argc, char *argv[]) {
char dummybuff[size];
int ncol_cm=CM_ROWS;
double xt_ghost=C_GHOST;
moench03CommonMode *cm=NULL;
moench03GhostSummation *gs=NULL;
#ifdef CORR
cm=new moench03CommonMode(ncol_cm);
gs=new moench03GhostSummation(det, xt_ghost);
//int ncol_cm=CM_ROWS;
//double xt_ghost=C_GHOST;
cm=new moench03CommonMode(CM_ROWS);
gs=new moench03GhostSummation(det, C_GHOST);
#endif
double *gainmap=NULL;
float *gm;
@@ -308,9 +325,10 @@ int main(int argc, char *argv[]) {
uint64_t bunchId = 0;
uint64_t timestamp = 0;
int16_t modId = 0;
uint32_t expLength=0;
uint16_t xCoord = 0;
uint16_t yCoord = 0;
uint16_t zCoord = 0;
//uint16_t zCoord = 0;
uint32_t debug = 0;
//uint32_t dr = 16;
//int16_t *dout;//=new int16_t [nnx*nny];
@@ -341,6 +359,7 @@ int main(int argc, char *argv[]) {
filter->getImageSize(nnx, nny,nnsx, nnsy);
std::map<std::string, std::string> addJsonHeader;
@@ -350,16 +369,13 @@ int main(int argc, char *argv[]) {
// cout << "+++++++++++++++++++++++++++++++LOOP" << endl;
// get header, (if dummy, fail is on parse error or end of acquisition)
#ifndef NEWZMQ
if (!zmqsocket->ReceiveHeader(0, acqIndex, frameIndex, subframeIndex, filename, fileindex)){
#endif
#ifdef NEWZMQ
rapidjson::Document doc;
if (!zmqsocket->ReceiveHeader(0, doc, SLS_DETECTOR_JSON_HEADER_VERSION)) {
// rapidjson::Document doc;
if (!zmqsocket->ReceiveHeader(0, zHeader, SLS_DETECTOR_JSON_HEADER_VERSION)) {
/* zmqsocket->CloseHeaderMessage();*/
#endif
// if (!zmqsocket->ReceiveHeader(0, acqIndex, frameIndex, subframeIndex, filename, fileindex)) {
cprintf(RED, "Got Dummy\n");
// t1=high_resolution_clock::now();
@@ -378,7 +394,11 @@ int main(int argc, char *argv[]) {
if (newFrame>0) {
cprintf(RED,"DIDn't receive any data!\n");
if (send) {
zmqsocket2->SendHeaderData(0, true, SLS_DETECTOR_JSON_HEADER_VERSION);
//zHeader.data = false;
outHeader.data=false;
// zmqsocket2->SendHeaderData(0, true, SLS_DETECTOR_JSON_HEADER_VERSION);
zmqsocket2->SendHeader(0,outHeader);
cprintf(RED, "Sent Dummy\n");
}
} else {
@@ -510,14 +530,39 @@ int main(int argc, char *argv[]) {
if(send_something) {
zmqsocket2->SendHeaderData (0, false,SLS_DETECTOR_JSON_HEADER_VERSION , dr, fileindex, 1,1,nnx,nny,nnx*nny*dr/8,acqIndex, frameIndex, fname,acqIndex,0 , packetNumber,bunchId, timestamp, modId,xCoord, yCoord, zCoord,debug, roundRNumber, detType, version, 0,0, 0,&additionalJsonHeader);
// zmqsocket2->SendHeaderData (0, false,SLS_DETECTOR_JSON_HEADER_VERSION , dr, fileindex, 1,1,nnx,nny,nnx*nny*dr/8,acqIndex, frameIndex, fname,acqIndex,0 , packetNumber,bunchId, timestamp, modId,xCoord, yCoord, zCoord,debug, roundRNumber, detType, version, 0,0, 0,&additionalJsonHeader);
outHeader.data=true;
outHeader.dynamicRange=dr;
outHeader.fileIndex=fileindex;
outHeader.ndetx=1;
outHeader.ndety=1;
outHeader.npixelsx=nnx;
outHeader.npixelsy=nny;
outHeader.imageSize=nnx*nny*dr/8;
outHeader.acqIndex=acqIndex;
outHeader.frameIndex=frameIndex;
outHeader.fname=fname;
outHeader.frameNumber=acqIndex;
outHeader.expLength=expLength;
outHeader.packetNumber=packetNumber;
outHeader.bunchId=bunchId;
outHeader.timestamp=timestamp;
outHeader.modId=modId;
outHeader.row=xCoord;
outHeader.column=yCoord;
outHeader.debug=debug;
outHeader.roundRNumber=roundRNumber;
outHeader.detType=detType;
outHeader.version=version;
zmqsocket2->SendHeader(0,outHeader);
zmqsocket2->SendData((char*)dout,nnx*nny*dr/8);
cprintf(GREEN, "Sent Data\n");
}
zmqsocket2->SendHeaderData(0, true, SLS_DETECTOR_JSON_HEADER_VERSION);
outHeader.data=false;
zmqsocket2->SendHeader(0,outHeader);
// zmqsocket2->SendHeaderData(0, true, SLS_DETECTOR_JSON_HEADER_VERSION);
cprintf(RED, "Sent Dummy\n");
if (dout)
delete [] dout;
@@ -544,33 +589,84 @@ int main(int argc, char *argv[]) {
}
#ifdef NEWZMQ
//#ifdef NEWZMQ
if (newFrame) {
begin = std::chrono::steady_clock::now();
//time(&begin);
// t0 = high_resolution_clock::now();
//cout <<"new frame" << endl;
// acqIndex, frameIndex, subframeIndex, filename, fileindex
size = doc["size"].GetUint();
// multisize = size;// * zmqsocket->size();
// dynamicRange = doc["bitmode"].GetUint();
// nPixelsX = doc["shape"][0].GetUint();
// nPixelsY = doc["shape"][1].GetUint();
filename = doc["fname"].GetString();
//acqIndex = doc["acqIndex"].GetUint64();
//frameIndex = doc["fIndex"].GetUint64();
fileindex = doc["fileIndex"].GetUint64();
//subFrameIndex = doc["expLength"].GetUint();
//packetNumber=doc["packetNumber"].GetUint();
//bunchId=doc["bunchId"].GetUint();
//timestamp=doc["timestamp"].GetUint();
//modId=doc["modId"].GetUint();
//debug=doc["debug"].GetUint();
//roundRNumber=doc["roundRNumber"].GetUint();
//detType=doc["detType"].GetUint();
//version=doc["version"].GetUint();
size = zHeader.imageSize;//doc["size"].GetUint();
// dynamicRange = zheader.dynamicRange; //doc["bitmode"].GetUint();
// nPixelsX = zHeader.npixelsx; //doc["shape"][0].GetUint();
// nPixelsY = zHeader.npixelsy;// doc["shape"][1].GetUint();
filename = zHeader.fname;//doc["fname"].GetString();
acqIndex = zHeader.acqIndex; //doc["acqIndex"].GetUint64();
// frameIndex = zHeader.frameIndex;//doc["fIndex"].GetUint64();
fileindex = zHeader.fileIndex;//doc["fileIndex"].GetUint64();
expLength = zHeader.expLength;//doc["expLength"].GetUint();
packetNumber=zHeader.packetNumber;//doc["packetNumber"].GetUint();
bunchId=zHeader.bunchId;//doc["bunchId"].GetUint();
timestamp=zHeader.timestamp;//doc["timestamp"].GetUint();
modId=zHeader.modId;//doc["modId"].GetUint();
debug=zHeader.debug;//doc["debug"].GetUint();
// roundRNumber=r.roundRNumber;//doc["roundRNumber"].GetUint();
detType=zHeader.detType;//doc["detType"].GetUint();
version=zHeader.version;//doc["version"].GetUint();
/*document["bitmode"].GetUint(); zHeader.dynamicRange
document["fileIndex"].GetUint64(); zHeader.fileIndex
document["detshape"][0].GetUint();
zHeader.ndetx
document["detshape"][1].GetUint();
zHeader.ndety
document["shape"][0].GetUint();
zHeader.npixelsx
document["shape"][1].GetUint();
zHeader.npixelsy
document["size"].GetUint(); zHeader.imageSize
document["acqIndex"].GetUint64(); zHeader.acqIndex
document["frameIndex"].GetUint64(); zHeader.frameIndex
document["fname"].GetString(); zHeader.fname
document["frameNumber"].GetUint64(); zHeader.frameNumber
document["expLength"].GetUint(); zHeader.expLength
document["packetNumber"].GetUint(); zHeader.packetNumber
document["bunchId"].GetUint64(); zHeader.bunchId
document["timestamp"].GetUint64(); zHeader.timestamp
document["modId"].GetUint(); zHeader.modId
document["row"].GetUint(); zHeader.row
document["column"].GetUint(); zHeader.column
document["reserved"].GetUint(); zHeader.reserved
document["debug"].GetUint(); zHeader.debug
document["roundRNumber"].GetUint(); zHeader.roundRNumber
document["detType"].GetUint(); zHeader.detType
document["version"].GetUint(); zHeader.version
document["flippedDataX"].GetUint(); zHeader.flippedDataX
document["quad"].GetUint(); zHeader.quad
document["completeImage"].GetUint(); zHeader.completeImage
*/
//dataSize=size;
//strcpy(fname,filename.c_str());
@@ -604,6 +700,8 @@ int main(int argc, char *argv[]) {
// xCoord, yCoord,zCoord,
// flippedDataX, packetNumber, bunchId, timestamp, modId, debug, roundRNumber, detType, version);
addJsonHeader=zHeader.addJsonHeader;
/* Analog detector commands */
//isPedestal=0;
//isFlat=0;
@@ -611,9 +709,10 @@ int main(int argc, char *argv[]) {
fMode=eFrame;
frameMode_s="frame";
cprintf(MAGENTA, "Frame mode: ");
if (doc.HasMember("frameMode")) {
if (doc["frameMode"].IsString()) {
frameMode_s=doc["frameMode"].GetString();
// if (doc.HasMember("frameMode")) {
if (addJsonHeader.find("frameMode")!= addJsonHeader.end()) {
// if (doc["frameMode"].IsString()) {
frameMode_s=addJsonHeader.at("frameMode");//doc["frameMode"].GetString();
if (frameMode_s == "pedestal"){
fMode=ePedestal;
//isPedestal=1;
@@ -639,7 +738,7 @@ int main(int argc, char *argv[]) {
cprintf(MAGENTA, "Resetting flatfield\n");
fMode=eFlat;
}
#endif
//#endif
else {
fMode=eFrame;
//isPedestal=0;
@@ -647,19 +746,23 @@ int main(int argc, char *argv[]) {
fMode=eFrame;
frameMode_s="frame";
}
}
//}
}
cprintf(MAGENTA, "%s\n" , frameMode_s.c_str());
mt->setFrameMode(fMode);
// threshold=0;
cprintf(MAGENTA, "Threshold: ");
if (doc.HasMember("threshold")) {
if (doc["threshold"].IsInt()) {
threshold=doc["threshold"].GetInt();
if (addJsonHeader.find("threshold")!= addJsonHeader.end()) {
istringstream(addJsonHeader.at("threshold")) >>threshold;
// threshold=atoi(addJsonHeader.at("threshold").c_str());//doc["frameMode"].GetString();
}
//if (doc.HasMember("threshold")) {
//if (doc["threshold"].IsInt()) {
// threshold=doc["threshold"].GetInt();
mt->setThreshold(threshold);
}
}
// }
// }
cprintf(MAGENTA, "%d\n", threshold);
xmin=0;
@@ -667,40 +770,47 @@ int main(int argc, char *argv[]) {
ymin=0;
ymax=npy;
cprintf(MAGENTA, "ROI: ");
if (doc.HasMember("roi")) {
if (doc["roi"].IsArray()) {
if (doc["roi"].Size() > 0 )
if (doc["roi"][0].IsInt())
xmin=doc["roi"][0].GetInt();
if (doc["roi"].Size() > 1 )
if (doc["roi"][1].IsInt())
xmax=doc["roi"][1].GetInt();
if (addJsonHeader.find("roi")!= addJsonHeader.end()) {
istringstream(addJsonHeader.at("roi")) >> xmin >> xmax >> ymin >> ymax ;
// if (doc.HasMember("roi")) {
//if (doc["roi"].IsArray()) {
// if (doc["roi"].Size() > 0 )
// if (doc["roi"][0].IsInt())
// xmin=doc["roi"][0].GetInt();
if (doc["roi"].Size() > 2 )
if (doc["roi"][2].IsInt())
ymin=doc["roi"][2].GetInt();
// if (doc["roi"].Size() > 1 )
// if (doc["roi"][1].IsInt())
// xmax=doc["roi"][1].GetInt();
if (doc["roi"].Size() > 3 )
if (doc["roi"][3].IsInt())
ymax=doc["roi"][3].GetInt();
}
// if (doc["roi"].Size() > 2 )
// if (doc["roi"][2].IsInt())
// ymin=doc["roi"][2].GetInt();
// if (doc["roi"].Size() > 3 )
// if (doc["roi"][3].IsInt())
// ymax=doc["roi"][3].GetInt();
// }
}
cprintf(MAGENTA, "%d %d %d %d\n", xmin, xmax, ymin, ymax);
mt->setROI(xmin, xmax, ymin, ymax);
if (doc.HasMember("dynamicRange")) {
dr=doc["dynamicRange"].GetUint();
if (addJsonHeader.find("dynamicRange")!= addJsonHeader.end()) {
istringstream(addJsonHeader.at("dynamicRange")) >> dr ;
dr=32;
}
// if (doc.HasMember("dynamicRange")) {
// dr=doc["dynamicRange"].GetUint();
// dr=32;
// }
dMode=eAnalog;
detectorMode_s="analog";
cprintf(MAGENTA, "Detector mode: ");
if (doc.HasMember("detectorMode")) {
if (doc["detectorMode"].IsString()) {
detectorMode_s=doc["detectorMode"].GetString();
if (addJsonHeader.find("detectorMode")!= addJsonHeader.end()) {;
//if (doc.HasMember("detectorMode")) {
//if (doc["detectorMode"].IsString()) {
detectorMode_s=addJsonHeader.at("detectorMode");//=doc["detectorMode"].GetString();
#ifdef INTERP
if (detectorMode_s == "interpolating"){
dMode=eInterpolating;
@@ -718,7 +828,7 @@ int main(int argc, char *argv[]) {
mt->setInterpolation(NULL);
#endif
}
}
// }
}
@@ -767,19 +877,19 @@ int main(int argc, char *argv[]) {
// }
// threshold=0;
cprintf(MAGENTA, "Subframes: ");
subframes=0;
//isubframe=0;
insubframe=0;
subnorm=1;
f0=0;
nnsubframe=0;
if (doc.HasMember("subframes")) {
if (doc["subframes"].IsInt()) {
subframes=doc["subframes"].GetInt();
}
}
cprintf(MAGENTA, "%ld\n", subframes);
// cprintf(MAGENTA, "Subframes: ");
// subframes=0;
// //isubframe=0;
// insubframe=0;
// subnorm=1;
// f0=0;
// nnsubframe=0;
// if (doc.HasMember("subframes")) {
// if (doc["subframes"].IsInt()) {
// subframes=doc["subframes"].GetInt();
// }
// }
// cprintf(MAGENTA, "%ld\n", subframes);
newFrame=0;
@@ -811,13 +921,13 @@ int main(int argc, char *argv[]) {
// get data
// acqIndex = doc["acqIndex"].GetUint64();
frameIndex = doc["fIndex"].GetUint64();
frameIndex = zHeader.frameIndex;////doc["fIndex"].GetUint64();
// subFrameIndex = doc["expLength"].GetUint();
// bunchId=doc["bunchId"].GetUint();
// timestamp=doc["timestamp"].GetUint();
packetNumber=doc["packetNumber"].GetUint();
packetNumber=zHeader.packetNumber; //doc["packetNumber"].GetUint();
// cout << acqIndex << " " << frameIndex << " " << subFrameIndex << " "<< bunchId << " " << timestamp << " " << packetNumber << endl;
//cprintf(GREEN, "frame\n");
if (packetNumber>=40) {
@@ -866,8 +976,9 @@ int main(int argc, char *argv[]) {
zmqsocket2->SendHeaderData (0, false,SLS_DETECTOR_JSON_HEADER_VERSION , dr, fileindex, 1,1,nnx,nny,nnx*nny*dr/8,acqIndex, frameIndex, fname,acqIndex,0 , packetNumber,bunchId, timestamp, modId,xCoord, yCoord, zCoord,debug, roundRNumber, detType, version, 0,0, 0,&additionalJsonHeader);
// zmqsocket2->SendHeaderData (0, false,SLS_DETECTOR_JSON_HEADER_VERSION , dr, fileindex, 1,1,nnx,nny,nnx*nny*dr/8,acqIndex, frameIndex, fname,acqIndex,0 , packetNumber,bunchId, timestamp, modId,xCoord, yCoord, zCoord,debug, roundRNumber, detType, version, 0,0, 0,&additionalJsonHeader);
zHeader.data = true;
zmqsocket2->SendHeader(0,zHeader);
zmqsocket2->SendData((char*)dout,nnx*nny*dr/8);
cprintf(GREEN, "Sent subdata\n");

2
slsDetectorCalibration/singlePhotonDetector.h
View File

@@ -490,7 +490,7 @@ int *getClusters(char *data, int *ph=NULL) {
// (clusters+nph)->ped=getPedestal(ix,iy,0);
for (ir=-(clusterSizeY/2); ir<(clusterSizeY/2)+1; ir++) {
for (ic=-(clusterSize/2); ic<(clusterSize/2)+1; ic++) {
if ((iy+ir)>=iy && (iy+ir)<ny && (ix+ic)>=ix && (ix+ic)<nx)
if ((iy+ir)>=0 && (iy+ir)<ny && (ix+ic)>=0 && (ix+ic)<nx)
(clusters+nph)->set_data(val[iy+ir][ix+ic],ic,ir);
}
}

23
slsDetectorCalibration/single_photon_hit.h
View File

@@ -36,16 +36,14 @@ class single_photon_hit {
\param myFile file descriptor
*/
size_t write(FILE *myFile) {
//fwrite((void*)this, 1, 3*sizeof(int)+4*sizeof(double)+sizeof(quad), myFile);
// if (fwrite((void*)this, 1, sizeof(int)+2*sizeof(int16_t), myFile))
//fwrite((void*)this, 1, 3*sizeof(int)+4*sizeof(double)+sizeof(quad), myFile); // if (fwrite((void*)this, 1, sizeof(int)+2*sizeof(int16_t), myFile))
#ifdef OLDFORMAT
if (fwrite((void*)&iframe, 1, sizeof(int), myFile)) {};
#endif
#ifndef WRITE_QUAD
//printf("no quad ");
//if (fwrite((void*)&x, 2, sizeof(int16_t), myFile))
return fwrite((void*)&x, 1, dx*dy*sizeof(int)+2*sizeof(int16_t), myFile);
if (fwrite((void*)&x, sizeof(int16_t), 2, myFile))
return fwrite((void*)data, sizeof(int), dx*dy, myFile);
#endif
#ifdef WRITE_QUAD
// printf("quad ");
@@ -91,8 +89,8 @@ class single_photon_hit {
default:
;
}
if (fwrite((void*)&x, 2, sizeof(int16_t), myFile))
return fwrite((void*)qq, 1, 4*sizeof(int), myFile);
if (fwrite((void*)&x, sizeof(int16_t), 2, myFile))
return fwrite((void*)qq, sizeof(int), 4, myFile);
#endif
return 0;
};
@@ -109,14 +107,14 @@ class single_photon_hit {
#endif
#ifndef WRITE_QUAD
// printf( "no quad \n");
if (fread((void*)&x, 2, sizeof(int16_t), myFile))
return fread((void*)data, 1, dx*dy*sizeof(int), myFile);
if (fread((void*)&x, sizeof(int16_t),2, myFile))
return fread((void*)data, sizeof(int), dx*dy,myFile);
#endif
#ifdef WRITE_QUAD
int qq[4];
// printf( "quad \n");
if (fread((void*)&x, 2, sizeof(int16_t), myFile))
if (fread((void*)qq, 1, 4*sizeof(int), myFile)) {
printf( "quad \n");
if (fread((void*)&x, sizeof(int16_t), 2, myFile))
if (fread((void*)qq, sizeof(int), 4, myFile)) {
quad=TOP_RIGHT;
/* int mm=qq[0]; */
@@ -216,7 +214,6 @@ class single_photon_hit {
for (int iy=0; iy<dy; iy++) {
for (int ix=0; ix<dx; ix++) {
printf("%d \t",data[ix+iy*dx]);
}
printf("\n");
}

130
slsDetectorServers/ctbDetectorServer/RegisterDefs.h Executable file → Normal file
View File

@@ -10,7 +10,8 @@
#define FPGA_VERSION_BRD_RVSN_MSK (0x00FFFFFF << FPGA_VERSION_BRD_RVSN_OFST)
#define FPGA_VERSION_DTCTR_TYP_OFST (24)
#define FPGA_VERSION_DTCTR_TYP_MSK (0x000000FF << FPGA_VERSION_DTCTR_TYP_OFST)
#define FPGA_VERSION_DTCTR_TYP_CTB_VAL ((0x4 << FPGA_VERSION_DTCTR_TYP_OFST) & FPGA_VERSION_DTCTR_TYP_MSK)
#define FPGA_VERSION_DTCTR_TYP_CTB_VAL \
((0x4 << FPGA_VERSION_DTCTR_TYP_OFST) & FPGA_VERSION_DTCTR_TYP_MSK)
/* Fix pattern RO register */
#define FIX_PATT_REG (0x01 << MEM_MAP_SHIFT)
@@ -57,7 +58,8 @@
#define STATUS_PLL_PHS_DN_OFST (23)
#define STATUS_PLL_PHS_DN_MSK (0x00000001 << STATUS_PLL_PHS_DN_OFST)
#define STATUS_PT_CNTRL_STTS_OFF_OFST (24)
#define STATUS_PT_CNTRL_STTS_OFF_MSK (0x000000FF << STATUS_PT_CNTRL_STTS_OFF_OFST)
#define STATUS_PT_CNTRL_STTS_OFF_MSK \
(0x000000FF << STATUS_PT_CNTRL_STTS_OFF_OFST)
#define STATUS_IDLE_MSK (0x677FF)
/* Look at me RO register TODO */
@@ -67,24 +69,30 @@
#define SYSTEM_STATUS_REG (0x04 << MEM_MAP_SHIFT)
#define SYSTEM_STATUS_DDR3_CLBRTN_OK_OFST (0)
#define SYSTEM_STATUS_DDR3_CLBRTN_OK_MSK (0x00000001 << SYSTEM_STATUS_DDR3_CLBRTN_OK_OFST)
#define SYSTEM_STATUS_DDR3_CLBRTN_OK_MSK \
(0x00000001 << SYSTEM_STATUS_DDR3_CLBRTN_OK_OFST)
#define SYSTEM_STATUS_DDR3_CLBRTN_FL_OFST (1)
#define SYSTEM_STATUS_DDR3_CLBRTN_FL_MSK (0x00000001 << SYSTEM_STATUS_DDR3_CLBRTN_FL_OFST)
#define SYSTEM_STATUS_DDR3_CLBRTN_FL_MSK \
(0x00000001 << SYSTEM_STATUS_DDR3_CLBRTN_FL_OFST)
#define SYSTEM_STATUS_DDR3_INT_DN_OFST (2)
#define SYSTEM_STATUS_DDR3_INT_DN_MSK (0x00000001 << SYSTEM_STATUS_DDR3_INT_DN_OFST)
#define SYSTEM_STATUS_DDR3_INT_DN_MSK \
(0x00000001 << SYSTEM_STATUS_DDR3_INT_DN_OFST)
#define SYSTEM_STATUS_RCNFG_PLL_LCK_OFST (3)
#define SYSTEM_STATUS_RCNFG_PLL_LCK_MSK (0x00000001 << SYSTEM_STATUS_RCNFG_PLL_LCK_OFST)
#define SYSTEM_STATUS_RCNFG_PLL_LCK_MSK \
(0x00000001 << SYSTEM_STATUS_RCNFG_PLL_LCK_OFST)
#define SYSTEM_STATUS_PLL_A_LCK_OFST (4)
#define SYSTEM_STATUS_PLL_A_LCK_MSK (0x00000001 << SYSTEM_STATUS_PLL_A_LCK_OFST)
/* PLL Param (Reconfiguratble PLL Parameter) RO register TODO FIXME: Same as PLL_PARAM_REG 0x50 */
/* PLL Param (Reconfiguratble PLL Parameter) RO register TODO FIXME: Same as
* PLL_PARAM_REG 0x50 */
//#define PLL_PARAM_REG (0x05 << MEM_MAP_SHIFT)
/* FIFO Data RO register TODO */
#define FIFO_DATA_REG (0x06 << MEM_MAP_SHIFT)
#define FIFO_DATA_HRDWR_SRL_NMBR_OFST (0)
#define FIFO_DATA_HRDWR_SRL_NMBR_MSK (0x0000FFFF << FIFO_DATA_HRDWR_SRL_NMBR_OFST)
#define FIFO_DATA_HRDWR_SRL_NMBR_MSK \
(0x0000FFFF << FIFO_DATA_HRDWR_SRL_NMBR_OFST)
//#define FIFO_DATA_WRD_OFST (16)
//#define FIFO_DATA_WRD_MSK (0x0000FFFF << FIFO_DATA_WRD_OFST)
@@ -114,7 +122,8 @@
#define API_VERSION_DTCTR_TYP_OFST (24)
#define API_VERSION_DTCTR_TYP_MSK (0x000000FF << API_VERSION_DTCTR_TYP_OFST)
/* Time from Start 64 bit RO register. t = GCLK x 50 ns. Reset using CONTROL_CRST. TODO */
/* Time from Start 64 bit RO register. t = GCLK x 50 ns. Reset using
* CONTROL_CRST. TODO */
#define TIME_FROM_START_LSB_REG (0x10 << MEM_MAP_SHIFT)
#define TIME_FROM_START_MSB_REG (0x11 << MEM_MAP_SHIFT)
@@ -135,12 +144,16 @@
#define PERIOD_LEFT_MSB_REG (0x19 << MEM_MAP_SHIFT)
/* Exposure Time Left 64 bit RO register */
//#define EXPTIME_LEFT_LSB_REG (0x1A << MEM_MAP_SHIFT) // Not used in FW
//#define EXPTIME_LEFT_MSB_REG (0x1B << MEM_MAP_SHIFT) // Not used in FW
//#define EXPTIME_LEFT_LSB_REG (0x1A << MEM_MAP_SHIFT) // Not
// used in FW #define EXPTIME_LEFT_MSB_REG (0x1B <<
// MEM_MAP_SHIFT)
//// Not used in FW
/* Gates Left 64 bit RO register */
//#define GATES_LEFT_LSB_REG (0x1C << MEM_MAP_SHIFT) // Not used in FW
//#define GATES_LEFT_MSB_REG (0x1D << MEM_MAP_SHIFT) // Not used in FW
//#define GATES_LEFT_LSB_REG (0x1C << MEM_MAP_SHIFT) // Not
// used in FW #define GATES_LEFT_MSB_REG (0x1D <<
// MEM_MAP_SHIFT)
//// Not used in FW
/* Data In 64 bit RO register TODO */
#define DATA_IN_LSB_REG (0x1E << MEM_MAP_SHIFT)
@@ -151,14 +164,17 @@
#define PATTERN_OUT_MSB_REG (0x21 << MEM_MAP_SHIFT)
/* Frames From Start 64 bit RO register TODO */
//#define FRAMES_FROM_START_LSB_REG (0x22 << MEM_MAP_SHIFT) // Not used in FW
//#define FRAMES_FROM_START_MSB_REG (0x23 << MEM_MAP_SHIFT) // Not used in FW
//#define FRAMES_FROM_START_LSB_REG (0x22 << MEM_MAP_SHIFT) // Not
// used in FW #define FRAMES_FROM_START_MSB_REG (0x23 <<
// MEM_MAP_SHIFT)
//// Not used in FW
/* Frames From Start PG 64 bit RO register. Reset using CONTROL_CRST. TODO */
#define FRAMES_FROM_START_PG_LSB_REG (0x24 << MEM_MAP_SHIFT)
#define FRAMES_FROM_START_PG_MSB_REG (0x25 << MEM_MAP_SHIFT)
/* Start Frame Time (Measurement Time) 64 bit register (timestamp at a frame start until reset) TODO */
/* Start Frame Time (Measurement Time) 64 bit register (timestamp at a frame
* start until reset) TODO */
#define START_FRAME_TIME_LSB_REG (0x26 << MEM_MAP_SHIFT)
#define START_FRAME_TIME_MSB_REG (0x27 << MEM_MAP_SHIFT)
@@ -177,9 +193,11 @@
/* FIFO Digital In Status RO register */
#define FIFO_DIN_STATUS_REG (0x3B << MEM_MAP_SHIFT)
#define FIFO_DIN_STATUS_FIFO_FULL_OFST (30)
#define FIFO_DIN_STATUS_FIFO_FULL_MSK (0x00000001 << FIFO_DIN_STATUS_FIFO_FULL_OFST)
#define FIFO_DIN_STATUS_FIFO_FULL_MSK \
(0x00000001 << FIFO_DIN_STATUS_FIFO_FULL_OFST)
#define FIFO_DIN_STATUS_FIFO_EMPTY_OFST (31)
#define FIFO_DIN_STATUS_FIFO_EMPTY_MSK (0x00000001 << FIFO_DIN_STATUS_FIFO_EMPTY_OFST)
#define FIFO_DIN_STATUS_FIFO_EMPTY_MSK \
(0x00000001 << FIFO_DIN_STATUS_FIFO_EMPTY_OFST)
/* FIFO Digital In 64 bit RO register */
#define FIFO_DIN_LSB_REG (0x3C << MEM_MAP_SHIFT)
@@ -243,9 +261,11 @@
#define DUMMY_FIFO_CHNNL_SLCT_OFST (0)
#define DUMMY_FIFO_CHNNL_SLCT_MSK (0x0000003F << DUMMY_FIFO_CHNNL_SLCT_OFST)
#define DUMMY_ANLG_FIFO_RD_STRBE_OFST (8)
#define DUMMY_ANLG_FIFO_RD_STRBE_MSK (0x00000001 << DUMMY_ANLG_FIFO_RD_STRBE_OFST)
#define DUMMY_ANLG_FIFO_RD_STRBE_MSK \
(0x00000001 << DUMMY_ANLG_FIFO_RD_STRBE_OFST)
#define DUMMY_DGTL_FIFO_RD_STRBE_OFST (9)
#define DUMMY_DGTL_FIFO_RD_STRBE_MSK (0x00000001 << DUMMY_DGTL_FIFO_RD_STRBE_OFST)
#define DUMMY_DGTL_FIFO_RD_STRBE_MSK \
(0x00000001 << DUMMY_DGTL_FIFO_RD_STRBE_OFST)
/* Receiver IP Address RW register */
#define RX_IP_REG (0x45 << MEM_MAP_SHIFT)
@@ -313,21 +333,23 @@
#define CONTROL_STP_ACQSTN_OFST (1)
#define CONTROL_STP_ACQSTN_MSK (0x00000001 << CONTROL_STP_ACQSTN_OFST)
//#define CONTROL_STRT_FF_TST_OFST (2)
//#define CONTROL_STRT_FF_TST_MSK (0x00000001 << CONTROL_STRT_FF_TST_OFST)
//#define CONTROL_STP_FF_TST_OFST (3)
//#define CONTROL_STP_FF_TST_MSK (0x00000001 << CONTROL_STP_FF_TST_OFST)
//#define CONTROL_STRT_RDT_OFST (4)
//#define CONTROL_STRT_RDT_MSK (0x00000001 << CONTROL_STRT_RDT_OFST)
//#define CONTROL_STP_RDT_OFST (5)
//#define CONTROL_STP_RDT_MSK (0x00000001 << CONTROL_STP_RDT_OFST)
//#define CONTROL_STRT_FF_TST_MSK (0x00000001 <<
// CONTROL_STRT_FF_TST_OFST) #define CONTROL_STP_FF_TST_OFST (3)
//#define CONTROL_STP_FF_TST_MSK (0x00000001 <<
// CONTROL_STP_FF_TST_OFST) #define CONTROL_STRT_RDT_OFST (4)
//#define CONTROL_STRT_RDT_MSK (0x00000001 <<
// CONTROL_STRT_RDT_OFST) #define CONTROL_STP_RDT_OFST (5)
// #define CONTROL_STP_RDT_MSK (0x00000001 <<
// CONTROL_STP_RDT_OFST)
#define CONTROL_STRT_EXPSR_OFST (6)
#define CONTROL_STRT_EXPSR_MSK (0x00000001 << CONTROL_STRT_EXPSR_OFST)
//#define CONTROL_STP_EXPSR_OFST (7)
//#define CONTROL_STP_EXPSR_MSK (0x00000001 << CONTROL_STP_RDT_OFST)
//#define CONTROL_STRT_TRN_OFST (8)
//#define CONTROL_STRT_TRN_MSK (0x00000001 << CONTROL_STRT_RDT_OFST)
//#define CONTROL_STP_EXPSR_MSK (0x00000001 <<
// CONTROL_STP_RDT_OFST) #define CONTROL_STRT_TRN_OFST (8) #define
// CONTROL_STRT_TRN_MSK (0x00000001 << CONTROL_STRT_RDT_OFST)
//#define CONTROL_STP_TRN_OFST (9)
//#define CONTROL_STP_TRN_MSK (0x00000001 << CONTROL_STP_RDT_OFST)
//#define CONTROL_STP_TRN_MSK (0x00000001 <<
// CONTROL_STP_RDT_OFST)
#define CONTROL_CRE_RST_OFST (10)
#define CONTROL_CRE_RST_MSK (0x00000001 << CONTROL_CRE_RST_OFST)
#define CONTROL_PRPHRL_RST_OFST (11) // Only GBE10?
@@ -335,7 +357,8 @@
#define CONTROL_MMRY_RST_OFST (12)
#define CONTROL_MMRY_RST_MSK (0x00000001 << CONTROL_MMRY_RST_OFST)
//#define CONTROL_PLL_RCNFG_WR_OFST (13)
//#define CONTROL_PLL_RCNFG_WR_MSK (0x00000001 << CONTROL_PLL_RCNFG_WR_OFST)
//#define CONTROL_PLL_RCNFG_WR_MSK (0x00000001 <<
// CONTROL_PLL_RCNFG_WR_OFST)
#define CONTROL_SND_10GB_PCKT_OFST (14)
#define CONTROL_SND_10GB_PCKT_MSK (0x00000001 << CONTROL_SND_10GB_PCKT_OFST)
#define CONTROL_CLR_ACQSTN_FIFO_OFST (15)
@@ -348,7 +371,8 @@
#define PLL_CNTRL_REG (0x51 << MEM_MAP_SHIFT)
#define PLL_CNTRL_RCNFG_PRMTR_RST_OFST (0)
#define PLL_CNTRL_RCNFG_PRMTR_RST_MSK (0x00000001 << PLL_CNTRL_RCNFG_PRMTR_RST_OFST)
#define PLL_CNTRL_RCNFG_PRMTR_RST_MSK \
(0x00000001 << PLL_CNTRL_RCNFG_PRMTR_RST_OFST)
#define PLL_CNTRL_WR_PRMTR_OFST (2)
#define PLL_CNTRL_WR_PRMTR_MSK (0x00000001 << PLL_CNTRL_WR_PRMTR_OFST)
#define PLL_CNTRL_PLL_RST_OFST (3)
@@ -378,7 +402,8 @@
#define PATTERN_LOOP_0_ADDR_REG (0x54 << MEM_MAP_SHIFT)
#define PATTERN_LOOP_0_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_0_ADDR_STRT_MSK (0x00001FFF << PATTERN_LOOP_0_ADDR_STRT_OFST)
#define PATTERN_LOOP_0_ADDR_STRT_MSK \
(0x00001FFF << PATTERN_LOOP_0_ADDR_STRT_OFST)
#define PATTERN_LOOP_0_ADDR_STP_OFST (16)
#define PATTERN_LOOP_0_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_0_ADDR_STP_OFST)
@@ -389,7 +414,8 @@
#define PATTERN_LOOP_1_ADDR_REG (0x56 << MEM_MAP_SHIFT)
#define PATTERN_LOOP_1_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_1_ADDR_STRT_MSK (0x00001FFF << PATTERN_LOOP_1_ADDR_STRT_OFST)
#define PATTERN_LOOP_1_ADDR_STRT_MSK \
(0x00001FFF << PATTERN_LOOP_1_ADDR_STRT_OFST)
#define PATTERN_LOOP_1_ADDR_STP_OFST (16)
#define PATTERN_LOOP_1_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_1_ADDR_STP_OFST)
@@ -400,7 +426,8 @@
#define PATTERN_LOOP_2_ADDR_REG (0x58 << MEM_MAP_SHIFT)
#define PATTERN_LOOP_2_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_2_ADDR_STRT_MSK (0x00001FFF << PATTERN_LOOP_2_ADDR_STRT_OFST)
#define PATTERN_LOOP_2_ADDR_STRT_MSK \
(0x00001FFF << PATTERN_LOOP_2_ADDR_STRT_OFST)
#define PATTERN_LOOP_2_ADDR_STP_OFST (16)
#define PATTERN_LOOP_2_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_2_ADDR_STP_OFST)
@@ -412,7 +439,7 @@
#define PATTERN_WAIT_0_ADDR_OFST (0)
#define PATTERN_WAIT_0_ADDR_MSK (0x00001FFF << PATTERN_WAIT_0_ADDR_OFST)
//FIXME: is mask 3FF
// FIXME: is mask 3FF
/* Pattern Wait 1 RW regiser */
#define PATTERN_WAIT_1_ADDR_REG (0x5B << MEM_MAP_SHIFT)
@@ -445,7 +472,6 @@
/* Number of Words RW register TODO */
#define NUMBER_OF_WORDS_REG (0x5F << MEM_MAP_SHIFT)
/* Delay 64 bit RW register. t = DLY x 50 ns. */
#define DELAY_LSB_REG (0x60 << MEM_MAP_SHIFT)
#define DELAY_MSB_REG (0x61 << MEM_MAP_SHIFT)
@@ -463,12 +489,14 @@
#define PERIOD_MSB_REG (0x67 << MEM_MAP_SHIFT)
/* Period 64 bit RW register */
//#define EXPTIME_LSB_REG (0x68 << MEM_MAP_SHIFT) // Not used in FW
//#define EXPTIME_MSB_REG (0x69 << MEM_MAP_SHIFT) // Not used in FW
//#define EXPTIME_LSB_REG (0x68 << MEM_MAP_SHIFT) //
// Not used in FW #define EXPTIME_MSB_REG (0x69 <<
// MEM_MAP_SHIFT) // Not used in FW
/* Gates 64 bit RW register */
//#define GATES_LSB_REG (0x6A << MEM_MAP_SHIFT) // Not used in FW
//#define GATES_MSB_REG (0x6B << MEM_MAP_SHIFT) // Not used in FW
//#define GATES_LSB_REG (0x6A << MEM_MAP_SHIFT) // Not used
// in FW #define GATES_MSB_REG (0x6B << MEM_MAP_SHIFT) //
// Not used in FW
/* Pattern IO Control 64 bit RW regiser
* Each bit configured as output(1)/ input(0) */
@@ -505,7 +533,6 @@
#define READOUT_10G_ENABLE_DGTL_OFST (8)
#define READOUT_10G_ENABLE_DGTL_MSK (0x00000001 << READOUT_10G_ENABLE_DGTL_OFST)
/* Digital Bit External Trigger RW register */
#define DBIT_EXT_TRG_REG (0x7B << MEM_MAP_SHIFT)
@@ -517,11 +544,15 @@
/* Pin Delay 0 RW register */
#define OUTPUT_DELAY_0_REG (0x7C << MEM_MAP_SHIFT)
#define OUTPUT_DELAY_0_OTPT_STTNG_STEPS (25)
#define OUTPUT_DELAY_0_OTPT_STTNG_OFST (0) //t = OTPT_STTNG * 25 ps, max for Cyclone V = 775 ps
#define OUTPUT_DELAY_0_OTPT_STTNG_MSK (0x0000001F << OUTPUT_DELAY_0_OTPT_STTNG_OFST)
// 1: load dynamic output settings, 0: trigger start of dynamic output delay configuration pn falling edge of ODT (output delay trigger) bit
#define OUTPUT_DELAY_0_OTPT_STTNG_OFST \
(0) // t = OTPT_STTNG * 25 ps, max for Cyclone V = 775 ps
#define OUTPUT_DELAY_0_OTPT_STTNG_MSK \
(0x0000001F << OUTPUT_DELAY_0_OTPT_STTNG_OFST)
// 1: load dynamic output settings, 0: trigger start of dynamic output delay
// configuration pn falling edge of ODT (output delay trigger) bit
#define OUTPUT_DELAY_0_OTPT_TRGGR_OFST (31)
#define OUTPUT_DELAY_0_OTPT_TRGGR_MSK (0x00000001 << OUTPUT_DELAY_0_OTPT_TRGGR_OFST)
#define OUTPUT_DELAY_0_OTPT_TRGGR_MSK \
(0x00000001 << OUTPUT_DELAY_0_OTPT_TRGGR_OFST)
#define OUTPUT_DELAY_0_OTPT_TRGGR_LD_VAL (1)
#define OUTPUT_DELAY_0_OTPT_TRGGR_STRT_VAL (0)
@@ -546,10 +577,7 @@
#define I2C_SCL_LOW_COUNT_REG (0x108 << MEM_MAP_SHIFT)
#define I2C_SCL_HIGH_COUNT_REG (0x109 << MEM_MAP_SHIFT)
#define I2C_SDA_HOLD_REG (0x10A << MEM_MAP_SHIFT)
//fixme: upto 0x10f
// fixme: upto 0x10f
/* Round Robin */
#define RXR_ENDPOINT_START_REG (0x1000 << MEM_MAP_SHIFT)

851
slsDetectorServers/ctbDetectorServer/slsDetectorFunctionList.c Executable file → Normal file
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File diff suppressed because it is too large Load Diff

74
slsDetectorServers/ctbDetectorServer/slsDetectorServer_defs.h Executable file → Normal file
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@@ -1,7 +1,6 @@
#pragma once
#include "sls_detector_defs.h"
#include "RegisterDefs.h"
#include "sls_detector_defs.h"
#define MIN_REQRD_VRSN_T_RD_API 0x181130
#define REQRD_FRMWR_VRSN 0x191127
@@ -15,13 +14,13 @@ typedef struct udp_header_struct {
uint16_t udp_destmac_lsb;
uint32_t udp_srcmac_lsb;
uint8_t ip_tos;
uint8_t ip_ihl: 4, ip_ver: 4;
uint8_t ip_ihl : 4, ip_ver : 4;
uint16_t udp_ethertype;
uint16_t ip_identification;
uint16_t ip_totallength;
uint8_t ip_protocol;
uint8_t ip_ttl;
uint16_t ip_fragmentoffset: 13, ip_flags: 3;
uint16_t ip_fragmentoffset : 13, ip_flags : 3;
uint16_t ip_srcip_msb;
uint16_t ip_checksum;
uint16_t ip_destip_msb;
@@ -36,11 +35,54 @@ typedef struct udp_header_struct {
#define UDP_IP_HEADER_LENGTH_BYTES (28)
/* Enums */
enum ADCINDEX {V_PWR_IO, V_PWR_A, V_PWR_B, V_PWR_C, V_PWR_D, I_PWR_IO, I_PWR_A, I_PWR_B, I_PWR_C, I_PWR_D, S_ADC0, S_ADC1, S_ADC2, S_ADC3, S_ADC4, S_ADC5, S_ADC6, S_ADC7, S_TMP};
enum DACINDEX {D0, D1, D2, D3, D4, D5, D6, D7, D8, D9,
D10, D11, D12, D13, D14, D15, D16, D17,
D_PWR_D, D_PWR_CHIP, D_PWR_C, D_PWR_B, D_PWR_A, D_PWR_IO};
enum CLKINDEX {RUN_CLK, ADC_CLK, SYNC_CLK, DBIT_CLK, NUM_CLOCKS};
enum ADCINDEX {
V_PWR_IO,
V_PWR_A,
V_PWR_B,
V_PWR_C,
V_PWR_D,
I_PWR_IO,
I_PWR_A,
I_PWR_B,
I_PWR_C,
I_PWR_D,
S_ADC0,
S_ADC1,
S_ADC2,
S_ADC3,
S_ADC4,
S_ADC5,
S_ADC6,
S_ADC7,
S_TMP
};
enum DACINDEX {
D0,
D1,
D2,
D3,
D4,
D5,
D6,
D7,
D8,
D9,
D10,
D11,
D12,
D13,
D14,
D15,
D16,
D17,
D_PWR_D,
D_PWR_CHIP,
D_PWR_C,
D_PWR_B,
D_PWR_A,
D_PWR_IO
};
enum CLKINDEX { RUN_CLK, ADC_CLK, SYNC_CLK, DBIT_CLK, NUM_CLOCKS };
#define CLK_NAMES "run", "adc", "sync", "dbit"
/* Hardware Definitions */
@@ -67,7 +109,7 @@ enum CLKINDEX {RUN_CLK, ADC_CLK, SYNC_CLK, DBIT_CLK, NUM_CLOCKS};
#define DEFAULT_NUM_FRAMES (1)
#define DEFAULT_EXPTIME (0)
#define DEFAULT_NUM_CYCLES (1)
#define DEFAULT_PERIOD (1 * 1000 * 1000) //ns
#define DEFAULT_PERIOD (1 * 1000 * 1000) // ns
#define DEFAULT_DELAY (0)
#define DEFAULT_HIGH_VOLTAGE (0)
#define DEFAULT_VLIMIT (-100)
@@ -85,16 +127,21 @@ enum CLKINDEX {RUN_CLK, ADC_CLK, SYNC_CLK, DBIT_CLK, NUM_CLOCKS};
#define VCHIP_MIN_MV (1673)
#define VCHIP_MAX_MV (2668) // min dac val
#define POWER_RGLTR_MIN (636)
#define POWER_RGLTR_MAX (2638) // min dac val (not vchip-max) because of dac conversions
#define POWER_RGLTR_MAX \
(2638) // min dac val (not vchip-max) because of dac conversions
#define VCHIP_POWER_INCRMNT (200)
#define VIO_MIN_MV (1200) // for fpga to function
/* Defines in the Firmware */
#define MAX_PATTERN_LENGTH (0x2000)
#define DIGITAL_IO_DELAY_MAXIMUM_PS ((OUTPUT_DELAY_0_OTPT_STTNG_MSK >> OUTPUT_DELAY_0_OTPT_STTNG_OFST) * OUTPUT_DELAY_0_OTPT_STTNG_STEPS)
#define DIGITAL_IO_DELAY_MAXIMUM_PS \
((OUTPUT_DELAY_0_OTPT_STTNG_MSK >> OUTPUT_DELAY_0_OTPT_STTNG_OFST) * \
OUTPUT_DELAY_0_OTPT_STTNG_STEPS)
#define MAX_PHASE_SHIFTS_STEPS (8)
#define WAIT_TME_US_FR_ACQDONE_REG (100) // wait time in us after acquisition done to ensure there is no data in fifo
#define WAIT_TME_US_FR_ACQDONE_REG \
(100) // wait time in us after acquisition done to ensure there is no data
// in fifo
#define WAIT_TIME_US_PLL (10 * 1000)
#define WAIT_TIME_US_STP_ACQ (100)
#define WAIT_TIME_CONFIGURE_MAC (2 * 1000 * 1000)
@@ -109,4 +156,3 @@ enum CLKINDEX {RUN_CLK, ADC_CLK, SYNC_CLK, DBIT_CLK, NUM_CLOCKS};
#define MAXIMUM_ADC_CLK (65)
#define PLL_VCO_FREQ_MHZ (800)

135
slsDetectorServers/eigerDetectorServer/9mhvserial_bf.c Executable file → Normal file
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@@ -1,14 +1,14 @@
#include "ansi.h"
#include <termios.h> /* POSIX terminal control definitions */
#include <errno.h>
#include <fcntl.h> // File control definitions
#include <linux/i2c-dev.h> // I2C_SLAVE, __u8 reg
#include <stdio.h>
#include <stdlib.h> // atoi
#include <fcntl.h> // File control definitions
#include <sys/ioctl.h> // ioctl
#include <unistd.h> // read, close
#include <string.h> // memset
#include <linux/i2c-dev.h> // I2C_SLAVE, __u8 reg
#include <errno.h>
#include <sys/ioctl.h> // ioctl
#include <termios.h> /* POSIX terminal control definitions */
#include <unistd.h> // read, close
#define PORTNAME "/dev/ttyBF1"
#define GOODBYE 200
@@ -18,43 +18,41 @@
//#define I2C_DEVICE_ADDRESS 0x48
#define I2C_REGISTER_ADDRESS 0x40
int i2c_open(const char *file, unsigned int addr) {
int i2c_open(const char* file,unsigned int addr){
//device file
int fd = open( file, O_RDWR );
// device file
int fd = open(file, O_RDWR);
if (fd < 0) {
LOG(logERROR, ("Warning: Unable to open file %s\n",file));
LOG(logERROR, ("Warning: Unable to open file %s\n", file));
return -1;
}
//device address
if( ioctl( fd, I2C_SLAVE, addr&0x7F ) < 0 ) {
LOG(logERROR, ("Warning: Unable to set slave address:0x%x \n",addr));
// device address
if (ioctl(fd, I2C_SLAVE, addr & 0x7F) < 0) {
LOG(logERROR, ("Warning: Unable to set slave address:0x%x \n", addr));
return -2;
}
return fd;
}
int i2c_read(){
int i2c_read() {
int fd = i2c_open(I2C_DEVICE_FILE, I2C_DEVICE_ADDRESS);
__u8 reg = I2C_REGISTER_ADDRESS & 0xff;
unsigned char buf = reg;
if (write(fd, &buf, 1)!= 1){
LOG(logERROR, ("Warning: Unable to write read request to register %d\n", reg));
if (write(fd, &buf, 1) != 1) {
LOG(logERROR,
("Warning: Unable to write read request to register %d\n", reg));
return -1;
}
//read and update value (but old value read out)
if(read(fd, &buf, 1) != 1){
// read and update value (but old value read out)
if (read(fd, &buf, 1) != 1) {
LOG(logERROR, ("Warning: Unable to read register %d\n", reg));
return -2;
}
//read again to read the updated value
if(read(fd, &buf, 1) != 1){
// read again to read the updated value
if (read(fd, &buf, 1) != 1) {
LOG(logERROR, ("Warning: Unable to read register %d\n", reg));
return -2;
}
@@ -62,13 +60,12 @@ int i2c_read(){
return buf;
}
int i2c_write(unsigned int value){
int i2c_write(unsigned int value) {
__u8 val = value & 0xff;
int fd = i2c_open(I2C_DEVICE_FILE, I2C_DEVICE_ADDRESS);
if(fd < 0)
if (fd < 0)
return fd;
__u8 reg = I2C_REGISTER_ADDRESS & 0xff;
@@ -76,7 +73,8 @@ int i2c_write(unsigned int value){
buf[0] = reg;
buf[1] = val;
if (write(fd, buf, 2) != 2) {
LOG(logERROR, ("Warning: Unable to write %d to register %d\n",val, reg));
LOG(logERROR,
("Warning: Unable to write %d to register %d\n", val, reg));
return -1;
}
@@ -84,22 +82,18 @@ int i2c_write(unsigned int value){
return 0;
}
int main(int argc, char* argv[]) {
int main(int argc, char *argv[]) {
int fd = open(PORTNAME, O_RDWR | O_NOCTTY | O_SYNC);
if(fd < 0){
if (fd < 0) {
LOG(logERROR, ("Warning: Unable to open port %s\n", PORTNAME));
return -1;
}
LOG(logINFO, ("opened port at %s\n",PORTNAME));
LOG(logINFO, ("opened port at %s\n", PORTNAME));
struct termios serial_conf;
// reset structure
memset(&serial_conf,0,sizeof(serial_conf));
memset(&serial_conf, 0, sizeof(serial_conf));
// control options
serial_conf.c_cflag = B2400 | CS8 | CREAD | CLOCAL;
// input options
@@ -109,37 +103,37 @@ int main(int argc, char* argv[]) {
// line options
serial_conf.c_lflag = ICANON;
// flush input
if(tcflush(fd, TCIOFLUSH) < 0){
if (tcflush(fd, TCIOFLUSH) < 0) {
LOG(logERROR, ("Warning: error form tcflush %d\n", errno));
return 0;
}
// set new options for the port, TCSANOW:changes occur immediately without waiting for data to complete
if(tcsetattr(fd, TCSANOW, &serial_conf) < 0){
// set new options for the port, TCSANOW:changes occur immediately without
// waiting for data to complete
if (tcsetattr(fd, TCSANOW, &serial_conf) < 0) {
LOG(logERROR, ("Warning: error form tcsetattr %d\n", errno));
return 0;
}
if(tcsetattr(fd, TCSAFLUSH, &serial_conf) < 0){
if (tcsetattr(fd, TCSAFLUSH, &serial_conf) < 0) {
LOG(logERROR, ("Warning: error form tcsetattr %d\n", errno));
return 0;
}
int ret = 0;
int n = 0;
int ival= 0;
int ival = 0;
char buffer[BUFFERSIZE];
memset(buffer,0,BUFFERSIZE);
buffer[BUFFERSIZE-1] = '\n';
memset(buffer, 0, BUFFERSIZE);
buffer[BUFFERSIZE - 1] = '\n';
LOG(logINFO, ("Ready...\n"));
while(ret != GOODBYE){
memset(buffer,0,BUFFERSIZE);
n = read(fd,buffer,BUFFERSIZE);
while (ret != GOODBYE) {
memset(buffer, 0, BUFFERSIZE);
n = read(fd, buffer, BUFFERSIZE);
LOG(logDEBUG1, ("Received %d Bytes\n", n));
LOG(logINFO, ("Got message: '%s'\n",buffer));
LOG(logINFO, ("Got message: '%s'\n", buffer));
switch(buffer[0]){
switch (buffer[0]) {
case '\0':
LOG(logINFO, ("Got Start (Detector restart)\n"));
break;
@@ -147,43 +141,44 @@ int main(int argc, char* argv[]) {
LOG(logINFO, ("Got Start \n"));
break;
case 'p':
if (!sscanf(&buffer[1],"%d",&ival)){
if (!sscanf(&buffer[1], "%d", &ival)) {
LOG(logERROR, ("Warning: cannot scan voltage value\n"));
break;
}
// ok/ fail
memset(buffer,0,BUFFERSIZE);
buffer[BUFFERSIZE-1] = '\n';
if(i2c_write(ival)<0)
strcpy(buffer,"fail ");
memset(buffer, 0, BUFFERSIZE);
buffer[BUFFERSIZE - 1] = '\n';
if (i2c_write(ival) < 0)
strcpy(buffer, "fail ");
else
strcpy(buffer,"success ");
LOG(logINFO, ("Sending: '%s'\n",buffer));
strcpy(buffer, "success ");
LOG(logINFO, ("Sending: '%s'\n", buffer));
n = write(fd, buffer, BUFFERSIZE);
LOG(logDEBUG1, ("Sent %d Bytes\n", n));
break;
case 'g':
ival = i2c_read();
//ok/ fail
memset(buffer,0,BUFFERSIZE);
buffer[BUFFERSIZE-1] = '\n';
if(ival < 0)
strcpy(buffer,"fail ");
// ok/ fail
memset(buffer, 0, BUFFERSIZE);
buffer[BUFFERSIZE - 1] = '\n';
if (ival < 0)
strcpy(buffer, "fail ");
else
strcpy(buffer,"success ");
strcpy(buffer, "success ");
n = write(fd, buffer, BUFFERSIZE);
LOG(logINFO, ("Sending: '%s'\n",buffer));
LOG(logINFO, ("Sending: '%s'\n", buffer));
LOG(logDEBUG1, ("Sent %d Bytes\n", n));
//value
memset(buffer,0,BUFFERSIZE);
buffer[BUFFERSIZE-1] = '\n';
if(ival >= 0){
LOG(logINFO, ("Sending: '%d'\n",ival));
sprintf(buffer,"%d ",ival);
// value
memset(buffer, 0, BUFFERSIZE);
buffer[BUFFERSIZE - 1] = '\n';
if (ival >= 0) {
LOG(logINFO, ("Sending: '%d'\n", ival));
sprintf(buffer, "%d ", ival);
n = write(fd, buffer, BUFFERSIZE);
LOG(logINFO, ("Sent %d Bytes\n", n));
}else LOG(logERROR, ("%s\n",buffer));
} else
LOG(logERROR, ("%s\n", buffer));
break;
case 'e':
@@ -191,7 +186,7 @@ int main(int argc, char* argv[]) {
ret = GOODBYE;
break;
default:
LOG(logERROR, ("Unknown Command. buffer:'%s'\n",buffer));
LOG(logERROR, ("Unknown Command. buffer:'%s'\n", buffer));
break;
}
}

1184
slsDetectorServers/eigerDetectorServer/Beb.c Executable file → Normal file
View File

File diff suppressed because it is too large Load Diff

87
slsDetectorServers/eigerDetectorServer/Beb.h Executable file → Normal file
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@@ -1,11 +1,9 @@
#pragma once
#include "LocalLinkInterface.h"
#include "slsDetectorServer_defs.h"
struct BebInfo{
struct BebInfo {
unsigned int beb_number;
unsigned int serial_address;
char src_mac_1GbE[50];
@@ -16,25 +14,26 @@ struct BebInfo{
unsigned int src_port_10GbE;
};
void BebInfo_BebInfo(struct BebInfo* bebInfo, unsigned int beb_num);
void BebInfo_BebDstInfo(struct BebInfo* bebInfo, unsigned int beb_num);
int BebInfo_SetSerialAddress(struct BebInfo* bebInfo, unsigned int add);
int BebInfo_SetHeaderInfo(struct BebInfo* bebInfo, int ten_gig, char* src_mac, char* src_ip, unsigned int src_port);//src_port fixed 42000+beb_number or 52000 + beb_number);
unsigned int BebInfo_GetBebNumber(struct BebInfo* bebInfo);
unsigned int BebInfo_GetSerialAddress(struct BebInfo* bebInfo);
char* BebInfo_GetSrcMAC(struct BebInfo* bebInfo, int ten_gig);
char* BebInfo_GetSrcIP(struct BebInfo* bebInfo, int ten_gig);
unsigned int BebInfo_GetSrcPort(struct BebInfo* bebInfo, int ten_gig);
void BebInfo_Print(struct BebInfo* bebInfo);
void BebInfo_BebInfo(struct BebInfo *bebInfo, unsigned int beb_num);
void BebInfo_BebDstInfo(struct BebInfo *bebInfo, unsigned int beb_num);
int BebInfo_SetSerialAddress(struct BebInfo *bebInfo, unsigned int add);
int BebInfo_SetHeaderInfo(
struct BebInfo *bebInfo, int ten_gig, char *src_mac, char *src_ip,
unsigned int
src_port); // src_port fixed 42000+beb_number or 52000 + beb_number);
unsigned int BebInfo_GetBebNumber(struct BebInfo *bebInfo);
unsigned int BebInfo_GetSerialAddress(struct BebInfo *bebInfo);
char *BebInfo_GetSrcMAC(struct BebInfo *bebInfo, int ten_gig);
char *BebInfo_GetSrcIP(struct BebInfo *bebInfo, int ten_gig);
unsigned int BebInfo_GetSrcPort(struct BebInfo *bebInfo, int ten_gig);
void BebInfo_Print(struct BebInfo *bebInfo);
void Beb_ClearBebInfos();
int Beb_InitBebInfos();
int Beb_CheckSourceStuffBebInfo();
unsigned int Beb_GetBebInfoIndex(unsigned int beb_numb);
void Beb_GetModuleConfiguration(int* master, int* top, int* normal);
int Beb_IsTransmitting(int* retval, int tengiga, int waitForDelay);
void Beb_GetModuleConfiguration(int *master, int *top, int *normal);
int Beb_IsTransmitting(int *retval, int tengiga, int waitForDelay);
int Beb_SetMasterViaSoftware();
int Beb_SetSlaveViaSoftware();
@@ -56,27 +55,43 @@ u_int32_t Beb_GetFirmwareRevision();
u_int32_t Beb_GetFirmwareSoftwareAPIVersion();
void Beb_ResetFrameNumber();
int Beb_WriteTo(unsigned int index);
int Beb_SetMAC(char* mac, uint8_t* dst_ptr);
int Beb_SetIP(char* ip, uint8_t* dst_ptr);
int Beb_SetPortNumber(unsigned int port_number, uint8_t* dst_ptr);
int Beb_SetMAC(char *mac, uint8_t *dst_ptr);
int Beb_SetIP(char *ip, uint8_t *dst_ptr);
int Beb_SetPortNumber(unsigned int port_number, uint8_t *dst_ptr);
void Beb_AdjustIPChecksum(struct udp_header_type *ip);
int Beb_SetHeaderData(unsigned int beb_number, int ten_gig, char* dst_mac, char* dst_ip, unsigned int dst_port);
int Beb_SetHeaderData1(char* src_mac, char* src_ip, unsigned int src_port, char* dst_mac, char* dst_ip, unsigned int dst_port);
int Beb_SetHeaderData(unsigned int beb_number, int ten_gig, char *dst_mac,
char *dst_ip, unsigned int dst_port);
int Beb_SetHeaderData1(char *src_mac, char *src_ip, unsigned int src_port,
char *dst_mac, char *dst_ip, unsigned int dst_port);
void Beb_SwapDataFun(int little_endian, unsigned int n, unsigned int *d);
int Beb_SetByteOrder();
void Beb_Beb();
int Beb_SetBebSrcHeaderInfos(unsigned int beb_number, int ten_gig, char* src_mac, char* src_ip, unsigned int src_port);
int Beb_SetUpUDPHeader(unsigned int beb_number, int ten_gig, unsigned int header_number, char* dst_mac, char* dst_ip, unsigned int dst_port);
int Beb_SetBebSrcHeaderInfos(unsigned int beb_number, int ten_gig,
char *src_mac, char *src_ip,
unsigned int src_port);
int Beb_SetUpUDPHeader(unsigned int beb_number, int ten_gig,
unsigned int header_number, char *dst_mac, char *dst_ip,
unsigned int dst_port);
/*int Beb_SendMultiReadRequest(unsigned int beb_number, unsigned int left_right, int ten_gig, unsigned int dst_number, unsigned int npackets, unsigned int packet_size, int stop_read_when_fifo_empty=1);*/
int Beb_SendMultiReadRequest(unsigned int beb_number, unsigned int left_right, int ten_gig, unsigned int dst_number, unsigned int npackets, unsigned int packet_size, int stop_read_when_fifo_empty);
/*int Beb_SendMultiReadRequest(unsigned int beb_number, unsigned int
* left_right, int ten_gig, unsigned int dst_number, unsigned int npackets,
* unsigned int packet_size, int stop_read_when_fifo_empty=1);*/
int Beb_SendMultiReadRequest(unsigned int beb_number, unsigned int left_right,
int ten_gig, unsigned int dst_number,
unsigned int npackets, unsigned int packet_size,
int stop_read_when_fifo_empty);
int Beb_StopAcquisition();
int Beb_SetUpTransferParameters(short the_bit_mode);
/*int Beb_RequestNImages(unsigned int beb_number, unsigned int left_right, int ten_gig, unsigned int dst_number, unsigned int nimages, int test_just_send_out_packets_no_wait=0); //all images go to the same destination!*/
int Beb_RequestNImages(unsigned int beb_number, int ten_gig, unsigned int dst_number, unsigned int nimages, int test_just_send_out_packets_no_wait);
/*int Beb_RequestNImages(unsigned int beb_number, unsigned int left_right, int
* ten_gig, unsigned int dst_number, unsigned int nimages, int
* test_just_send_out_packets_no_wait=0); //all images go to the same
* destination!*/
int Beb_RequestNImages(unsigned int beb_number, int ten_gig,
unsigned int dst_number, unsigned int nimages,
int test_just_send_out_packets_no_wait);
int Beb_Test(unsigned int beb_number);
@@ -85,17 +100,15 @@ int Beb_GetBebFPGATemp();
void Beb_SetDetectorNumber(uint32_t detid);
int Beb_SetQuad(int value);
int Beb_GetQuad();
int* Beb_GetDetectorPosition();
int *Beb_GetDetectorPosition();
int Beb_SetDetectorPosition(int pos[]);
int Beb_SetStartingFrameNumber(uint64_t value);
int Beb_GetStartingFrameNumber(uint64_t* retval, int tengigaEnable);
int Beb_GetStartingFrameNumber(uint64_t *retval, int tengigaEnable);
void Beb_SetReadNLines(int value);
uint16_t Beb_swap_uint16( uint16_t val);
int Beb_open(u_int32_t** csp0base, u_int32_t offset);
u_int32_t Beb_Read32 (u_int32_t* baseaddr, u_int32_t offset);
u_int32_t Beb_Write32 (u_int32_t* baseaddr, u_int32_t offset, u_int32_t data);
void Beb_close(int fd,u_int32_t* csp0base);
uint16_t Beb_swap_uint16(uint16_t val);
int Beb_open(u_int32_t **csp0base, u_int32_t offset);
u_int32_t Beb_Read32(u_int32_t *baseaddr, u_int32_t offset);
u_int32_t Beb_Write32(u_int32_t *baseaddr, u_int32_t offset, u_int32_t data);
void Beb_close(int fd, u_int32_t *csp0base);

2013
slsDetectorServers/eigerDetectorServer/FebControl.c Executable file → Normal file
View File

File diff suppressed because it is too large Load Diff

132
slsDetectorServers/eigerDetectorServer/FebControl.h Executable file → Normal file
View File

@@ -2,8 +2,7 @@
#include "FebInterface.h"
#include <netinet/in.h>
struct Module{
struct Module {
unsigned int module_number;
int top_address_valid;
unsigned int top_left_address;
@@ -12,39 +11,42 @@ struct Module{
unsigned int bottom_left_address;
unsigned int bottom_right_address;
unsigned int idelay_top[4]; //ll,lr,rl,ll
unsigned int idelay_bottom[4]; //ll,lr,rl,ll
unsigned int idelay_top[4]; // ll,lr,rl,ll
unsigned int idelay_bottom[4]; // ll,lr,rl,ll
float high_voltage;
int* top_dac;
int* bottom_dac;
int *top_dac;
int *bottom_dac;
};
void Module_Module(struct Module *mod, unsigned int number,
unsigned int address_top);
void Module_ModuleBottom(struct Module *mod, unsigned int number,
unsigned int address_bottom);
void Module_Module1(struct Module *mod, unsigned int number,
unsigned int address_top, unsigned int address_bottom);
unsigned int Module_GetModuleNumber(struct Module *mod);
int Module_TopAddressIsValid(struct Module *mod);
unsigned int Module_GetTopBaseAddress(struct Module *mod);
unsigned int Module_GetTopLeftAddress(struct Module *mod);
unsigned int Module_GetTopRightAddress(struct Module *mod);
unsigned int Module_GetBottomBaseAddress(struct Module *mod);
int Module_BottomAddressIsValid(struct Module *mod);
unsigned int Module_GetBottomLeftAddress(struct Module *mod);
unsigned int Module_GetBottomRightAddress(struct Module *mod);
unsigned int Module_SetTopIDelay(struct Module *mod, unsigned int chip,
unsigned int value);
unsigned int Module_GetTopIDelay(struct Module *mod, unsigned int chip);
unsigned int Module_SetBottomIDelay(struct Module *mod, unsigned int chip,
unsigned int value);
unsigned int Module_GetBottomIDelay(struct Module *mod, unsigned int chip);
void Module_Module(struct Module* mod,unsigned int number, unsigned int address_top);
void Module_ModuleBottom(struct Module* mod,unsigned int number, unsigned int address_bottom);
void Module_Module1(struct Module* mod,unsigned int number, unsigned int address_top, unsigned int address_bottom);
unsigned int Module_GetModuleNumber(struct Module* mod);
int Module_TopAddressIsValid(struct Module* mod);
unsigned int Module_GetTopBaseAddress(struct Module* mod);
unsigned int Module_GetTopLeftAddress(struct Module* mod) ;
unsigned int Module_GetTopRightAddress(struct Module* mod);
unsigned int Module_GetBottomBaseAddress(struct Module* mod);
int Module_BottomAddressIsValid(struct Module* mod);
unsigned int Module_GetBottomLeftAddress(struct Module* mod);
unsigned int Module_GetBottomRightAddress(struct Module* mod);
unsigned int Module_SetTopIDelay(struct Module* mod,unsigned int chip,unsigned int value);
unsigned int Module_GetTopIDelay(struct Module* mod,unsigned int chip) ;
unsigned int Module_SetBottomIDelay(struct Module* mod,unsigned int chip,unsigned int value);
unsigned int Module_GetBottomIDelay(struct Module* mod,unsigned int chip);
float Module_SetHighVoltage(struct Module* mod,float value);
float Module_GetHighVoltage(struct Module* mod);
int Module_SetTopDACValue(struct Module* mod,unsigned int i, int value);
int Module_GetTopDACValue(struct Module* mod,unsigned int i);
int Module_SetBottomDACValue(struct Module* mod,unsigned int i, int value);
int Module_GetBottomDACValue(struct Module* mod,unsigned int i);
float Module_SetHighVoltage(struct Module *mod, float value);
float Module_GetHighVoltage(struct Module *mod);
int Module_SetTopDACValue(struct Module *mod, unsigned int i, int value);
int Module_GetTopDACValue(struct Module *mod, unsigned int i);
int Module_SetBottomDACValue(struct Module *mod, unsigned int i, int value);
int Module_GetBottomDACValue(struct Module *mod, unsigned int i);
void Feb_Control_activate(int activate);
@@ -52,22 +54,30 @@ int Feb_Control_IsBottomModule();
int Feb_Control_GetModuleNumber();
void Feb_Control_PrintModuleList();
int Feb_Control_GetModuleIndex(unsigned int module_number, unsigned int* module_index);
int Feb_Control_CheckModuleAddresses(struct Module* m);
int Feb_Control_GetModuleIndex(unsigned int module_number,
unsigned int *module_index);
int Feb_Control_CheckModuleAddresses(struct Module *m);
int Feb_Control_AddModule(unsigned int module_number, unsigned int top_address);
int Feb_Control_AddModule1(unsigned int module_number, int top_enable, unsigned int top_address, unsigned int bottom_address, int half_module);
int Feb_Control_GetDACNumber(char* s, unsigned int* n);
int Feb_Control_SendDACValue(unsigned int dst_num, unsigned int ch, unsigned int* value);
int Feb_Control_VoltageToDAC(float value, unsigned int* digital, unsigned int nsteps, float vmin, float vmax);
float Feb_Control_DACToVoltage(unsigned int digital,unsigned int nsteps,float vmin,float vmax);
int Feb_Control_SendIDelays(unsigned int dst_num, int chip_lr, unsigned int channels, unsigned int ndelay_units);
int Feb_Control_AddModule1(unsigned int module_number, int top_enable,
unsigned int top_address,
unsigned int bottom_address, int half_module);
int Feb_Control_GetDACNumber(char *s, unsigned int *n);
int Feb_Control_SendDACValue(unsigned int dst_num, unsigned int ch,
unsigned int *value);
int Feb_Control_VoltageToDAC(float value, unsigned int *digital,
unsigned int nsteps, float vmin, float vmax);
float Feb_Control_DACToVoltage(unsigned int digital, unsigned int nsteps,
float vmin, float vmax);
int Feb_Control_SendIDelays(unsigned int dst_num, int chip_lr,
unsigned int channels, unsigned int ndelay_units);
int Feb_Control_SetStaticBits();
int Feb_Control_SetStaticBits1(unsigned int the_static_bits);
int Feb_Control_SendBitModeToBebServer();
unsigned int Feb_Control_ConvertTimeToRegister(float time_in_sec);
unsigned int Feb_Control_AddressToAll();
int Feb_Control_SetCommandRegister(unsigned int cmd);
int Feb_Control_GetDAQStatusRegister(unsigned int dst_address, unsigned int* ret_status);
int Feb_Control_GetDAQStatusRegister(unsigned int dst_address,
unsigned int *ret_status);
int Feb_Control_StartDAQOnlyNWaitForFinish(int sleep_time_us);
int Feb_Control_ResetChipCompletely();
int Feb_Control_ResetChipPartially();
@@ -80,21 +90,24 @@ unsigned int Feb_Control_GetNModules();
unsigned int Feb_Control_GetNHalfModules();
int Feb_Control_SetHighVoltage(int value);
int Feb_Control_GetHighVoltage(int* value);
int Feb_Control_GetHighVoltage(int *value);
int Feb_Control_SendHighVoltage(int dacvalue);
int Feb_Control_ReceiveHighVoltage(unsigned int* value);
int Feb_Control_ReceiveHighVoltage(unsigned int *value);
int Feb_Control_SetIDelays(unsigned int module_num, unsigned int ndelay_units);
int Feb_Control_SetIDelays1(unsigned int module_num, unsigned int chip_pos, unsigned int ndelay_units);
int Feb_Control_SetIDelays1(unsigned int module_num, unsigned int chip_pos,
unsigned int ndelay_units);
int Feb_Control_DecodeDACString(char* dac_str, unsigned int* module_index, int* top, int* bottom, unsigned int* dac_ch);
int Feb_Control_SetDAC(char* s, int value, int is_a_voltage_mv);
int Feb_Control_GetDAC(char* s, int* ret_value, int voltage_mv);
int Feb_Control_GetDACName(unsigned int dac_num,char* s);
int Feb_Control_DecodeDACString(char *dac_str, unsigned int *module_index,
int *top, int *bottom, unsigned int *dac_ch);
int Feb_Control_SetDAC(char *s, int value, int is_a_voltage_mv);
int Feb_Control_GetDAC(char *s, int *ret_value, int voltage_mv);
int Feb_Control_GetDACName(unsigned int dac_num, char *s);
int Feb_Control_SetTrimbits(unsigned int module_num, unsigned int* trimbits, int top);
unsigned int* Feb_Control_GetTrimbits();
int Feb_Control_SetTrimbits(unsigned int module_num, unsigned int *trimbits,
int top);
unsigned int *Feb_Control_GetTrimbits();
int Feb_Control_SaveAllTrimbitsTo(int value, int top);
int Feb_Control_Reset();
int Feb_Control_PrepareForAcquisition();
@@ -111,7 +124,8 @@ unsigned int Feb_Control_GetNExposures();
int Feb_Control_SetExposureTime(double the_exposure_time_in_sec);
double Feb_Control_GetExposureTime();
int64_t Feb_Control_GetExposureTime_in_nsec();
int Feb_Control_SetSubFrameExposureTime(int64_t the_subframe_exposure_time_in_10nsec);
int Feb_Control_SetSubFrameExposureTime(
int64_t the_subframe_exposure_time_in_10nsec);
int64_t Feb_Control_GetSubFrameExposureTime();
int Feb_Control_SetSubFramePeriod(int64_t the_subframe_period_in_10nsec);
int64_t Feb_Control_GetSubFramePeriod();
@@ -119,17 +133,24 @@ int Feb_Control_SetExposurePeriod(double the_exposure_period_in_sec);
double Feb_Control_GetExposurePeriod();
int Feb_Control_SetDynamicRange(unsigned int four_eight_sixteen_or_thirtytwo);
unsigned int Feb_Control_GetDynamicRange();
int Feb_Control_SetReadoutSpeed(unsigned int readout_speed); //0 was default, 0->full,1->half,2->quarter or 3->super_slow
int Feb_Control_SetReadoutMode(unsigned int readout_mode); ///0 was default,0->parallel,1->non-parallel,2-> safe_mode
int Feb_Control_SetTriggerMode(unsigned int trigger_mode, int polarity);//0 and 1 was default,
int Feb_Control_SetExternalEnableMode(int use_external_enable, int polarity);//0 and 1 was default,
int Feb_Control_SetReadoutSpeed(
unsigned int readout_speed); // 0 was default, 0->full,1->half,2->quarter or
// 3->super_slow
int Feb_Control_SetReadoutMode(
unsigned int readout_mode); /// 0 was
/// default,0->parallel,1->non-parallel,2->
/// safe_mode
int Feb_Control_SetTriggerMode(unsigned int trigger_mode,
int polarity); // 0 and 1 was default,
int Feb_Control_SetExternalEnableMode(int use_external_enable,
int polarity); // 0 and 1 was default,
int Feb_Control_SetInTestModeVariable(int on);
int Feb_Control_GetTestModeVariable();
void Feb_Control_Set_Counter_Bit(int value);
int Feb_Control_Get_Counter_Bit();
int Feb_Control_Pulse_Pixel(int npulses,int x, int y);
int Feb_Control_Pulse_Pixel(int npulses, int x, int y);
int Feb_Control_PulsePixelNMove(int npulses, int inc_x_pos, int inc_y_pos);
int Feb_Control_Shift32InSerialIn(unsigned int value_to_shift_in);
int Feb_Control_SendTokenIn();
@@ -158,5 +179,4 @@ int Feb_Control_SetReadNLines(int value);
int Feb_Control_GetReadNLines();
int Feb_Control_WriteRegister(uint32_t offset, uint32_t data);
int Feb_Control_ReadRegister(uint32_t offset, uint32_t* retval);
int Feb_Control_ReadRegister(uint32_t offset, uint32_t *retval);

207
slsDetectorServers/eigerDetectorServer/FebInterface.c Executable file → Normal file
View File

@@ -1,27 +1,24 @@
#include "FebInterface.h"
#include "LocalLinkInterface.h"
#include "xparameters.h"
#include "clogger.h"
#include "xparameters.h"
#include <unistd.h>
struct LocalLinkInterface ll_local,* ll;
struct LocalLinkInterface ll_local, *ll;
unsigned int Feb_Interface_nfebs;
unsigned int* Feb_Interface_feb_numb;
unsigned int *Feb_Interface_feb_numb;
int Feb_Interface_send_ndata;
unsigned int Feb_Interface_send_buffer_size;
unsigned int* Feb_Interface_send_data_raw;
unsigned int* Feb_Interface_send_data;
unsigned int *Feb_Interface_send_data_raw;
unsigned int *Feb_Interface_send_data;
int Feb_Interface_recv_ndata;
unsigned int Feb_Interface_recv_buffer_size;
unsigned int* Feb_Interface_recv_data_raw;
unsigned int* Feb_Interface_recv_data;
unsigned int *Feb_Interface_recv_data_raw;
unsigned int *Feb_Interface_recv_data;
void Feb_Interface_FebInterface() {
ll = &ll_local;
@@ -30,166 +27,210 @@ void Feb_Interface_FebInterface() {
Feb_Interface_send_ndata = 0;
Feb_Interface_send_buffer_size = 1026;
Feb_Interface_send_data_raw = malloc((Feb_Interface_send_buffer_size+1) * sizeof(unsigned int));
Feb_Interface_send_data_raw =
malloc((Feb_Interface_send_buffer_size + 1) * sizeof(unsigned int));
Feb_Interface_send_data = &Feb_Interface_send_data_raw[1];
Feb_Interface_recv_ndata = 0;
Feb_Interface_recv_buffer_size = 1026;
Feb_Interface_recv_data_raw = malloc((Feb_Interface_recv_buffer_size+1) * sizeof(unsigned int));
Feb_Interface_recv_data_raw =
malloc((Feb_Interface_recv_buffer_size + 1) * sizeof(unsigned int));
Feb_Interface_recv_data = &Feb_Interface_recv_data_raw[1];
Local_LocalLinkInterface1(ll,XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_RIGHT_BASEADDR);
Local_LocalLinkInterface1(
ll, XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_RIGHT_BASEADDR);
}
void Feb_Interface_SendCompleteList(unsigned int n,unsigned int* list) {
void Feb_Interface_SendCompleteList(unsigned int n, unsigned int *list) {
unsigned int i;
if (Feb_Interface_feb_numb) free(Feb_Interface_feb_numb);
if (Feb_Interface_feb_numb)
free(Feb_Interface_feb_numb);
Feb_Interface_nfebs = n;
Feb_Interface_feb_numb = malloc(n * sizeof(unsigned int));
for(i=0;i<n;i++) Feb_Interface_feb_numb[i] = list[i];
for (i = 0; i < n; i++)
Feb_Interface_feb_numb[i] = list[i];
}
int Feb_Interface_WriteTo(unsigned int ch) {
if (ch>0xfff) return 0;
if (ch > 0xfff)
return 0;
LOG(logDEBUG1, ("FIW ch %d\n", ch));
Feb_Interface_send_data_raw[0] = 0x8fff0000;
if (Local_Write(ll,4,Feb_Interface_send_data_raw)!=4) return 0;
Feb_Interface_send_data_raw[0] = 0x8fff0000;
if (Local_Write(ll, 4, Feb_Interface_send_data_raw) != 4)
return 0;
Feb_Interface_send_data_raw[0] = 0x90000000 | (ch<<16);
if (Local_Write(ll,4,Feb_Interface_send_data_raw)!=4) return 0;
Feb_Interface_send_data_raw[0] = 0x90000000 | (ch << 16);
if (Local_Write(ll, 4, Feb_Interface_send_data_raw) != 4)
return 0;
Feb_Interface_send_data_raw[0] = 0xc0000000;
return ((Feb_Interface_send_ndata+1)*4==Local_Write(ll,(Feb_Interface_send_ndata+1)*4,Feb_Interface_send_data_raw));
Feb_Interface_send_data_raw[0] = 0xc0000000;
return ((Feb_Interface_send_ndata + 1) * 4 ==
Local_Write(ll, (Feb_Interface_send_ndata + 1) * 4,
Feb_Interface_send_data_raw));
}
int Feb_Interface_ReadFrom(unsigned int ch, unsigned int ntrys) {
unsigned int t;
if (ch>=0xfff) return 0;
if (ch >= 0xfff)
return 0;
Feb_Interface_recv_data_raw[0] = 0xa0000000 | (ch<<16);
Local_Write(ll,4,Feb_Interface_recv_data_raw);
Feb_Interface_recv_data_raw[0] = 0xa0000000 | (ch << 16);
Local_Write(ll, 4, Feb_Interface_recv_data_raw);
usleep(20);
Feb_Interface_recv_ndata=-1;
for(t=0;t<ntrys;t++) {
if ((Feb_Interface_recv_ndata=Local_Read(ll,Feb_Interface_recv_buffer_size*4,Feb_Interface_recv_data_raw)/4)>0) {
Feb_Interface_recv_ndata = -1;
for (t = 0; t < ntrys; t++) {
if ((Feb_Interface_recv_ndata =
Local_Read(ll, Feb_Interface_recv_buffer_size * 4,
Feb_Interface_recv_data_raw) /
4) > 0) {
Feb_Interface_recv_ndata--;
break;
}
usleep(1000);
}
return (Feb_Interface_recv_ndata>=0);
return (Feb_Interface_recv_ndata >= 0);
}
int Feb_Interface_SetByteOrder() {
Feb_Interface_send_data_raw[0] = 0x8fff0000;
if (Local_Write(ll,4,Feb_Interface_send_data_raw)!=4) return 0;
if (Local_Write(ll, 4, Feb_Interface_send_data_raw) != 4)
return 0;
Feb_Interface_send_ndata = 2;
Feb_Interface_send_data[0] = 0;
Feb_Interface_send_data[1] = 0;
unsigned int i;
unsigned int dst = 0xff;
for(i=0;i<Feb_Interface_nfebs;i++) dst = (dst | Feb_Interface_feb_numb[i]);
for (i = 0; i < Feb_Interface_nfebs; i++)
dst = (dst | Feb_Interface_feb_numb[i]);
int passed = Feb_Interface_WriteTo(dst);
return passed;
}
int Feb_Interface_ReadRegister(unsigned int sub_num, unsigned int reg_num,unsigned int* value_read) {
return Feb_Interface_ReadRegisters(sub_num,1,&reg_num,value_read);
int Feb_Interface_ReadRegister(unsigned int sub_num, unsigned int reg_num,
unsigned int *value_read) {
return Feb_Interface_ReadRegisters(sub_num, 1, &reg_num, value_read);
}
int Feb_Interface_ReadRegisters(unsigned int sub_num, unsigned int nreads, unsigned int* reg_nums,unsigned int* values_read) {
//here cout<<"Reading Register ...."<<endl;
int Feb_Interface_ReadRegisters(unsigned int sub_num, unsigned int nreads,
unsigned int *reg_nums,
unsigned int *values_read) {
// here cout<<"Reading Register ...."<<endl;
unsigned int i;
nreads &= 0x3ff;
if (!nreads||nreads>Feb_Interface_send_buffer_size-2) return 0;
if (!nreads || nreads > Feb_Interface_send_buffer_size - 2)
return 0;
Feb_Interface_send_ndata = nreads+2;
Feb_Interface_send_ndata = nreads + 2;
Feb_Interface_send_data[0] = 0x20000000 | nreads << 14;
for(i=0;i<nreads;i++) Feb_Interface_send_data[i+1]=reg_nums[i];
Feb_Interface_send_data[nreads+1] = 0;
for (i = 0; i < nreads; i++)
Feb_Interface_send_data[i + 1] = reg_nums[i];
Feb_Interface_send_data[nreads + 1] = 0;
if (!Feb_Interface_WriteTo(sub_num)||!Feb_Interface_ReadFrom(sub_num,20)||Feb_Interface_recv_ndata!=(int)(nreads+2)) return 0;
if (!Feb_Interface_WriteTo(sub_num) ||
!Feb_Interface_ReadFrom(sub_num, 20) ||
Feb_Interface_recv_ndata != (int)(nreads + 2))
return 0;
for(i=0;i<nreads;i++) values_read[i] = Feb_Interface_recv_data[i+1];
for (i = 0; i < nreads; i++)
values_read[i] = Feb_Interface_recv_data[i + 1];
return 1;
}
int Feb_Interface_WriteRegister(unsigned int sub_num, unsigned int reg_num,unsigned int value, int wait_on, unsigned int wait_on_address) {
return Feb_Interface_WriteRegisters(sub_num,1,&reg_num,&value,&wait_on,&wait_on_address);
int Feb_Interface_WriteRegister(unsigned int sub_num, unsigned int reg_num,
unsigned int value, int wait_on,
unsigned int wait_on_address) {
return Feb_Interface_WriteRegisters(sub_num, 1, &reg_num, &value, &wait_on,
&wait_on_address);
}
int Feb_Interface_WriteRegisters(unsigned int sub_num, unsigned int nwrites, unsigned int* reg_nums, unsigned int* values, int* wait_ons, unsigned int* wait_on_addresses) {
int Feb_Interface_WriteRegisters(unsigned int sub_num, unsigned int nwrites,
unsigned int *reg_nums, unsigned int *values,
int *wait_ons,
unsigned int *wait_on_addresses) {
unsigned int i;
nwrites &= 0x3ff; //10 bits
if (!nwrites||2*nwrites>Feb_Interface_send_buffer_size-2) return 0;
nwrites &= 0x3ff; // 10 bits
if (!nwrites || 2 * nwrites > Feb_Interface_send_buffer_size - 2)
return 0;
//cout<<"Write register : "<<this<<" "<<s_num<<" "<<nwrites<<" "<<reg_nums<<" "<<values<<" "<<wait_ons<<" "<<wait_on_addresses<<endl;
Feb_Interface_send_ndata = 2*nwrites+2;
// cout<<"Write register : "<<this<<" "<<s_num<<" "<<nwrites<<"
// "<<reg_nums<<" "<<values<<" "<<wait_ons<<" "<<wait_on_addresses<<endl;
Feb_Interface_send_ndata = 2 * nwrites + 2;
Feb_Interface_send_data[0] = 0x80000000 | nwrites << 14;
Feb_Interface_send_data[2*nwrites+1] = 0;
Feb_Interface_send_data[2 * nwrites + 1] = 0;
for(i=0;i<nwrites;i++) Feb_Interface_send_data[2*i+1] = 0x3fff&reg_nums[i];
for(i=0;i<nwrites;i++) Feb_Interface_send_data[2*i+2] = values[i];
for (i = 0; i < nwrites; i++)
Feb_Interface_send_data[2 * i + 1] = 0x3fff & reg_nums[i];
for (i = 0; i < nwrites; i++)
Feb_Interface_send_data[2 * i + 2] = values[i];
// wait on busy data(28), address of busy flag data(27 downto 14)
if (wait_ons&&wait_on_addresses) for(i=0;i<nwrites;i++) Feb_Interface_send_data[2*i+1] |= (wait_ons[i]<<28 | (0x3fff&wait_on_addresses[i])<<14);
if (wait_ons && wait_on_addresses)
for (i = 0; i < nwrites; i++)
Feb_Interface_send_data[2 * i + 1] |=
(wait_ons[i] << 28 | (0x3fff & wait_on_addresses[i]) << 14);
if (!Feb_Interface_WriteTo(sub_num)) return 0;
if (!Feb_Interface_WriteTo(sub_num))
return 0;
return 1;
}
int Feb_Interface_WriteMemoryInLoops(unsigned int sub_num, unsigned int mem_num, unsigned int start_address, unsigned int nwrites, unsigned int *values) {
int Feb_Interface_WriteMemoryInLoops(unsigned int sub_num, unsigned int mem_num,
unsigned int start_address,
unsigned int nwrites,
unsigned int *values) {
unsigned int max_single_packet_size = 352;
int passed=1;
int passed = 1;
unsigned int n_to_send = max_single_packet_size;
unsigned int ndata_sent = 0;
unsigned int ndata_countdown = nwrites;
while(ndata_countdown>0) {
n_to_send = ndata_countdown<max_single_packet_size ? ndata_countdown:max_single_packet_size;
if (!Feb_Interface_WriteMemory(sub_num,mem_num,start_address,n_to_send,&(values[ndata_sent]))) {passed=0; break;}
ndata_countdown-=n_to_send;
ndata_sent +=n_to_send;
start_address +=n_to_send;
usleep(500);//500 works
while (ndata_countdown > 0) {
n_to_send = ndata_countdown < max_single_packet_size
? ndata_countdown
: max_single_packet_size;
if (!Feb_Interface_WriteMemory(sub_num, mem_num, start_address,
n_to_send, &(values[ndata_sent]))) {
passed = 0;
break;
}
ndata_countdown -= n_to_send;
ndata_sent += n_to_send;
start_address += n_to_send;
usleep(500); // 500 works
}
return passed;
}
int Feb_Interface_WriteMemory(unsigned int sub_num, unsigned int mem_num, unsigned int start_address, unsigned int nwrites, unsigned int *values) {
int Feb_Interface_WriteMemory(unsigned int sub_num, unsigned int mem_num,
unsigned int start_address, unsigned int nwrites,
unsigned int *values) {
// -1 means write to all
unsigned int i;
mem_num &= 0x3f;
start_address &= 0x3fff;
nwrites &= 0x3ff;
if (!nwrites||nwrites>Feb_Interface_send_buffer_size-2) {
LOG(logERROR, ("invalid nwrites:%d\n",nwrites));
if (!nwrites || nwrites > Feb_Interface_send_buffer_size - 2) {
LOG(logERROR, ("invalid nwrites:%d\n", nwrites));
return 0;
}//*d-1026
} //*d-1026
Feb_Interface_send_ndata = nwrites+2;//*d-1026
Feb_Interface_send_data[0] = 0xc0000000 | mem_num << 24 | nwrites << 14 | start_address; //cmd -> write to memory, nwrites, mem number, start address
Feb_Interface_send_data[nwrites+1] = 0;
for(i=0;i<nwrites;i++) Feb_Interface_send_data[i+1] = values[i];
Feb_Interface_send_ndata = nwrites + 2; //*d-1026
Feb_Interface_send_data[0] =
0xc0000000 | mem_num << 24 | nwrites << 14 |
start_address; // cmd -> write to memory, nwrites, mem number, start
// address
Feb_Interface_send_data[nwrites + 1] = 0;
for (i = 0; i < nwrites; i++)
Feb_Interface_send_data[i + 1] = values[i];
if (!Feb_Interface_WriteTo(sub_num)) return 0;
if (!Feb_Interface_WriteTo(sub_num))
return 0;
return 1;
}

28
slsDetectorServers/eigerDetectorServer/FebInterface.h Executable file → Normal file
View File

@@ -3,12 +3,24 @@
int Feb_Interface_WriteTo(unsigned int ch);
int Feb_Interface_ReadFrom(unsigned int ch, unsigned int ntrys);
void Feb_Interface_FebInterface();
void Feb_Interface_SendCompleteList(unsigned int n,unsigned int* list);
void Feb_Interface_SendCompleteList(unsigned int n, unsigned int *list);
int Feb_Interface_SetByteOrder();
int Feb_Interface_ReadRegister(unsigned int sub_num, unsigned int reg_num,unsigned int* value_read);
int Feb_Interface_ReadRegisters(unsigned int sub_num, unsigned int nreads, unsigned int* reg_nums,unsigned int* values_read);
int Feb_Interface_WriteRegister(unsigned int sub_num, unsigned int reg_num,unsigned int value, int wait_on, unsigned int wait_on_address);
int Feb_Interface_WriteRegisters(unsigned int sub_num, unsigned int nwrites, unsigned int* reg_nums, unsigned int* values, int* wait_ons, unsigned int* wait_on_addresses);
int Feb_Interface_WriteMemoryInLoops(unsigned int sub_num, unsigned int mem_num, unsigned int start_address, unsigned int nwrites, unsigned int *values);
int Feb_Interface_WriteMemory(unsigned int sub_num, unsigned int mem_num, unsigned int start_address, unsigned int nwrites, unsigned int *values);
int Feb_Interface_ReadRegister(unsigned int sub_num, unsigned int reg_num,
unsigned int *value_read);
int Feb_Interface_ReadRegisters(unsigned int sub_num, unsigned int nreads,
unsigned int *reg_nums,
unsigned int *values_read);
int Feb_Interface_WriteRegister(unsigned int sub_num, unsigned int reg_num,
unsigned int value, int wait_on,
unsigned int wait_on_address);
int Feb_Interface_WriteRegisters(unsigned int sub_num, unsigned int nwrites,
unsigned int *reg_nums, unsigned int *values,
int *wait_ons,
unsigned int *wait_on_addresses);
int Feb_Interface_WriteMemoryInLoops(unsigned int sub_num, unsigned int mem_num,
unsigned int start_address,
unsigned int nwrites,
unsigned int *values);
int Feb_Interface_WriteMemory(unsigned int sub_num, unsigned int mem_num,
unsigned int start_address, unsigned int nwrites,
unsigned int *values);

114
slsDetectorServers/eigerDetectorServer/FebRegisterDefs.h Executable file → Normal file
View File

@@ -1,5 +1,5 @@
//daq register definitions
// daq register definitions
#define DAQ_REG_CTRL 1
#define DAQ_REG_CHIP_CMDS 2
#define DAQ_REG_STATIC_BITS 3
@@ -12,7 +12,7 @@
#define DAQ_REG_EXPOSURE_TIMER 4 // == (31 downto 3) * 10^(2 downto 0)
#define DAQ_REG_EXPOSURE_REPEAT_TIMER 5 // == (31 downto 3) * 10^(2 downto 0)
#define DAQ_REG_SUBFRAME_EXPOSURES 6
#define DAQ_REG_SUBFRAME_PERIOD 7 //also pg and fifo status register
#define DAQ_REG_SUBFRAME_PERIOD 7 // also pg and fifo status register
#define DAQ_REG_PARTIAL_READOUT 8
#define DAQ_REG_HRDWRE 12
@@ -22,22 +22,22 @@
#define DAQ_REG_HRDWRE_TOP_OFST (1)
#define DAQ_REG_HRDWRE_TOP_MSK (0x00000001 << DAQ_REG_HRDWRE_TOP_OFST)
#define DAQ_REG_HRDWRE_INTRRPT_SF_OFST (2)
#define DAQ_REG_HRDWRE_INTRRPT_SF_MSK (0x00000001 << DAQ_REG_HRDWRE_INTRRPT_SF_OFST)
#define DAQ_REG_HRDWRE_INTRRPT_SF_MSK \
(0x00000001 << DAQ_REG_HRDWRE_INTRRPT_SF_OFST)
#define DAQ_REG_RO_OFFSET 20
#define DAQ_REG_STATUS (DAQ_REG_RO_OFFSET + 0) //also pg and fifo status register
#define DAQ_REG_STATUS \
(DAQ_REG_RO_OFFSET + 0) // also pg and fifo status register
#define FEB_REG_STATUS (DAQ_REG_RO_OFFSET + 3)
#define MEAS_SUBPERIOD_REG (DAQ_REG_RO_OFFSET + 4)
#define MEAS_PERIOD_REG (DAQ_REG_RO_OFFSET + 5)
#define DAQ_CTRL_RESET 0x80000000
#define DAQ_CTRL_START 0x40000000
#define ACQ_CTRL_START 0x50000000 //this is 0x10000000 (acq) | 0x40000000 (daq)
#define ACQ_CTRL_START 0x50000000 // this is 0x10000000 (acq) | 0x40000000 (daq)
#define DAQ_CTRL_STOP 0x00000000
//direct chip commands to the DAQ_REG_CHIP_CMDS register
// direct chip commands to the DAQ_REG_CHIP_CMDS register
#define DAQ_SET_STATIC_BIT 0x00000001
#define DAQ_RESET_COMPLETELY 0x0000000E
#define DAQ_RESET_PERIPHERY 0x00000002
@@ -52,9 +52,10 @@
#define DAQ_SERIALIN_SHIFT_IN_32 0x00000100
#define DAQ_LOAD_16ROWS_OF_TRIMBITS 0x00000200
#define DAQ_IGNORE_INITIAL_CRAP 0x00000400 //crap before readout
#define DAQ_IGNORE_INITIAL_CRAP 0x00000400 // crap before readout
#define DAQ_READOUT_NROWS 0x00000800
#define DAQ_CLKOUT_LAST_4_BITS_AND_RETURN_TO_START 0x00001000 //last 4 bit of data in the last frame
#define DAQ_CLKOUT_LAST_4_BITS_AND_RETURN_TO_START \
0x00001000 // last 4 bit of data in the last frame
#define DAQ_RELEASE_IMAGE_STORE_AFTER_READOUT 0x00002000
#define DAQ_RESET_PIXEL_COUNTERS_AFTER_READOUT 0x00004000
@@ -63,77 +64,87 @@
#define DAQ_CLK_MAIN_CLK_TO_SELECT_NEXT_PIXEL 0x00010000
#define DAQ_SEND_N_TEST_PULSES 0x00020000
#define DAQ_CHIP_CONTROLLER_HALF_SPEED 0x00040000 //everything at 100 MHz (50MHz ddr readout)
#define DAQ_CHIP_CONTROLLER_QUARTER_SPEED 0x00080000 //everything at 50 MHz (25MHz ddr readout)
#define DAQ_CHIP_CONTROLLER_SUPER_SLOW_SPEED 0x000c0000 //everything at ~200 kHz (200 kHz MHz ddr readout)
#define DAQ_CHIP_CONTROLLER_HALF_SPEED \
0x00040000 // everything at 100 MHz (50MHz ddr readout)
#define DAQ_CHIP_CONTROLLER_QUARTER_SPEED \
0x00080000 // everything at 50 MHz (25MHz ddr readout)
#define DAQ_CHIP_CONTROLLER_SUPER_SLOW_SPEED \
0x000c0000 // everything at ~200 kHz (200 kHz MHz ddr readout)
//#define DAQ_FIFO_ENABLE 0x00100000 commented out as it is not used anywhere
//#define DAQ_FIFO_ENABLE 0x00100000 commented out as it
// is not used anywhere
#define DAQ_REG_CHIP_CMDS_INT_TRIGGER 0x00100000
//direct chip commands to the DAQ_REG_CHIP_CMDS register
#define DAQ_NEXPOSURERS_SAFEST_MODE_ROW_CLK_BEFORE_MODE 0x00200000 //row clk is before main clk readout sequence
#define DAQ_NEXPOSURERS_NORMAL_NONPARALLEL_MODE 0x00400000 //expose ->readout ->expose -> ..., with store is always closed
#define DAQ_NEXPOSURERS_PARALLEL_MODE 0x00600000 //parallel acquire/read mode
// direct chip commands to the DAQ_REG_CHIP_CMDS register
#define DAQ_NEXPOSURERS_SAFEST_MODE_ROW_CLK_BEFORE_MODE \
0x00200000 // row clk is before main clk readout sequence
#define DAQ_NEXPOSURERS_NORMAL_NONPARALLEL_MODE \
0x00400000 // expose ->readout ->expose -> ..., with store is always closed
#define DAQ_NEXPOSURERS_PARALLEL_MODE 0x00600000 // parallel acquire/read mode
//DAQ_NEXPOSURERS_READOUT_COMPLETE_IMAGES is old now hard-wired in the firmware that every image comes with a header
//#define DAQ_NEXPOSURERS_READOUT_COMPLETE_IMAGES 0x00800000 //DAQ_IGNORE_INITIAL_CRAP and DAQ_CLKOUT_LAST_4_BITS_AND_RETURN_TO_START
// DAQ_NEXPOSURERS_READOUT_COMPLETE_IMAGES is old now hard-wired in the firmware
// that every image comes with a header #define
// DAQ_NEXPOSURERS_READOUT_COMPLETE_IMAGES 0x00800000
////DAQ_IGNORE_INITIAL_CRAP and DAQ_CLKOUT_LAST_4_BITS_AND_RETURN_TO_START
#define DAQ_NEXPOSURERS_EXTERNAL_ENABLING 0x01000000
#define DAQ_NEXPOSURERS_EXTERNAL_ENABLING_POLARITY 0x02000000
#define DAQ_NEXPOSURERS_EXTERNAL_TRIGGER_POLARITY 0x04000000
#define DAQ_NEXPOSURERS_INTERNAL_ACQUISITION 0x00000000 //internally controlled
#define DAQ_NEXPOSURERS_EXTERNAL_ACQUISITION_START 0x08000000 //external acquisition start
#define DAQ_NEXPOSURERS_EXTERNAL_IMAGE_START 0x10000000 //external image start
#define DAQ_NEXPOSURERS_EXTERNAL_IMAGE_START_AND_STOP 0x18000000 //externally controlly, external image start and stop
#define DAQ_NEXPOSURERS_INTERNAL_ACQUISITION 0x00000000 // internally controlled
#define DAQ_NEXPOSURERS_EXTERNAL_ACQUISITION_START \
0x08000000 // external acquisition start
#define DAQ_NEXPOSURERS_EXTERNAL_IMAGE_START 0x10000000 // external image start
#define DAQ_NEXPOSURERS_EXTERNAL_IMAGE_START_AND_STOP \
0x18000000 // externally controlly, external image start and stop
#define DAQ_NEXPOSURERS_ACTIVATE_AUTO_SUBIMAGING 0x20000000
#define DAQ_NEXPOSURERS_ACTIVATE_RATE_CORRECTION 0x40000000
//#define DAQ_MASTER_HALF_MODULE 0x80000000 currently not used
//#define DAQ_MASTER_HALF_MODULE 0x80000000 currently not
// used
//chips static bits
// chips static bits
#define DAQ_STATIC_BIT_PROGRAM 0x00000001
#define DAQ_STATIC_BIT_M4 0x00000002 //these are the status bits, not bit mode
#define DAQ_STATIC_BIT_M8 0x00000004 //these are the status bits, not bit mode
#define DAQ_STATIC_BIT_M12 0x00000000 //these are the status bits, not bit mode, ie. "00" is 12 bit mode
#define DAQ_STATIC_BIT_M4 0x00000002 // these are the status bits, not bit mode
#define DAQ_STATIC_BIT_M8 0x00000004 // these are the status bits, not bit mode
#define DAQ_STATIC_BIT_M12 \
0x00000000 // these are the status bits, not bit mode, ie. "00" is 12 bit
// mode
#define DAQ_STATIC_BIT_CHIP_TEST 0x00000008
#define DAQ_STATIC_BIT_ROTEST 0x00000010
#define DAQ_CS_BAR_LEFT 0x00000020
#define DAQ_CS_BAR_RIGHT 0x00000040
//status flags
// status flags
#define DAQ_STATUS_DAQ_RUNNING 0x01
#define DAQ_DATA_COLLISION_ERROR 0x02
#define DAQ_STATUS_CURRENT_M4 0x04
#define DAQ_STATUS_CURRENT_M8 0x08
#define DAQ_STATUS_CURRENT_M12 0x00 //in 12 bit mode both are cleared
#define DAQ_STATUS_CURRENT_M12 0x00 // in 12 bit mode both are cleared
#define DAQ_STATUS_CURRENT_TESTMODE 0x10
#define DAQ_STATUS_TOKEN_OUT 0x20
#define DAQ_STATUS_SERIAL_OUT 0x40
#define DAQ_STATUS_PIXELS_ARE_ENABLED 0x80
#define DAQ_STATUS_DAQ_RUN_TOGGLE 0x200
//data delay registers
// data delay registers
#define CHIP_DATA_OUT_DELAY_REG_CTRL 1
#define CHIP_DATA_OUT_DELAY_REG2 2
#define CHIP_DATA_OUT_DELAY_REG3 3
#define CHIP_DATA_OUT_DELAY_REG4 4
#define CHIP_DATA_OUT_DELAY_SET 0x20000000
//module configuration
// module configuration
#define TOP_BIT_MASK 0x00f
#define MASTER_BIT_MASK 0x200
#define NORMAL_MODULE_BIT_MASK 0x400
// Master Slave Top Bottom Definition
#define MODULE_CONFIGURATION_MASK 0x84
//Software Configuration
#define MASTERCONFIG_OFFSET 0x160 //0x20 * 11 (P11)
// Software Configuration
#define MASTERCONFIG_OFFSET 0x160 // 0x20 * 11 (P11)
#define MASTER_BIT 0x1
#define OVERWRITE_HARDWARE_BIT 0x2
#define DEACTIVATE_BIT 0x4
@@ -146,11 +157,12 @@
#define FLOW_REG_OFFSET 0x140
#define FLOW_REG_TXM_FLOW_CNTRL_10G_OFST (0)
#define FLOW_REG_TXM_FLOW_CNTRL_10G_MSK (0x1 << FLOW_REG_TXM_FLOW_CNTRL_10G_OFST)
#define FLOW_REG_TXM_FLOW_CNTRL_10G_MSK \
(0x1 << FLOW_REG_TXM_FLOW_CNTRL_10G_OFST)
#define FLOW_REG_OVERFLOW_32_BIT_OFST (2)
#define FLOW_REG_OVERFLOW_32_BIT_MSK (0x1 << FLOW_REG_OVERFLOW_32_BIT_OFST)
//command memory
// command memory
#define LEFT_OFFSET 0x0
#define RIGHT_OFFSET 0x100
@@ -164,13 +176,13 @@
#define TWO_REQUESTS_OFFSET 0x1c
#define TWO_REQUESTS_BIT 0x80000000
//version
// version
#define FIRMWARE_VERSION_OFFSET 0x4
#define FIRMWARESOFTWARE_API_OFFSET 0x0
#define FRAME_NUM_RESET_OFFSET 0xA0
//1g counters
// 1g counters
#define ONE_GIGA_LEFT_INDEX_LSB_COUNTER 0x04
#define ONE_GIGA_LEFT_INDEX_MSB_COUNTER 0x24
@@ -183,7 +195,7 @@
#define ONE_GIGA_RIGHT_TXN_DELAY_COUNTER 0x144
#define ONE_GIGA_RIGHT_FRAME_DELAY_COUNTER 0x164
//10g counters
// 10g counters
#define TEN_GIGA_LEFT_INDEX_LSB_COUNTER 0x84
#define TEN_GIGA_LEFT_INDEX_MSB_COUNTER 0xa4
@@ -210,19 +222,3 @@
#define UDP_HEADER_Z_MSK (0xFFFF << UDP_HEADER_Z_OFST)
#define UDP_HEADER_Y_OFST (16)
#define UDP_HEADER_Y_MSK (0xFFFF << UDP_HEADER_Y_OFST)

36
slsDetectorServers/eigerDetectorServer/HardwareIO.c Executable file → Normal file
View File

@@ -1,76 +1,64 @@
#include "HardwareIO.h"
xfs_u8 HWIO_xfs_in8(xfs_u32 InAddress)
{
xfs_u8 HWIO_xfs_in8(xfs_u32 InAddress) {
/* read the contents of the I/O location and then synchronize the I/O
* such that the I/O operation completes before proceeding on
*/
xfs_u8 IoContents;
__asm__ volatile ("eieio; lbz %0,0(%1)":"=r" (IoContents):"b"
(InAddress));
__asm__ volatile("eieio; lbz %0,0(%1)" : "=r"(IoContents) : "b"(InAddress));
return IoContents;
}
/*****************************************************************************/
xfs_u16 HWIO_xfs_in16(xfs_u32 InAddress)
{
xfs_u16 HWIO_xfs_in16(xfs_u32 InAddress) {
/* read the contents of the I/O location and then synchronize the I/O
* such that the I/O operation completes before proceeding on
*/
xfs_u16 IoContents;
__asm__ volatile ("eieio; lhz %0,0(%1)":"=r" (IoContents):"b"
(InAddress));
__asm__ volatile("eieio; lhz %0,0(%1)" : "=r"(IoContents) : "b"(InAddress));
return IoContents;
}
/*****************************************************************************/
xfs_u32 HWIO_xfs_in32(xfs_u32 InAddress)
{
xfs_u32 HWIO_xfs_in32(xfs_u32 InAddress) {
/* read the contents of the I/O location and then synchronize the I/O
* such that the I/O operation completes before proceeding on
*/
xfs_u32 IoContents;
__asm__ volatile ("eieio; lwz %0,0(%1)":"=r" (IoContents):"b"
(InAddress));
__asm__ volatile("eieio; lwz %0,0(%1)" : "=r"(IoContents) : "b"(InAddress));
return IoContents;
}
/*****************************************************************************/
void HWIO_xfs_out8(xfs_u32 OutAddress, xfs_u8 Value)
{
void HWIO_xfs_out8(xfs_u32 OutAddress, xfs_u8 Value) {
/* write the contents of the I/O location and then synchronize the I/O
* such that the I/O operation completes before proceeding on
*/
__asm__ volatile ("stb %0,0(%1); eieio"::"r" (Value), "b"(OutAddress));
__asm__ volatile("stb %0,0(%1); eieio" ::"r"(Value), "b"(OutAddress));
}
/*****************************************************************************/
void HWIO_xfs_out16(xfs_u32 OutAddress, xfs_u16 Value)
{
void HWIO_xfs_out16(xfs_u32 OutAddress, xfs_u16 Value) {
/* write the contents of the I/O location and then synchronize the I/O
* such that the I/O operation completes before proceeding on
*/
__asm__ volatile ("sth %0,0(%1); eieio"::"r" (Value), "b"(OutAddress));
__asm__ volatile("sth %0,0(%1); eieio" ::"r"(Value), "b"(OutAddress));
}
/*****************************************************************************/
void HWIO_xfs_out32(xfs_u32 OutAddress, xfs_u32 Value)
{
void HWIO_xfs_out32(xfs_u32 OutAddress, xfs_u32 Value) {
/* write the contents of the I/O location and then synchronize the I/O
* such that the I/O operation completes before proceeding on
*/
__asm__ volatile ("stw %0,0(%1); eieio"::"r" (Value), "b"(OutAddress));
__asm__ volatile("stw %0,0(%1); eieio" ::"r"(Value), "b"(OutAddress));
}

17
slsDetectorServers/eigerDetectorServer/HardwareIO.h Executable file → Normal file
View File

@@ -1,16 +1,13 @@
//Class initially from Gerd and was called mmap_test.c
// Class initially from Gerd and was called mmap_test.c
#pragma once
#include "xfs_types.h"
xfs_u8 HWIO_xfs_in8(xfs_u32 InAddress);
xfs_u16 HWIO_xfs_in16(xfs_u32 InAddress);
xfs_u32 HWIO_xfs_in32(xfs_u32 InAddress);
xfs_u8 HWIO_xfs_in8(xfs_u32 InAddress);
xfs_u16 HWIO_xfs_in16(xfs_u32 InAddress);
xfs_u32 HWIO_xfs_in32(xfs_u32 InAddress);
void HWIO_xfs_out8(xfs_u32 OutAddress, xfs_u8 Value);
void HWIO_xfs_out16(xfs_u32 OutAddress, xfs_u16 Value);
void HWIO_xfs_out32(xfs_u32 OutAddress, xfs_u32 Value);
void HWIO_xfs_out8(xfs_u32 OutAddress, xfs_u8 Value);
void HWIO_xfs_out16(xfs_u32 OutAddress, xfs_u16 Value);
void HWIO_xfs_out32(xfs_u32 OutAddress, xfs_u32 Value);

9
slsDetectorServers/eigerDetectorServer/HardwareMMappingDefs.h Executable file → Normal file
View File

@@ -1,11 +1,10 @@
//from Gerd and was called mmap_test.h
// from Gerd and was called mmap_test.h
#ifndef __PLB_LL_FIFO_H__
#define __PLB_LL_FIFO_H__
/******************************************************************************/
/* definitions */
/******************************************************************************/
@@ -20,7 +19,6 @@
#define PLB_LL_FIFO_CTRL_LL_SOF 0x10000000
#define PLB_LL_FIFO_CTRL_LL_MASK 0xF0000000
#define PLB_LL_FIFO_CTRL_TX_RESET 0x08000000
#define PLB_LL_FIFO_CTRL_RX_RESET 0x04000000
@@ -38,10 +36,8 @@
// reset Rx and Tx Fifo and set User Reset
#define PLB_LL_FIFO_CTRL_RESET_FIFO 0x0C400000
#define PLB_LL_FIFO_CTRL_CONFIG_VECTOR 0x000FFFFF
#define PLB_LL_FIFO_STATUS_LL_REM_SHIFT 30
#define PLB_LL_FIFO_STATUS_LL_REM 0xC0000000
#define PLB_LL_FIFO_STATUS_LL_EOF 0x20000000
@@ -56,7 +52,4 @@
#define PLB_LL_FIFO_ALMOST_FULL_THRESHOLD_WORDS 100
#endif // __PLB_LL_FIFO_H__

198
slsDetectorServers/eigerDetectorServer/LocalLinkInterface.c Executable file → Normal file
View File

@@ -2,82 +2,85 @@
#include "HardwareMMappingDefs.h"
#include "clogger.h"
#include <unistd.h>
#include <sys/mman.h>
#include <fcntl.h>
#include <sys/mman.h>
#include <unistd.h>
void Local_LocalLinkInterface1(struct LocalLinkInterface* ll,unsigned int ll_fifo_badr) {
void Local_LocalLinkInterface1(struct LocalLinkInterface *ll,
unsigned int ll_fifo_badr) {
LOG(logDEBUG1, ("Initialize PLB LL FIFOs\n"));
ll->ll_fifo_base=0;
ll->ll_fifo_ctrl_reg=0;
if (Local_Init(ll,ll_fifo_badr)) {
ll->ll_fifo_base = 0;
ll->ll_fifo_ctrl_reg = 0;
if (Local_Init(ll, ll_fifo_badr)) {
Local_Reset(ll);
LOG(logDEBUG1, ("\tFIFO Status : 0x%08x\n\n\n", Local_StatusVector(ll)));
} else LOG(logERROR, ("\tCould not map LocalLink : 0x%08x\n\n\n", ll_fifo_badr));
LOG(logDEBUG1,
("\tFIFO Status : 0x%08x\n\n\n", Local_StatusVector(ll)));
} else
LOG(logERROR,
("\tCould not map LocalLink : 0x%08x\n\n\n", ll_fifo_badr));
}
void Local_LocalLinkInterface(struct LocalLinkInterface* ll) {
void Local_LocalLinkInterface(struct LocalLinkInterface *ll) {
LOG(logDEBUG1, ("Initializing new memory\n"));
}
int Local_Init(struct LocalLinkInterface* ll,unsigned int ll_fifo_badr) {
int Local_Init(struct LocalLinkInterface *ll, unsigned int ll_fifo_badr) {
int fd;
void *plb_ll_fifo_ptr;
if ((fd=open("/dev/mem", O_RDWR)) < 0) {
if ((fd = open("/dev/mem", O_RDWR)) < 0) {
fprintf(stderr, "Could not open /dev/mem\n");
return 0;
}
plb_ll_fifo_ptr = mmap(0, getpagesize(), PROT_READ | PROT_WRITE, MAP_FILE | MAP_SHARED, fd, ll_fifo_badr);
plb_ll_fifo_ptr = mmap(0, getpagesize(), PROT_READ | PROT_WRITE,
MAP_FILE | MAP_SHARED, fd, ll_fifo_badr);
close(fd);
if (plb_ll_fifo_ptr == MAP_FAILED) {
perror ("mmap");
perror("mmap");
return 0;
}
ll->ll_fifo_base = (xfs_u32) plb_ll_fifo_ptr;
ll->ll_fifo_base = (xfs_u32)plb_ll_fifo_ptr;
ll->ll_fifo_ctrl_reg = 0;
return 1;
}
int Local_Reset(struct LocalLinkInterface* ll) {
return Local_Reset1(ll,PLB_LL_FIFO_CTRL_RESET_STD);
int Local_Reset(struct LocalLinkInterface *ll) {
return Local_Reset1(ll, PLB_LL_FIFO_CTRL_RESET_STD);
}
int Local_Reset1(struct LocalLinkInterface* ll,unsigned int rst_mask) {
int Local_Reset1(struct LocalLinkInterface *ll, unsigned int rst_mask) {
ll->ll_fifo_ctrl_reg |= rst_mask;
LOG(logDEBUG1, ("\tCTRL Register bits: 0x%08x\n",ll->ll_fifo_ctrl_reg));
LOG(logDEBUG1, ("\tCTRL Register bits: 0x%08x\n", ll->ll_fifo_ctrl_reg));
HWIO_xfs_out32(ll->ll_fifo_base+4*PLB_LL_FIFO_REG_CTRL,ll->ll_fifo_ctrl_reg);
HWIO_xfs_out32(ll->ll_fifo_base+4*PLB_LL_FIFO_REG_CTRL,ll->ll_fifo_ctrl_reg);
HWIO_xfs_out32(ll->ll_fifo_base+4*PLB_LL_FIFO_REG_CTRL,ll->ll_fifo_ctrl_reg);
HWIO_xfs_out32(ll->ll_fifo_base+4*PLB_LL_FIFO_REG_CTRL,ll->ll_fifo_ctrl_reg);
HWIO_xfs_out32(ll->ll_fifo_base + 4 * PLB_LL_FIFO_REG_CTRL,
ll->ll_fifo_ctrl_reg);
HWIO_xfs_out32(ll->ll_fifo_base + 4 * PLB_LL_FIFO_REG_CTRL,
ll->ll_fifo_ctrl_reg);
HWIO_xfs_out32(ll->ll_fifo_base + 4 * PLB_LL_FIFO_REG_CTRL,
ll->ll_fifo_ctrl_reg);
HWIO_xfs_out32(ll->ll_fifo_base + 4 * PLB_LL_FIFO_REG_CTRL,
ll->ll_fifo_ctrl_reg);
ll->ll_fifo_ctrl_reg &= (~rst_mask);
HWIO_xfs_out32(ll->ll_fifo_base+4*PLB_LL_FIFO_REG_CTRL,ll->ll_fifo_ctrl_reg);
HWIO_xfs_out32(ll->ll_fifo_base + 4 * PLB_LL_FIFO_REG_CTRL,
ll->ll_fifo_ctrl_reg);
return 1;
}
unsigned int Local_StatusVector(struct LocalLinkInterface* ll) {
return HWIO_xfs_in32(ll->ll_fifo_base+4*PLB_LL_FIFO_REG_STATUS);
unsigned int Local_StatusVector(struct LocalLinkInterface *ll) {
return HWIO_xfs_in32(ll->ll_fifo_base + 4 * PLB_LL_FIFO_REG_STATUS);
}
int Local_Write(struct LocalLinkInterface* ll,unsigned int buffer_len, void *buffer) {
int Local_Write(struct LocalLinkInterface *ll, unsigned int buffer_len,
void *buffer) {
// note: buffer must be word (4 byte) aligned
// frame_len in byte
int vacancy=0;
int vacancy = 0;
int i;
int words_send = 0;
int last_word;
@@ -85,48 +88,55 @@ int Local_Write(struct LocalLinkInterface* ll,unsigned int buffer_len, void *buf
unsigned int fifo_ctrl;
xfs_u32 status;
if (buffer_len < 1) return -1;
if (buffer_len < 1)
return -1;
last_word = (buffer_len-1)/4;
last_word = (buffer_len - 1) / 4;
word_ptr = (unsigned int *)buffer;
LOG(logDEBUG1, ("LL Write - Len: %2d - If: %X - Data: ",buffer_len, ll->ll_fifo_base));
for (i=0; i < buffer_len/4; i++)
LOG(logDEBUG1, ("%.8X ",*(((unsigned *) buffer)+i)));
LOG(logDEBUG1, ("LL Write - Len: %2d - If: %X - Data: ", buffer_len,
ll->ll_fifo_base));
for (i = 0; i < buffer_len / 4; i++)
LOG(logDEBUG1, ("%.8X ", *(((unsigned *)buffer) + i)));
while (words_send <= last_word)
while (words_send <= last_word) {
while (!vacancy) // wait for Fifo to be empty again
{
while (!vacancy)//wait for Fifo to be empty again
{
status = HWIO_xfs_in32(ll->ll_fifo_base+4*PLB_LL_FIFO_REG_STATUS);
if ((status & PLB_LL_FIFO_STATUS_ALMOSTFULL) == 0) vacancy = 1;
status =
HWIO_xfs_in32(ll->ll_fifo_base + 4 * PLB_LL_FIFO_REG_STATUS);
if ((status & PLB_LL_FIFO_STATUS_ALMOSTFULL) == 0)
vacancy = 1;
if (vacancy == 0) {
LOG(logERROR, ("Fifo full!\n"));
}
}
//Just to know: #define PLB_LL_FIFO_ALMOST_FULL_THRESHOLD_WORDS 100
for (i=0; ((i<PLB_LL_FIFO_ALMOST_FULL_THRESHOLD_WORDS) && (words_send <= last_word)); i++)
{
// Just to know: #define PLB_LL_FIFO_ALMOST_FULL_THRESHOLD_WORDS 100
for (i = 0; ((i < PLB_LL_FIFO_ALMOST_FULL_THRESHOLD_WORDS) &&
(words_send <= last_word));
i++) {
fifo_ctrl = 0;
if (words_send == 0)
{
fifo_ctrl = PLB_LL_FIFO_CTRL_LL_SOF;//announce the start of file
if (words_send == 0) {
fifo_ctrl =
PLB_LL_FIFO_CTRL_LL_SOF; // announce the start of file
}
if (words_send == last_word)
{
fifo_ctrl |= (PLB_LL_FIFO_CTRL_LL_EOF | (( (buffer_len-1)<<PLB_LL_FIFO_CTRL_LL_REM_SHIFT) & PLB_LL_FIFO_CTRL_LL_REM) );
if (words_send == last_word) {
fifo_ctrl |=
(PLB_LL_FIFO_CTRL_LL_EOF |
(((buffer_len - 1) << PLB_LL_FIFO_CTRL_LL_REM_SHIFT) &
PLB_LL_FIFO_CTRL_LL_REM));
}
Local_ctrl_reg_write_mask(ll,PLB_LL_FIFO_CTRL_LL_MASK,fifo_ctrl);
HWIO_xfs_out32(ll->ll_fifo_base+4*PLB_LL_FIFO_REG_FIFO,word_ptr[words_send++]);
Local_ctrl_reg_write_mask(ll, PLB_LL_FIFO_CTRL_LL_MASK, fifo_ctrl);
HWIO_xfs_out32(ll->ll_fifo_base + 4 * PLB_LL_FIFO_REG_FIFO,
word_ptr[words_send++]);
}
}
return buffer_len;
}
int Local_Read(struct LocalLinkInterface* ll,unsigned int buffer_len, void *buffer) {
int Local_Read(struct LocalLinkInterface *ll, unsigned int buffer_len,
void *buffer) {
static unsigned int buffer_ptr = 0;
// note: buffer must be word (4 byte) aligned
// frame_len in byte
@@ -136,19 +146,15 @@ int Local_Read(struct LocalLinkInterface* ll,unsigned int buffer_len, void *buff
volatile unsigned int fifo_val;
int sof = 0;
LOG(logDEBUG1, ("LL Read - If: %X - Data: ",ll->ll_fifo_base));
LOG(logDEBUG1, ("LL Read - If: %X - Data: ", ll->ll_fifo_base));
word_ptr = (unsigned int *)buffer;
do
{
status = HWIO_xfs_in32(ll->ll_fifo_base+4*PLB_LL_FIFO_REG_STATUS);
do {
status = HWIO_xfs_in32(ll->ll_fifo_base + 4 * PLB_LL_FIFO_REG_STATUS);
if (!(status & PLB_LL_FIFO_STATUS_EMPTY))
{
if (status & PLB_LL_FIFO_STATUS_LL_SOF)
{
if (buffer_ptr)
{
if (!(status & PLB_LL_FIFO_STATUS_EMPTY)) {
if (status & PLB_LL_FIFO_STATUS_LL_SOF) {
if (buffer_ptr) {
buffer_ptr = 0;
return -1; // buffer overflow
}
@@ -156,65 +162,61 @@ int Local_Read(struct LocalLinkInterface* ll,unsigned int buffer_len, void *buff
sof = 1;
}
fifo_val = HWIO_xfs_in32(ll->ll_fifo_base+4*PLB_LL_FIFO_REG_FIFO); //read from fifo
fifo_val = HWIO_xfs_in32(
ll->ll_fifo_base + 4 * PLB_LL_FIFO_REG_FIFO); // read from fifo
if ((buffer_ptr > 0) || sof)
{
if ( (buffer_len >> 2) > buffer_ptr)
{
if ((buffer_ptr > 0) || sof) {
if ((buffer_len >> 2) > buffer_ptr) {
LOG(logDEBUG1, ("%.8X ", fifo_val));
word_ptr[buffer_ptr++] = fifo_val; //write to buffer
}
else
{
word_ptr[buffer_ptr++] = fifo_val; // write to buffer
} else {
buffer_ptr = 0;
return -2; // buffer overflow
}
if (status & PLB_LL_FIFO_STATUS_LL_EOF)
{
len = (buffer_ptr << 2) -3 + ( (status & PLB_LL_FIFO_STATUS_LL_REM)>>PLB_LL_FIFO_STATUS_LL_REM_SHIFT );
LOG(logDEBUG1, ("Len: %d\n",len));
if (status & PLB_LL_FIFO_STATUS_LL_EOF) {
len = (buffer_ptr << 2) - 3 +
((status & PLB_LL_FIFO_STATUS_LL_REM) >>
PLB_LL_FIFO_STATUS_LL_REM_SHIFT);
LOG(logDEBUG1, ("Len: %d\n", len));
buffer_ptr = 0;
return len;
}
}
}
}
while(!(status & PLB_LL_FIFO_STATUS_EMPTY));
} while (!(status & PLB_LL_FIFO_STATUS_EMPTY));
return 0;
}
int Local_ctrl_reg_write_mask(struct LocalLinkInterface* ll,unsigned int mask, unsigned int val) {
int Local_ctrl_reg_write_mask(struct LocalLinkInterface *ll, unsigned int mask,
unsigned int val) {
ll->ll_fifo_ctrl_reg &= (~mask);
ll->ll_fifo_ctrl_reg |= ( mask & val);
HWIO_xfs_out32(ll->ll_fifo_base+4*PLB_LL_FIFO_REG_CTRL,ll->ll_fifo_ctrl_reg);
ll->ll_fifo_ctrl_reg |= (mask & val);
HWIO_xfs_out32(ll->ll_fifo_base + 4 * PLB_LL_FIFO_REG_CTRL,
ll->ll_fifo_ctrl_reg);
return 1;
}
int Local_Test(struct LocalLinkInterface* ll,unsigned int buffer_len, void *buffer) {
int Local_Test(struct LocalLinkInterface *ll, unsigned int buffer_len,
void *buffer) {
int len;
unsigned int rec_buff_len = 4096;
unsigned int rec_buffer[4097];
Local_Write(ll,buffer_len,buffer);
Local_Write(ll, buffer_len, buffer);
usleep(10000);
do{
len = Local_Read(ll,rec_buff_len,rec_buffer);
LOG(logDEBUG1, ("receive length: %i\n",len));
do {
len = Local_Read(ll, rec_buff_len, rec_buffer);
LOG(logDEBUG1, ("receive length: %i\n", len));
if (len > 0) {
rec_buffer[len]=0;
LOG(logINFO, ("%s\n", (char*) rec_buffer));
rec_buffer[len] = 0;
LOG(logINFO, ("%s\n", (char *)rec_buffer));
}
} while(len > 0);
} while (len > 0);
return 1;
}

29
slsDetectorServers/eigerDetectorServer/LocalLinkInterface.h Executable file → Normal file
View File

@@ -2,20 +2,23 @@
#include "HardwareIO.h"
struct LocalLinkInterface{
struct LocalLinkInterface {
xfs_u32 ll_fifo_base;
unsigned int ll_fifo_ctrl_reg;
};
int Local_Init(struct LocalLinkInterface* ll,unsigned int ll_fifo_badr);
int Local_Reset1(struct LocalLinkInterface* ll,unsigned int rst_mask);
int Local_ctrl_reg_write_mask(struct LocalLinkInterface* ll,unsigned int mask, unsigned int val);
void Local_LocalLinkInterface1(struct LocalLinkInterface* ll,unsigned int ll_fifo_badr);
unsigned int Local_StatusVector(struct LocalLinkInterface* ll);
int Local_Reset(struct LocalLinkInterface* ll);
int Local_Write(struct LocalLinkInterface* ll,unsigned int buffer_len, void *buffer);
int Local_Read(struct LocalLinkInterface* ll,unsigned int buffer_len, void *buffer);
int Local_Test(struct LocalLinkInterface* ll,unsigned int buffer_len, void *buffer);
void Local_LocalLinkInterface(struct LocalLinkInterface* ll);
int Local_Init(struct LocalLinkInterface *ll, unsigned int ll_fifo_badr);
int Local_Reset1(struct LocalLinkInterface *ll, unsigned int rst_mask);
int Local_ctrl_reg_write_mask(struct LocalLinkInterface *ll, unsigned int mask,
unsigned int val);
void Local_LocalLinkInterface1(struct LocalLinkInterface *ll,
unsigned int ll_fifo_badr);
unsigned int Local_StatusVector(struct LocalLinkInterface *ll);
int Local_Reset(struct LocalLinkInterface *ll);
int Local_Write(struct LocalLinkInterface *ll, unsigned int buffer_len,
void *buffer);
int Local_Read(struct LocalLinkInterface *ll, unsigned int buffer_len,
void *buffer);
int Local_Test(struct LocalLinkInterface *ll, unsigned int buffer_len,
void *buffer);
void Local_LocalLinkInterface(struct LocalLinkInterface *ll);

973
slsDetectorServers/eigerDetectorServer/slsDetectorFunctionList.c Executable file → Normal file
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File diff suppressed because it is too large Load Diff

58
slsDetectorServers/eigerDetectorServer/slsDetectorServer_defs.h Executable file → Normal file
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@@ -10,8 +10,27 @@
#define STATUS_ERROR 2
/* Enums */
enum DACINDEX {E_SVP,E_VTR,E_VRF,E_VRS,E_SVN,E_VTGSTV,E_VCMP_LL,E_VCMP_LR,E_CAL,E_VCMP_RL,E_RXB_RB,E_RXB_LB,E_VCMP_RR,E_VCP,E_VCN,E_VIS,E_VTHRESHOLD};
#define DEFAULT_DAC_VALS { \
enum DACINDEX {
E_SVP,
E_VTR,
E_VRF,
E_VRS,
E_SVN,
E_VTGSTV,
E_VCMP_LL,
E_VCMP_LR,
E_CAL,
E_VCMP_RL,
E_RXB_RB,
E_RXB_LB,
E_VCMP_RR,
E_VCP,
E_VCN,
E_VIS,
E_VTHRESHOLD
};
#define DEFAULT_DAC_VALS \
{ \
0, /* SvP */ \
2480, /* Vtr */ \
3300, /* Vrf */ \
@@ -29,10 +48,19 @@ enum DACINDEX {E_SVP,E_VTR,E_VRF,E_VRS,E_SVN,E_VTGSTV,E_VCMP_LL,E_VCMP_L
2000, /* Vcn */ \
1550 /* Vis */ \
};
enum ADCINDEX {TEMP_FPGAEXT, TEMP_10GE, TEMP_DCDC, TEMP_SODL, TEMP_SODR, TEMP_FPGA, TEMP_FPGAFEBL, TEMP_FPGAFEBR};
enum NETWORKINDEX {TXN_LEFT, TXN_RIGHT, TXN_FRAME,FLOWCTRL_10G};
enum ROINDEX {E_PARALLEL, E_NON_PARALLEL};
enum CLKINDEX {RUN_CLK, NUM_CLOCKS};
enum ADCINDEX {
TEMP_FPGAEXT,
TEMP_10GE,
TEMP_DCDC,
TEMP_SODL,
TEMP_SODR,
TEMP_FPGA,
TEMP_FPGAFEBL,
TEMP_FPGAFEBR
};
enum NETWORKINDEX { TXN_LEFT, TXN_RIGHT, TXN_FRAME, FLOWCTRL_10G };
enum ROINDEX { E_PARALLEL, E_NON_PARALLEL };
enum CLKINDEX { RUN_CLK, NUM_CLOCKS };
#define CLK_NAMES "run"
/* Hardware Definitions */
@@ -40,13 +68,13 @@ enum CLKINDEX {RUN_CLK, NUM_CLOCKS};
#define NCHIP (4)
#define NDAC (16)
#define TEN_GIGA_BUFFER_SIZE (4112)
#define ONE_GIGA_BUFFER_SIZE (1040)
#define TEN_GIGA_CONSTANT (4)
#define ONE_GIGA_CONSTANT (16)
#define NORMAL_HIGHVOLTAGE_INPUTPORT "/sys/class/hwmon/hwmon5/device/in0_input"
#define NORMAL_HIGHVOLTAGE_OUTPUTPORT "/sys/class/hwmon/hwmon5/device/out0_output"
#define NORMAL_HIGHVOLTAGE_OUTPUTPORT \
"/sys/class/hwmon/hwmon5/device/out0_output"
#define SPECIAL9M_HIGHVOLTAGE_PORT "/dev/ttyS1"
#define SPECIAL9M_HIGHVOLTAGE_BUFFERSIZE (16)
#define DEFAULT_UDP_SOURCE_PORT (0xE185)
@@ -55,8 +83,8 @@ enum CLKINDEX {RUN_CLK, NUM_CLOCKS};
#define DEFAULT_NUM_FRAMES (1)
#define DEFAULT_STARTING_FRAME_NUMBER (1)
#define DEFAULT_NUM_CYCLES (1)
#define DEFAULT_EXPTIME (1E9) //ns
#define DEFAULT_PERIOD (1E9) //ns
#define DEFAULT_EXPTIME (1E9) // ns
#define DEFAULT_PERIOD (1E9) // ns
#define DEFAULT_DELAY (0)
#define DEFAULT_HIGH_VOLTAGE (0)
#define DEFAULT_SETTINGS (DYNAMICGAIN)
@@ -73,7 +101,7 @@ enum CLKINDEX {RUN_CLK, NUM_CLOCKS};
#define DEFAULT_PHOTON_ENERGY (-1)
#define DEFAULT_RATE_CORRECTION (0)
#define DEFAULT_EXT_GATING_ENABLE (0)
#define DEFAULT_EXT_GATING_POLARITY (1) //positive
#define DEFAULT_EXT_GATING_POLARITY (1) // positive
#define DEFAULT_TEST_MODE (0)
#define DEFAULT_HIGH_VOLTAGE (0)
@@ -86,12 +114,14 @@ enum CLKINDEX {RUN_CLK, NUM_CLOCKS};
#define DAC_MIN_MV (0)
#define DAC_MAX_MV (2048)
#define LTC2620_MIN_VAL (0) // including LTC defines instead of LTC262.h (includes bit banging and blackfin read and write)
#define LTC2620_MIN_VAL \
(0) // including LTC defines instead of LTC262.h (includes bit banging and
// blackfin read and write)
#define LTC2620_MAX_VAL (4095) // 12 bits
#define DAC_MAX_STEPS (4096)
#define MAX_SUBFRAME_EXPOSURE_VAL_IN_10NS (0x1FFFFFFF) /** 29 bit register for max subframe exposure value */
#define MAX_SUBFRAME_EXPOSURE_VAL_IN_10NS \
(0x1FFFFFFF) /** 29 bit register for max subframe exposure value */
#define SLAVE_HIGH_VOLTAGE_READ_VAL (-999)
#define HIGH_VOLTAGE_TOLERANCE (5)

8
slsDetectorServers/eigerDetectorServer/xfs_types.h Executable file → Normal file
View File

@@ -14,10 +14,8 @@ typedef signed int xfs_i32;
typedef signed short xfs_i16;
typedef signed char xfs_i8;
// UDP Header
struct udp_header_type
{
struct udp_header_type {
// ethternet frame (14 byte)
uint8_t dst_mac[6];
uint8_t src_mac[6];
@@ -41,8 +39,4 @@ struct udp_header_type
uint8_t dst_port[2];
uint8_t udp_message_len[2];
uint8_t udp_checksum[2];
};

62
slsDetectorServers/eigerDetectorServer/xparameters.h Executable file → Normal file
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@@ -1,4 +1,5 @@
/* ONLY THOSE ARE USED IN THIS SOFTWARE. If one of those is modified in xilinx compilation, this file should be replaced with updated values
/* ONLY THOSE ARE USED IN THIS SOFTWARE. If one of those is modified in xilinx
compilation, this file should be replaced with updated values
XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_RIGHT_BASEADDR
XPAR_PLB_LL_FIFO_AURORA_RX4_TX1_RIGHT_BASEADDR
XPAR_PLB_LL_FIFO_AURORA_RX4_TX1_LEFT_BASEADDR
@@ -24,27 +25,22 @@ XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR
/******************************************************************/
/* Definitions for peripheral BB_IO_SHIFT_REG_PPC440 */
#define XPAR_BB_IO_SHIFT_REG_PPC440_BASEADDR 0xD3000000
#define XPAR_BB_IO_SHIFT_REG_PPC440_HIGHADDR 0xD300FFFF
/* Definitions for peripheral EIGER_BEB_SYNCH_IO_PPC440 */
#define XPAR_EIGER_BEB_SYNCH_IO_PPC440_BASEADDR 0xD3100000
#define XPAR_EIGER_BEB_SYNCH_IO_PPC440_HIGHADDR 0xD310FFFF
/* Definitions for peripheral PLB_BRAM_10G */
#define XPAR_PLB_BRAM_10G_MEM0_BASEADDR 0xD4100000
#define XPAR_PLB_BRAM_10G_MEM0_HIGHADDR 0xD410FFFF
/* Definitions for peripheral PLB_BRAM_TEMAC */
#define XPAR_PLB_BRAM_TEMAC_MEM0_BASEADDR 0xD4000000
#define XPAR_PLB_BRAM_TEMAC_MEM0_HIGHADDR 0xD400FFFF
/* Definitions for peripheral PLB_GPIO_SYS */
#define XPAR_PLB_GPIO_SYS_BASEADDR 0xD1000000
#define XPAR_PLB_GPIO_SYS_HIGHADDR 0xD100FFFF
@@ -52,12 +48,9 @@ XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR
/** Command Generator */
#define XPAR_CMD_GENERATOR 0xC5000000
/** Version Numbers */
#define XPAR_VERSION 0xc6000000
/* Definitions for peripheral PLB_GPIO_TEST */
#define XPAR_PLB_GPIO_TEST_BASEADDR 0xD1010000
#define XPAR_PLB_GPIO_TEST_HIGHADDR 0xD101FFFF
@@ -66,9 +59,6 @@ XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR
#define UDP_HEADER_FRAME_NUMBER_LSB_OFST (0x0140)
#define UDP_HEADER_FRAME_NUMBER_MSB_OFST (0x0160)
/* Definitions for packet, frame and delay down counters */
#define XPAR_COUNTER_BASEADDR 0xD1020000
#define XPAR_COUNTER_HIGHADDR 0xD102FFFF
@@ -83,8 +73,6 @@ XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR
#define UDP_HEADER_GET_FNUM_10G_RIGHT_LSB_OFST (0x00C4)
#define UDP_HEADER_GET_FNUM_10G_RIGHT_MSB_OFST (0x00E4)
/* Definitions for peripheral PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT */
#define XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR 0xC4100000
#define XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_HIGHADDR 0xC410FFFF
@@ -92,46 +80,37 @@ XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR
/* Definitions for a new memory */
//#define XPAR_PLB_LL_NEW_MEMORY 0xD1000000//0xD1000084//0xC4200000
/* Definitions for peripheral PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_RIGHT */
#define XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_RIGHT_BASEADDR 0xC4110000
#define XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_RIGHT_HIGHADDR 0xC411FFFF
/* Definitions for peripheral PLB_LL_FIFO_AURORA_RX4_TX1_LEFT */
#define XPAR_PLB_LL_FIFO_AURORA_RX4_TX1_LEFT_BASEADDR 0xC4120000
#define XPAR_PLB_LL_FIFO_AURORA_RX4_TX1_LEFT_HIGHADDR 0xC412FFFF
/* Definitions for peripheral PLB_LL_FIFO_AURORA_RX4_TX1_RIGHT */
#define XPAR_PLB_LL_FIFO_AURORA_RX4_TX1_RIGHT_BASEADDR 0xC4130000
#define XPAR_PLB_LL_FIFO_AURORA_RX4_TX1_RIGHT_HIGHADDR 0xC413FFFF
/* Definitions for peripheral PLB_LL_FIFO_XAUI_10G */
#define XPAR_PLB_LL_FIFO_XAUI_10G_BASEADDR 0xC4140000
#define XPAR_PLB_LL_FIFO_XAUI_10G_HIGHADDR 0xC414FFFF
/* Definitions for peripheral PLB_V46_CPU_TO_PLB_V46_BRIDGED */
#define XPAR_PLB_V46_CPU_TO_PLB_V46_BRIDGED_BRIDGE_BASEADDR 0xCFFF0000
#define XPAR_PLB_V46_CPU_TO_PLB_V46_BRIDGED_BRIDGE_HIGHADDR 0xCFFFFFFF
#define XPAR_PLB_V46_CPU_TO_PLB_V46_BRIDGED_RNG0_BASEADDR 0xD0000000
#define XPAR_PLB_V46_CPU_TO_PLB_V46_BRIDGED_RNG0_HIGHADDR 0xDFFFFFFF
/* Definitions for peripheral PPC_SRAM */
#define XPAR_PPC_SRAM_BASEADDR 0x00000000
#define XPAR_PPC_SRAM_HIGHADDR 0x01FFFFFF
/******************************************************************/
/* Definitions for peripheral PFLASH */
#define XPAR_PFLASH_NUM_BANKS_MEM 1
/******************************************************************/
/* Definitions for peripheral PFLASH */
@@ -155,13 +134,11 @@ XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR
#define XPAR_PLB_SHT1X_IF_CH1_BASEADDR 0xD2200000
#define XPAR_PLB_SHT1X_IF_CH1_HIGHADDR 0xD220FFFF
/* Definitions for peripheral PLB_SHT1X_IF_CH2 */
#define XPAR_PLB_SHT1X_IF_CH2_DEVICE_ID 1
#define XPAR_PLB_SHT1X_IF_CH2_BASEADDR 0xD2210000
#define XPAR_PLB_SHT1X_IF_CH2_HIGHADDR 0xD221FFFF
/******************************************************************/
/* Definitions for driver UARTLITE */
@@ -176,10 +153,8 @@ XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR
#define XPAR_RS232_ODD_PARITY 0
#define XPAR_RS232_DATA_BITS 8
/******************************************************************/
/* Canonical definitions for peripheral RS232 */
#define XPAR_UARTLITE_0_DEVICE_ID XPAR_RS232_DEVICE_ID
#define XPAR_UARTLITE_0_BASEADDR 0xC0000000
@@ -190,7 +165,6 @@ XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR
#define XPAR_UARTLITE_0_DATA_BITS 8
#define XPAR_UARTLITE_0_SIO_CHAN 1
/******************************************************************/
/* Definitions for driver SPI */
@@ -205,7 +179,6 @@ XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR
#define XPAR_SPI_FLASH_NUM_SS_BITS 1
#define XPAR_SPI_FLASH_NUM_TRANSFER_BITS 8
/* Definitions for peripheral XPS_SPI_FEB_CFG */
#define XPAR_XPS_SPI_FEB_CFG_DEVICE_ID 1
#define XPAR_XPS_SPI_FEB_CFG_BASEADDR 0xD2010000
@@ -215,10 +188,8 @@ XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR
#define XPAR_XPS_SPI_FEB_CFG_NUM_SS_BITS 2
#define XPAR_XPS_SPI_FEB_CFG_NUM_TRANSFER_BITS 8
/******************************************************************/
/* Canonical definitions for peripheral SPI_FLASH */
#define XPAR_SPI_0_DEVICE_ID XPAR_SPI_FLASH_DEVICE_ID
#define XPAR_SPI_0_BASEADDR 0xD2000000
@@ -228,7 +199,6 @@ XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR
#define XPAR_SPI_0_NUM_SS_BITS 1
#define XPAR_SPI_0_NUM_TRANSFER_BITS 8
/* Canonical definitions for peripheral XPS_SPI_FEB_CFG */
#define XPAR_SPI_1_DEVICE_ID XPAR_XPS_SPI_FEB_CFG_DEVICE_ID
#define XPAR_SPI_1_BASEADDR 0xD2010000
@@ -238,7 +208,6 @@ XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR
#define XPAR_SPI_1_NUM_SS_BITS 2
#define XPAR_SPI_1_NUM_TRANSFER_BITS 8
/******************************************************************/
/* Definitions for driver LLTEMAC */
@@ -275,23 +244,18 @@ XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR
#define XPAR_LLTEMAC_0_MCAST_EXTEND 0
#define XPAR_LLTEMAC_0_INTR 1
/* LocalLink TYPE Enumerations */
#define XPAR_LL_FIFO 1
#define XPAR_LL_DMA 2
/* Canonical LocalLink parameters for TEMAC_INST */
/******************************************************************/
/* Definitions for peripheral XPS_BRAM_IF_CNTLR_PPC440 */
#define XPAR_XPS_BRAM_IF_CNTLR_PPC440_BASEADDR 0xFFFC0000
#define XPAR_XPS_BRAM_IF_CNTLR_PPC440_HIGHADDR 0xFFFFFFFF
/******************************************************************/
#define XPAR_INTC_MAX_NUM_INTR_INPUTS 5
@@ -306,7 +270,6 @@ XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR
#define XPAR_XPS_INTC_PPC440_HIGHADDR 0xC100FFFF
#define XPAR_XPS_INTC_PPC440_KIND_OF_INTR 0xFFFFFFF4
/******************************************************************/
#define XPAR_INTC_SINGLE_BASEADDR 0xC1000000
@@ -331,10 +294,14 @@ XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR
#define XPAR_INTC_0_HIGHADDR 0xC100FFFF
#define XPAR_INTC_0_KIND_OF_INTR 0xFFFFFFF4
#define XPAR_INTC_0_LLFIFO_0_VEC_ID XPAR_XPS_INTC_PPC440_XPS_LL_FIFO_TEMAC_IP2INTC_IRPT_INTR
#define XPAR_INTC_0_LLTEMAC_0_VEC_ID XPAR_XPS_INTC_PPC440_TEMAC_INST_TEMACINTC0_IRPT_INTR
#define XPAR_INTC_0_TMRCTR_0_VEC_ID XPAR_XPS_INTC_PPC440_XPS_TIMER_PPC440_INTERRUPT_INTR
#define XPAR_INTC_0_SPI_0_VEC_ID XPAR_XPS_INTC_PPC440_SPI_FLASH_IP2INTC_IRPT_INTR
#define XPAR_INTC_0_LLFIFO_0_VEC_ID \
XPAR_XPS_INTC_PPC440_XPS_LL_FIFO_TEMAC_IP2INTC_IRPT_INTR
#define XPAR_INTC_0_LLTEMAC_0_VEC_ID \
XPAR_XPS_INTC_PPC440_TEMAC_INST_TEMACINTC0_IRPT_INTR
#define XPAR_INTC_0_TMRCTR_0_VEC_ID \
XPAR_XPS_INTC_PPC440_XPS_TIMER_PPC440_INTERRUPT_INTR
#define XPAR_INTC_0_SPI_0_VEC_ID \
XPAR_XPS_INTC_PPC440_SPI_FLASH_IP2INTC_IRPT_INTR
#define XPAR_INTC_0_UARTLITE_0_VEC_ID XPAR_XPS_INTC_PPC440_RS232_INTERRUPT_INTR
/******************************************************************/
@@ -347,7 +314,6 @@ XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR
#define XPAR_XPS_LL_FIFO_TEMAC_BASEADDR 0xC4000000
#define XPAR_XPS_LL_FIFO_TEMAC_HIGHADDR 0xC400FFFF
/******************************************************************/
/* Canonical definitions for peripheral XPS_LL_FIFO_TEMAC */
@@ -355,7 +321,6 @@ XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR
#define XPAR_LLFIFO_0_BASEADDR 0xC4000000
#define XPAR_LLFIFO_0_HIGHADDR 0xC400FFFF
/******************************************************************/
/* Definitions for driver SYSMON */
@@ -367,17 +332,14 @@ XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR
#define XPAR_XPS_SYSMON_ADC_PPC440_HIGHADDR 0xD001FFFF
#define XPAR_XPS_SYSMON_ADC_PPC440_INCLUDE_INTR 1
/******************************************************************/
/* Canonical definitions for peripheral XPS_SYSMON_ADC_PPC440 */
#define XPAR_SYSMON_0_DEVICE_ID XPAR_XPS_SYSMON_ADC_PPC440_DEVICE_ID
#define XPAR_SYSMON_0_BASEADDR 0xD0010000
#define XPAR_SYSMON_0_HIGHADDR 0xD001FFFF
#define XPAR_SYSMON_0_INCLUDE_INTR 1
/******************************************************************/
/* Definitions for driver TMRCTR */
@@ -388,16 +350,13 @@ XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR
#define XPAR_XPS_TIMER_PPC440_BASEADDR 0xC2000000
#define XPAR_XPS_TIMER_PPC440_HIGHADDR 0xC200FFFF
/******************************************************************/
/* Canonical definitions for peripheral XPS_TIMER_PPC440 */
#define XPAR_TMRCTR_0_DEVICE_ID XPAR_XPS_TIMER_PPC440_DEVICE_ID
#define XPAR_TMRCTR_0_BASEADDR 0xC2000000
#define XPAR_TMRCTR_0_HIGHADDR 0xC200FFFF
/******************************************************************/
/* Definitions for bus frequencies */
@@ -553,4 +512,3 @@ XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR
#define XPAR_PPC440_VIRTEX5_HW_VER "1.01.a"
/******************************************************************/

61
slsDetectorServers/gotthard2DetectorServer/RegisterDefs.h
View File

@@ -1,9 +1,7 @@
#pragma once
#define REG_OFFSET (4)
/* Base addresses 0x1804 0000 ---------------------------------------------*/
/* Reconfiguration core for readout pll */
#define BASE_READOUT_PLL (0x0000) // 0x1804_0000 - 0x1804_07FF
@@ -39,9 +37,8 @@
/* UDP datagram generator */
#define BASE_UDP_RAM (0x01000) // 0x1806_1000 - 0x1806_1FFF
/* Clock Generation registers ------------------------------------------------------*/
/* Clock Generation registers
* ------------------------------------------------------*/
#define PLL_RESET_REG (0x00 * REG_OFFSET + BASE_CLK_GENERATION)
#define PLL_RESET_READOUT_OFST (0)
@@ -49,8 +46,6 @@
#define PLL_RESET_SYSTEM_OFST (1)
#define PLL_RESET_SYSTEM_MSK (0x00000001 << PLL_RESET_SYSTEM_OFST)
/* Control registers --------------------------------------------------*/
/* Module Control Board Serial Number register */
@@ -72,8 +67,9 @@
#define API_VERSION_OFST (0)
#define API_VERSION_MSK (0x00FFFFFF << API_VERSION_OFST)
#define API_VERSION_DETECTOR_TYPE_OFST (24) //Not used in software
#define API_VERSION_DETECTOR_TYPE_MSK (0x000000FF << API_VERSION_DETECTOR_TYPE_OFST) //Not used in software
#define API_VERSION_DETECTOR_TYPE_OFST (24) // Not used in software
#define API_VERSION_DETECTOR_TYPE_MSK \
(0x000000FF << API_VERSION_DETECTOR_TYPE_OFST) // Not used in software
/* Fix pattern register */
#define FIX_PATT_REG (0x03 * REG_OFFSET + BASE_CONTROL)
@@ -105,15 +101,14 @@
#define CONTROL_CLR_ACQSTN_FIFO_OFST (15)
#define CONTROL_CLR_ACQSTN_FIFO_MSK (0x00000001 << CONTROL_CLR_ACQSTN_FIFO_OFST)
#define CONTROL_TIMING_SOURCE_EXT_OFST (17)
#define CONTROL_TIMING_SOURCE_EXT_MSK (0x00000001 << CONTROL_TIMING_SOURCE_EXT_OFST)
#define CONTROL_TIMING_SOURCE_EXT_MSK \
(0x00000001 << CONTROL_TIMING_SOURCE_EXT_OFST)
#define CONTROL_PWR_CHIP_OFST (31)
#define CONTROL_PWR_CHIP_MSK (0x00000001 << CONTROL_PWR_CHIP_OFST)
/** DTA Offset Register */
#define DTA_OFFSET_REG (0x24 * REG_OFFSET + BASE_CONTROL)
/* ASIC registers --------------------------------------------------*/
/* ASIC Config register */
@@ -121,17 +116,25 @@
#define ASIC_CONFIG_RUN_MODE_OFST (0)
#define ASIC_CONFIG_RUN_MODE_MSK (0x00000003 << ASIC_CONFIG_RUN_MODE_OFST)
#define ASIC_CONFIG_RUN_MODE_INT_BURST_VAL ((0x1 << ASIC_CONFIG_RUN_MODE_OFST) & ASIC_CONFIG_RUN_MODE_MSK)
#define ASIC_CONFIG_RUN_MODE_CONT_VAL ((0x2 << ASIC_CONFIG_RUN_MODE_OFST) & ASIC_CONFIG_RUN_MODE_MSK)
#define ASIC_CONFIG_RUN_MODE_EXT_BURST_VAL ((0x3 << ASIC_CONFIG_RUN_MODE_OFST) & ASIC_CONFIG_RUN_MODE_MSK)
#define ASIC_CONFIG_RUN_MODE_INT_BURST_VAL \
((0x1 << ASIC_CONFIG_RUN_MODE_OFST) & ASIC_CONFIG_RUN_MODE_MSK)
#define ASIC_CONFIG_RUN_MODE_CONT_VAL \
((0x2 << ASIC_CONFIG_RUN_MODE_OFST) & ASIC_CONFIG_RUN_MODE_MSK)
#define ASIC_CONFIG_RUN_MODE_EXT_BURST_VAL \
((0x3 << ASIC_CONFIG_RUN_MODE_OFST) & ASIC_CONFIG_RUN_MODE_MSK)
#define ASIC_CONFIG_GAIN_OFST (4)
#define ASIC_CONFIG_GAIN_MSK (0x00000003 << ASIC_CONFIG_GAIN_OFST)
#define ASIC_CONFIG_DYNAMIC_GAIN_VAL ((0x0 << ASIC_CONFIG_GAIN_OFST) & ASIC_CONFIG_GAIN_MSK)
#define ASIC_CONFIG_FIX_GAIN_1_VAL ((0x1 << ASIC_CONFIG_GAIN_OFST) & ASIC_CONFIG_GAIN_MSK)
#define ASIC_CONFIG_FIX_GAIN_2_VAL ((0x2 << ASIC_CONFIG_GAIN_OFST) & ASIC_CONFIG_GAIN_MSK)
#define ASIC_CONFIG_RESERVED_VAL ((0x3 << ASIC_CONFIG_GAIN_OFST) & ASIC_CONFIG_GAIN_MSK)
#define ASIC_CONFIG_DYNAMIC_GAIN_VAL \
((0x0 << ASIC_CONFIG_GAIN_OFST) & ASIC_CONFIG_GAIN_MSK)
#define ASIC_CONFIG_FIX_GAIN_1_VAL \
((0x1 << ASIC_CONFIG_GAIN_OFST) & ASIC_CONFIG_GAIN_MSK)
#define ASIC_CONFIG_FIX_GAIN_2_VAL \
((0x2 << ASIC_CONFIG_GAIN_OFST) & ASIC_CONFIG_GAIN_MSK)
#define ASIC_CONFIG_RESERVED_VAL \
((0x3 << ASIC_CONFIG_GAIN_OFST) & ASIC_CONFIG_GAIN_MSK)
#define ASIC_CONFIG_CURRENT_SRC_EN_OFST (7)
#define ASIC_CONFIG_CURRENT_SRC_EN_MSK (0x00000001 << ASIC_CONFIG_CURRENT_SRC_EN_OFST)
#define ASIC_CONFIG_CURRENT_SRC_EN_MSK \
(0x00000001 << ASIC_CONFIG_CURRENT_SRC_EN_OFST)
#define ASIC_CONFIG_RST_DAC_OFST (15)
#define ASIC_CONFIG_RST_DAC_MSK (0x00000001 << ASIC_CONFIG_RST_DAC_OFST)
#define ASIC_CONFIG_DONE_OFST (31)
@@ -151,8 +154,6 @@
#define ASIC_INT_EXPTIME_LSB_REG (0x04 * REG_OFFSET + BASE_ASIC)
#define ASIC_INT_EXPTIME_MSB_REG (0x05 * REG_OFFSET + BASE_ASIC)
/* Packetizer -------------------------------------------------------------*/
/* Packetizer Config Register */
@@ -175,8 +176,8 @@
#define COORD_RESERVED_OFST (0)
#define COORD_RESERVED_MSK (0x0000FFFF << COORD_RESERVED_OFST)
#define COORD_ID_OFST (16) // Not connected in firmware TODO
#define COORD_ID_MSK (0x0000FFFF << COORD_ID_OFST) // Not connected in firmware TODO
#define COORD_ID_MSK \
(0x0000FFFF << COORD_ID_OFST) // Not connected in firmware TODO
/* Flow control registers --------------------------------------------------*/
@@ -186,13 +187,16 @@
#define FLOW_STATUS_RUN_BUSY_OFST (0)
#define FLOW_STATUS_RUN_BUSY_MSK (0x00000001 << FLOW_STATUS_RUN_BUSY_OFST)
#define FLOW_STATUS_WAIT_FOR_TRGGR_OFST (3)
#define FLOW_STATUS_WAIT_FOR_TRGGR_MSK (0x00000001 << FLOW_STATUS_WAIT_FOR_TRGGR_OFST)
#define FLOW_STATUS_WAIT_FOR_TRGGR_MSK \
(0x00000001 << FLOW_STATUS_WAIT_FOR_TRGGR_OFST)
#define FLOW_STATUS_DLY_BFRE_TRGGR_OFST (4)
#define FLOW_STATUS_DLY_BFRE_TRGGR_MSK (0x00000001 << FLOW_STATUS_DLY_BFRE_TRGGR_OFST)
#define FLOW_STATUS_DLY_BFRE_TRGGR_MSK \
(0x00000001 << FLOW_STATUS_DLY_BFRE_TRGGR_OFST)
#define FLOW_STATUS_FIFO_FULL_OFST (5)
#define FLOW_STATUS_FIFO_FULL_MSK (0x00000001 << FLOW_STATUS_FIFO_FULL_OFST)
#define FLOW_STATUS_DLY_AFTR_TRGGR_OFST (15)
#define FLOW_STATUS_DLY_AFTR_TRGGR_MSK (0x00000001 << FLOW_STATUS_DLY_AFTR_TRGGR_OFST)
#define FLOW_STATUS_DLY_AFTR_TRGGR_MSK \
(0x00000001 << FLOW_STATUS_DLY_AFTR_TRGGR_OFST)
#define FLOW_STATUS_CSM_BUSY_OFST (17)
#define FLOW_STATUS_CSM_BUSY_MSK (0x00000001 << FLOW_STATUS_CSM_BUSY_OFST)
@@ -216,7 +220,8 @@
#define TIME_FROM_START_LSB_REG (0x0A * REG_OFFSET + BASE_FLOW_CONTROL)
#define TIME_FROM_START_MSB_REG (0x0B * REG_OFFSET + BASE_FLOW_CONTROL)
/* Get Frames from Start 64 bit register (frames from last reset using CONTROL_CRST) */
/* Get Frames from Start 64 bit register (frames from last reset using
* CONTROL_CRST) */
#define FRAMES_FROM_START_LSB_REG (0x0C * REG_OFFSET + BASE_FLOW_CONTROL)
#define FRAMES_FROM_START_MSB_REG (0x0D * REG_OFFSET + BASE_FLOW_CONTROL)

778
slsDetectorServers/gotthard2DetectorServer/slsDetectorFunctionList.c
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File diff suppressed because it is too large Load Diff

98
slsDetectorServers/gotthard2DetectorServer/slsDetectorServer_defs.h
View File

@@ -44,17 +44,17 @@
#define DEFAULT_CURRENT_SOURCE (0)
#define DEFAULT_TIMING_SOURCE (TIMING_INTERNAL)
#define DEFAULT_READOUT_C0 (8)//(108333336) // rdo_clk, 108 MHz
#define DEFAULT_READOUT_C1 (8)//(108333336) // rdo_x2_clk, 108 MHz
#define DEFAULT_SYSTEM_C0 (5)//(144444448) // run_clk, 144 MHz
#define DEFAULT_SYSTEM_C1 (10)//(72222224) // chip_clk, 72 MHz
#define DEFAULT_SYSTEM_C2 (5)//(144444448) // sync_clk, 144 MHz
#define DEFAULT_SYSTEM_C3 (5)//(144444448) // str_clk, 144 MHz
#define DEFAULT_READOUT_C0 (8) //(108333336) // rdo_clk, 108 MHz
#define DEFAULT_READOUT_C1 (8) //(108333336) // rdo_x2_clk, 108 MHz
#define DEFAULT_SYSTEM_C0 (5) //(144444448) // run_clk, 144 MHz
#define DEFAULT_SYSTEM_C1 (10) //(72222224) // chip_clk, 72 MHz
#define DEFAULT_SYSTEM_C2 (5) //(144444448) // sync_clk, 144 MHz
#define DEFAULT_SYSTEM_C3 (5) //(144444448) // str_clk, 144 MHz
/* Firmware Definitions */
#define IP_HEADER_SIZE (20)
#define FIXED_PLL_FREQUENCY (20000000) // 20MHz
#define INT_SYSTEM_C0_FREQUENCY (144000000) //144 MHz
#define INT_SYSTEM_C0_FREQUENCY (144000000) // 144 MHz
#define READOUT_PLL_VCO_FREQ_HZ (866666688) // 866 MHz
#define SYSTEM_PLL_VCO_FREQ_HZ (722222224) // 722 MHz
@@ -62,41 +62,57 @@
#define BIT16_MASK (0xFFFF)
/* Enums */
enum DACINDEX {G2_VREF_H_ADC, /* 0 */ \
G2_DAC_UNUSED, /* 1 */ \
G2_VB_COMP_FE, /* 2 */ \
G2_VB_COMP_ADC, /* 3 */ \
G2_VCOM_CDS, /* 4 */ \
G2_VREF_RSTORE,/* 5 */ \
G2_VB_OPA_1ST, /* 6 */ \
G2_VREF_COMP_FE,/* 7 */ \
G2_VCOM_ADC1, /* 8 */ \
G2_VREF_PRECH, /* 9 */ \
G2_VREF_L_ADC, /* 10 */ \
G2_VREF_CDS, /* 11 */ \
G2_VB_CS, /* 12 */ \
G2_VB_OPA_FD, /* 13 */ \
G2_DAC_UNUSED2, /* 14 */ \
G2_VCOM_ADC2 /* 15*/ \
};
#define DAC_NAMES "vref_h_adc", "dac_unused", "vb_comp_fe", "vb_comp_adc", "vcom_cds", "vref_rstore", "vb_opa_1st", "vref_comp_fe", "vcom_adc1", "vref_prech", "vref_l_adc", "vref_cds", "vb_cs", "vb_opa_fd", "dac_unused2", "vcom_adc2"
enum DACINDEX {
G2_VREF_H_ADC, /* 0 */
G2_DAC_UNUSED, /* 1 */
G2_VB_COMP_FE, /* 2 */
G2_VB_COMP_ADC, /* 3 */
G2_VCOM_CDS, /* 4 */
G2_VREF_RSTORE, /* 5 */
G2_VB_OPA_1ST, /* 6 */
G2_VREF_COMP_FE, /* 7 */
G2_VCOM_ADC1, /* 8 */
G2_VREF_PRECH, /* 9 */
G2_VREF_L_ADC, /* 10 */
G2_VREF_CDS, /* 11 */
G2_VB_CS, /* 12 */
G2_VB_OPA_FD, /* 13 */
G2_DAC_UNUSED2, /* 14 */
G2_VCOM_ADC2 /* 15*/
};
#define DAC_NAMES \
"vref_h_adc", "dac_unused", "vb_comp_fe", "vb_comp_adc", "vcom_cds", \
"vref_rstore", "vb_opa_1st", "vref_comp_fe", "vcom_adc1", \
"vref_prech", "vref_l_adc", "vref_cds", "vb_cs", "vb_opa_fd", \
"dac_unused2", "vcom_adc2"
enum ONCHIP_DACINDEX {G2_VCHIP_COMP_FE, /* 0 */ \
G2_VCHIP_OPA_1ST, /* 1 */ \
G2_VCHIP_OPA_FD, /* 2 */ \
G2_VCHIP_COMP_ADC, /* 3 */ \
G2_VCHIP_UNUSED, /* 4 */ \
G2_VCHIP_REF_COMP_FE, /* 5 */ \
G2_VCHIP_CS /* 6 */ \
};
#define ONCHIP_DAC_NAMES "vchip_comp_fe", "vchip_opa_1st", "vchip_opa_fd", "vchip_comp_adc", "vchip_unused", "vchip_ref_comp_fe", "vchip_cs"
enum ONCHIP_DACINDEX {
G2_VCHIP_COMP_FE, /* 0 */
G2_VCHIP_OPA_1ST, /* 1 */
G2_VCHIP_OPA_FD, /* 2 */
G2_VCHIP_COMP_ADC, /* 3 */
G2_VCHIP_UNUSED, /* 4 */
G2_VCHIP_REF_COMP_FE, /* 5 */
G2_VCHIP_CS /* 6 */
};
#define ONCHIP_DAC_NAMES \
"vchip_comp_fe", "vchip_opa_1st", "vchip_opa_fd", "vchip_comp_adc", \
"vchip_unused", "vchip_ref_comp_fe", "vchip_cs"
enum CLKINDEX {
READOUT_C0,
READOUT_C1,
SYSTEM_C0,
SYSTEM_C1,
SYSTEM_C2,
SYSTEM_C3,
NUM_CLOCKS
};
#define CLK_NAMES \
"READOUT_C0", "READOUT_C1", "SYSTEM_C0", "SYSTEM_C1", "SYSTEM_C2", \
"SYSTEM_C3"
enum CLKINDEX {READOUT_C0, READOUT_C1, SYSTEM_C0, SYSTEM_C1, SYSTEM_C2, SYSTEM_C3, NUM_CLOCKS};
#define CLK_NAMES "READOUT_C0", "READOUT_C1", "SYSTEM_C0", "SYSTEM_C1", "SYSTEM_C2", "SYSTEM_C3"
enum PLLINDEX {READOUT_PLL, SYSTEM_PLL};
enum PLLINDEX { READOUT_PLL, SYSTEM_PLL };
/** Chip Definitions */
#define ASIC_ADDR_MAX_BITS (4)
@@ -124,13 +140,13 @@ typedef struct udp_header_struct {
uint16_t udp_destmac_lsb;
uint32_t udp_srcmac_lsb;
uint8_t ip_tos;
uint8_t ip_ihl: 4, ip_ver: 4;
uint8_t ip_ihl : 4, ip_ver : 4;
uint16_t udp_ethertype;
uint16_t ip_identification;
uint16_t ip_totallength;
uint8_t ip_protocol;
uint8_t ip_ttl;
uint16_t ip_fragmentoffset: 13, ip_flags: 3;
uint16_t ip_fragmentoffset : 13, ip_flags : 3;
uint16_t ip_srcip_msb;
uint16_t ip_checksum;
uint16_t ip_destip_msb;

69
slsDetectorServers/gotthardDetectorServer/RegisterDefs.h Executable file → Normal file
View File

@@ -8,11 +8,16 @@
#define GAIN_CONFGAIN_OFST (0)
#define GAIN_CONFGAIN_MSK (0x000000FF << GAIN_CONFGAIN_OFST)
#define GAIN_CONFGAIN_HGH_GAIN_VAL ((0x0 << GAIN_CONFGAIN_OFST) & GAIN_CONFGAIN_MSK)
#define GAIN_CONFGAIN_DYNMC_GAIN_VAL ((0x8 << GAIN_CONFGAIN_OFST) & GAIN_CONFGAIN_MSK)
#define GAIN_CONFGAIN_LW_GAIN_VAL ((0x6 << GAIN_CONFGAIN_OFST) & GAIN_CONFGAIN_MSK)
#define GAIN_CONFGAIN_MDM_GAIN_VAL ((0x2 << GAIN_CONFGAIN_OFST) & GAIN_CONFGAIN_MSK)
#define GAIN_CONFGAIN_VRY_HGH_GAIN_VAL ((0x1 << GAIN_CONFGAIN_OFST) & GAIN_CONFGAIN_MSK)
#define GAIN_CONFGAIN_HGH_GAIN_VAL \
((0x0 << GAIN_CONFGAIN_OFST) & GAIN_CONFGAIN_MSK)
#define GAIN_CONFGAIN_DYNMC_GAIN_VAL \
((0x8 << GAIN_CONFGAIN_OFST) & GAIN_CONFGAIN_MSK)
#define GAIN_CONFGAIN_LW_GAIN_VAL \
((0x6 << GAIN_CONFGAIN_OFST) & GAIN_CONFGAIN_MSK)
#define GAIN_CONFGAIN_MDM_GAIN_VAL \
((0x2 << GAIN_CONFGAIN_OFST) & GAIN_CONFGAIN_MSK)
#define GAIN_CONFGAIN_VRY_HGH_GAIN_VAL \
((0x1 << GAIN_CONFGAIN_OFST) & GAIN_CONFGAIN_MSK)
/** Flow Control register */
//#define FLOW_CONTROL_REG (0x11 << MEM_MAP_SHIFT)
@@ -60,12 +65,16 @@
#define DAQ_TKN_TMNG_OFST (0)
#define DAQ_TKN_TMNG_MSK (0x0000FFFF << DAQ_TKN_TMNG_OFST)
#define DAQ_TKN_TMNG_BRD_RVSN_1_VAL ((0x1f16 << DAQ_TKN_TMNG_OFST) & DAQ_TKN_TMNG_MSK)
#define DAQ_TKN_TMNG_BRD_RVSN_2_VAL ((0x1f10 << DAQ_TKN_TMNG_OFST) & DAQ_TKN_TMNG_MSK)
#define DAQ_TKN_TMNG_BRD_RVSN_1_VAL \
((0x1f16 << DAQ_TKN_TMNG_OFST) & DAQ_TKN_TMNG_MSK)
#define DAQ_TKN_TMNG_BRD_RVSN_2_VAL \
((0x1f10 << DAQ_TKN_TMNG_OFST) & DAQ_TKN_TMNG_MSK)
#define DAQ_PCKT_LNGTH_OFST (16)
#define DAQ_PCKT_LNGTH_MSK (0x0000FFFF << DAQ_PCKT_LNGTH_OFST)
#define DAQ_PCKT_LNGTH_NO_ROI_VAL ((0x0013f << DAQ_PCKT_LNGTH_OFST) & DAQ_PCKT_LNGTH_MSK)
#define DAQ_PCKT_LNGTH_ROI_VAL ((0x0007f << DAQ_PCKT_LNGTH_OFST) & DAQ_PCKT_LNGTH_MSK)
#define DAQ_PCKT_LNGTH_NO_ROI_VAL \
((0x0013f << DAQ_PCKT_LNGTH_OFST) & DAQ_PCKT_LNGTH_MSK)
#define DAQ_PCKT_LNGTH_ROI_VAL \
((0x0007f << DAQ_PCKT_LNGTH_OFST) & DAQ_PCKT_LNGTH_MSK)
/** Time From Start register */
//#define TIME_FROM_START_REG (0x16 << MEM_MAP_SHIFT)
@@ -95,27 +104,37 @@
#define ADC_SYNC_ENET_STRT_DLY_OFST (0)
#define ADC_SYNC_ENET_STRT_DLY_MSK (0x0000000F << ADC_SYNC_ENET_STRT_DLY_OFST)
#define ADC_SYNC_ENET_STRT_DLY_VAL ((0x4 << ADC_SYNC_ENET_STRT_DLY_OFST) & ADC_SYNC_ENET_STRT_DLY_MSK)
#define ADC_SYNC_ENET_STRT_DLY_VAL \
((0x4 << ADC_SYNC_ENET_STRT_DLY_OFST) & ADC_SYNC_ENET_STRT_DLY_MSK)
#define ADC_SYNC_TKN1_HGH_DLY_OFST (4)
#define ADC_SYNC_TKN1_HGH_DLY_MSK (0x0000000F << ADC_SYNC_TKN1_HGH_DLY_OFST)
#define ADC_SYNC_TKN1_HGH_DLY_VAL ((0x1 << ADC_SYNC_TKN1_HGH_DLY_OFST) & ADC_SYNC_TKN1_HGH_DLY_MSK)
#define ADC_SYNC_TKN1_HGH_DLY_VAL \
((0x1 << ADC_SYNC_TKN1_HGH_DLY_OFST) & ADC_SYNC_TKN1_HGH_DLY_MSK)
#define ADC_SYNC_TKN2_HGH_DLY_OFST (8)
#define ADC_SYNC_TKN2_HGH_DLY_MSK (0x0000000F << ADC_SYNC_TKN2_HGH_DLY_OFST)
#define ADC_SYNC_TKN2_HGH_DLY_VAL ((0x2 << ADC_SYNC_TKN2_HGH_DLY_OFST) & ADC_SYNC_TKN2_HGH_DLY_MSK)
#define ADC_SYNC_TKN2_HGH_DLY_VAL \
((0x2 << ADC_SYNC_TKN2_HGH_DLY_OFST) & ADC_SYNC_TKN2_HGH_DLY_MSK)
#define ADC_SYNC_TKN1_LOW_DLY_OFST (12)
#define ADC_SYNC_TKN1_LOW_DLY_MSK (0x0000000F << ADC_SYNC_TKN1_LOW_DLY_OFST)
#define ADC_SYNC_TKN1_LOW_DLY_VAL ((0x2 << ADC_SYNC_TKN1_LOW_DLY_OFST) & ADC_SYNC_TKN1_LOW_DLY_MSK)
#define ADC_SYNC_TKN1_LOW_DLY_VAL \
((0x2 << ADC_SYNC_TKN1_LOW_DLY_OFST) & ADC_SYNC_TKN1_LOW_DLY_MSK)
#define ADC_SYNC_TKN2_LOW_DLY_OFST (16)
#define ADC_SYNC_TKN2_LOW_DLY_MSK (0x0000000F << ADC_SYNC_TKN2_LOW_DLY_OFST)
#define ADC_SYNC_TKN2_LOW_DLY_VAL ((0x3 << ADC_SYNC_TKN2_LOW_DLY_OFST) & ADC_SYNC_TKN2_LOW_DLY_MSK)
//0x32214
#define ADC_SYNC_TKN_VAL (ADC_SYNC_ENET_STRT_DLY_VAL | ADC_SYNC_TKN1_HGH_DLY_VAL | ADC_SYNC_TKN2_HGH_DLY_VAL | ADC_SYNC_TKN1_LOW_DLY_VAL | ADC_SYNC_TKN2_LOW_DLY_VAL)
#define ADC_SYNC_TKN2_LOW_DLY_VAL \
((0x3 << ADC_SYNC_TKN2_LOW_DLY_OFST) & ADC_SYNC_TKN2_LOW_DLY_MSK)
// 0x32214
#define ADC_SYNC_TKN_VAL \
(ADC_SYNC_ENET_STRT_DLY_VAL | ADC_SYNC_TKN1_HGH_DLY_VAL | \
ADC_SYNC_TKN2_HGH_DLY_VAL | ADC_SYNC_TKN1_LOW_DLY_VAL | \
ADC_SYNC_TKN2_LOW_DLY_VAL)
#define ADC_SYNC_CLEAN_FIFOS_OFST (20)
#define ADC_SYNC_CLEAN_FIFOS_MSK (0x00000001 << ADC_SYNC_CLEAN_FIFOS_OFST)
#define ADC_SYNC_ENET_DELAY_OFST (24)
#define ADC_SYNC_ENET_DELAY_MSK (0x000000FF << ADC_SYNC_ENET_DELAY_OFST)
#define ADC_SYNC_ENET_DELAY_NO_ROI_VAL ((0x88 << ADC_SYNC_ENET_DELAY_OFST) & ADC_SYNC_ENET_DELAY_MSK)
#define ADC_SYNC_ENET_DELAY_ROI_VAL ((0x1b << ADC_SYNC_ENET_DELAY_OFST) & ADC_SYNC_ENET_DELAY_MSK)
#define ADC_SYNC_ENET_DELAY_NO_ROI_VAL \
((0x88 << ADC_SYNC_ENET_DELAY_OFST) & ADC_SYNC_ENET_DELAY_MSK)
#define ADC_SYNC_ENET_DELAY_ROI_VAL \
((0x1b << ADC_SYNC_ENET_DELAY_OFST) & ADC_SYNC_ENET_DELAY_MSK)
/** Time From Start register */
//#define MU_TIME_REG (0x1a << MEM_MAP_SHIFT)
@@ -131,7 +150,9 @@
#define TEMP_SPI_IN_T2_CLK_MSK (0x00000001 << TEMP_SPI_IN_T2_CLK_OFST)
#define TEMP_SPI_IN_T2_CS_OFST (3)
#define TEMP_SPI_IN_T2_CS_MSK (0x00000001 << TEMP_SPI_IN_T2_CS_OFST)
#define TEMP_SPI_IN_IDLE_MSK (TEMP_SPI_IN_T1_CS_MSK | TEMP_SPI_IN_T2_CS_MSK | TEMP_SPI_IN_T1_CLK_MSK | TEMP_SPI_IN_T2_CLK_MSK)
#define TEMP_SPI_IN_IDLE_MSK \
(TEMP_SPI_IN_T1_CS_MSK | TEMP_SPI_IN_T2_CS_MSK | TEMP_SPI_IN_T1_CLK_MSK | \
TEMP_SPI_IN_T2_CLK_MSK)
/** Temperatre SPI Out register */
#define TEMP_SPI_OUT_REG (0x1c << MEM_MAP_SHIFT)
@@ -171,7 +192,8 @@
#define FPGA_VERSION_REG (0x22 << MEM_MAP_SHIFT)
#define FPGA_VERSION_OFST (0)
#define FPGA_VERSION_MSK (0x00FFFFFF << FPGA_VERSION_OFST) // to get in format yymmdd
#define FPGA_VERSION_MSK \
(0x00FFFFFF << FPGA_VERSION_OFST) // to get in format yymmdd
/* Fix Pattern register */
#define FIX_PATT_REG (0x23 << MEM_MAP_SHIFT)
@@ -260,7 +282,8 @@
#define EXT_SIGNAL_MSK (0x00000007 << EXT_SIGNAL_OFST)
#define EXT_SIGNAL_OFF_VAL ((0x0 << EXT_SIGNAL_OFST) & EXT_SIGNAL_MSK)
#define EXT_SIGNAL_TRGGR_IN_RSNG_VAL ((0x3 << EXT_SIGNAL_OFST) & EXT_SIGNAL_MSK)
#define EXT_SIGNAL_TRGGR_IN_FLLNG_VAL ((0x4 << EXT_SIGNAL_OFST) & EXT_SIGNAL_MSK)
#define EXT_SIGNAL_TRGGR_IN_FLLNG_VAL \
((0x4 << EXT_SIGNAL_OFST) & EXT_SIGNAL_MSK)
/** Look at me register */
//#define LOOK_AT_ME_REG (0x28 << MEM_MAP_SHIFT)
@@ -274,7 +297,8 @@
#define CHIP_OF_INTRST_ADC_SEL_OFST (0)
#define CHIP_OF_INTRST_ADC_SEL_MSK (0x0000001F << CHIP_OF_INTRST_ADC_SEL_OFST)
#define CHIP_OF_INTRST_NUM_CHNNLS_OFST (16)
#define CHIP_OF_INTRST_NUM_CHNNLS_MSK (0x0000FFFF << CHIP_OF_INTRST_NUM_CHNNLS_OFST)
#define CHIP_OF_INTRST_NUM_CHNNLS_MSK \
(0x0000FFFF << CHIP_OF_INTRST_NUM_CHNNLS_OFST)
/** Out MUX register */
//#define OUT_MUX_REG (0x2b << MEM_MAP_SHIFT)
@@ -366,4 +390,3 @@
/* Counter Block Memory starting address */
#define COUNTER_MEMORY_REG (0x85 << MEM_MAP_SHIFT)

591
slsDetectorServers/gotthardDetectorServer/slsDetectorFunctionList.c Executable file → Normal file
View File

File diff suppressed because it is too large Load Diff

49
slsDetectorServers/gotthardDetectorServer/slsDetectorServer_defs.h Executable file → Normal file
View File

@@ -3,12 +3,22 @@
#include <stdlib.h>
/* Enums */
enum ADCINDEX {TEMP_FPGA, TEMP_ADC};
enum DACINDEX {G_VREF_DS, G_VCASCN_PB, G_VCASCP_PB, G_VOUT_CM, G_VCASC_OUT, G_VIN_CM, G_VREF_COMP, G_IB_TESTC};
enum CLKINDEX {ADC_CLK, NUM_CLOCKS};
enum ADCINDEX { TEMP_FPGA, TEMP_ADC };
enum DACINDEX {
G_VREF_DS,
G_VCASCN_PB,
G_VCASCP_PB,
G_VOUT_CM,
G_VCASC_OUT,
G_VIN_CM,
G_VREF_COMP,
G_IB_TESTC
};
enum CLKINDEX { ADC_CLK, NUM_CLOCKS };
#define CLK_NAMES "adc"
#define DEFAULT_DAC_VALS { \
#define DEFAULT_DAC_VALS \
{ \
660, /* G_VREF_DS */ \
650, /* G_VCASCN_PB */ \
1480, /* G_VCASCP_PB */ \
@@ -34,10 +44,12 @@ enum CLKINDEX {ADC_CLK, NUM_CLOCKS};
#define CLK_FREQ (32007729) /* Hz */
/** Firmware Definitions */
#define IP_PACKET_SIZE_NO_ROI (NCHIP * (NCHAN / 2) * 2 + 14 + 20) // 2 packets, so divide by 2
#define IP_PACKET_SIZE_NO_ROI \
(NCHIP * (NCHAN / 2) * 2 + 14 + 20) // 2 packets, so divide by 2
#define IP_PACKET_SIZE_ROI (NCHIPS_PER_ADC * NCHAN * 2 + 14 + 20)
#define UDP_PACKETSIZE_NO_ROI (NCHIP * (NCHAN / 2) * 2 + 4 + 8 + 2) // 2 packets, so divide by 2
#define UDP_PACKETSIZE_NO_ROI \
(NCHIP * (NCHAN / 2) * 2 + 4 + 8 + 2) // 2 packets, so divide by 2
#define UDP_PACKETSIZE_ROI (NCHIPS_PER_ADC * NCHAN * 2 + 4 + 8 + 2)
/** Default Parameters */
@@ -57,7 +69,7 @@ enum CLKINDEX {ADC_CLK, NUM_CLOCKS};
#define DAC_MAX_MV (2500)
/** ENEt conf structs */
typedef struct mac_header_struct{
typedef struct mac_header_struct {
u_int8_t mac_dest_mac2;
u_int8_t mac_dest_mac1;
u_int8_t mac_dummy1;
@@ -78,8 +90,8 @@ typedef struct mac_header_struct{
typedef struct ip_header_struct {
u_int16_t ip_len;
u_int8_t ip_tos;
u_int8_t ip_ihl:4 ,ip_ver:4;
u_int16_t ip_offset:13,ip_flag:3;
u_int8_t ip_ihl : 4, ip_ver : 4;
u_int16_t ip_offset : 13, ip_flag : 3;
u_int16_t ip_ident;
u_int16_t ip_chksum;
u_int8_t ip_protocol;
@@ -88,14 +100,14 @@ typedef struct ip_header_struct {
u_int32_t ip_destip;
} ip_header;
typedef struct udp_header_struct{
typedef struct udp_header_struct {
u_int16_t udp_destport;
u_int16_t udp_srcport;
u_int16_t udp_chksum;
u_int16_t udp_len;
} udp_header;
typedef struct mac_conf_struct{
typedef struct mac_conf_struct {
mac_header mac;
ip_header ip;
udp_header udp;
@@ -105,23 +117,22 @@ typedef struct mac_conf_struct{
u_int32_t cdone;
} mac_conf;
typedef struct tse_conf_struct{
u_int32_t rev; //0x0
typedef struct tse_conf_struct {
u_int32_t rev; // 0x0
u_int32_t scratch;
u_int32_t command_config;
u_int32_t mac_0; //0x3
u_int32_t mac_0; // 0x3
u_int32_t mac_1;
u_int32_t frm_length;
u_int32_t pause_quant;
u_int32_t rx_section_empty; //0x7
u_int32_t rx_section_empty; // 0x7
u_int32_t rx_section_full;
u_int32_t tx_section_empty;
u_int32_t tx_section_full;
u_int32_t rx_almost_empty; //0xB
u_int32_t rx_almost_empty; // 0xB
u_int32_t rx_almost_full;
u_int32_t tx_almost_empty;
u_int32_t tx_almost_full;
u_int32_t mdio_addr0; //0xF
u_int32_t mdio_addr0; // 0xF
u_int32_t mdio_addr1;
}tse_conf;
} tse_conf;

270
slsDetectorServers/jungfrauDetectorServer/RegisterDefs.h Executable file → Normal file
View File

@@ -11,8 +11,6 @@
#define DETECTOR_TYPE_OFST (24)
#define DETECTOR_TYPE_MSK (0x000000FF << DETECTOR_TYPE_OFST)
/* Fix pattern register */
#define FIX_PATT_REG (0x01 << MEM_MAP_SHIFT)
@@ -25,35 +23,38 @@
#define RUN_BUSY_MSK (0x00000001 << RUN_BUSY_OFST)
#define WAITING_FOR_TRIGGER_OFST (3)
#define WAITING_FOR_TRIGGER_MSK (0x00000001 << WAITING_FOR_TRIGGER_OFST)
#define DELAYBEFORE_OFST (4) //Not used in software
#define DELAYBEFORE_MSK (0x00000001 << DELAYBEFORE_OFST) //Not used in software
#define DELAYAFTER_OFST (5) //Not used in software
#define DELAYAFTER_MSK (0x00000001 << DELAYAFTER_OFST) //Not used in software
#define DELAYBEFORE_OFST (4) // Not used in software
#define DELAYBEFORE_MSK (0x00000001 << DELAYBEFORE_OFST) // Not used in software
#define DELAYAFTER_OFST (5) // Not used in software
#define DELAYAFTER_MSK (0x00000001 << DELAYAFTER_OFST) // Not used in software
#define STOPPED_OFST (15)
#define STOPPED_MSK (0x00000001 << STOPPED_OFST)
#define RUNMACHINE_BUSY_OFST (17)
#define RUNMACHINE_BUSY_MSK (0x00000001 << RUNMACHINE_BUSY_OFST)
/* Look at me register */
#define LOOK_AT_ME_REG (0x03 << MEM_MAP_SHIFT) //Not used in firmware or software
#define LOOK_AT_ME_REG \
(0x03 << MEM_MAP_SHIFT) // Not used in firmware or software
/* System Status register */
#define SYSTEM_STATUS_REG (0x04 << MEM_MAP_SHIFT) //Not used in software
#define DDR3_CAL_DONE_OFST (0) //Not used in software
#define DDR3_CAL_DONE_MSK (0x00000001 << DDR3_CAL_DONE_OFST) //Not used in software
#define DDR3_CAL_FAIL_OFST (1) //Not used in software
#define DDR3_CAL_FAIL_MSK (0x00000001 << DDR3_CAL_FAIL_OFST) //Not used in software
#define DDR3_INIT_DONE_OFST (2) //Not used in software
#define DDR3_INIT_DONE_MSK (0x00000001 << DDR3_INIT_DONE_OFST) //Not used in software
#define RECONFIG_PLL_LCK_OFST (3) //Not used in software
#define RECONFIG_PLL_LCK_MSK (0x00000001 << RECONFIG_PLL_LCK_OFST) //Not used in software
#define PLL_A_LCK_OFST (4) //Not used in software
#define PLL_A_LCK_MSK (0x00000001 << PLL_A_LCK_OFST) //Not used in software
#define DD3_PLL_LCK_OFST (5) //Not used in software
#define DD3_PLL_LCK_MSK (0x00000001 << DD3_PLL_LCK_OFST) //Not used in software
#define SYSTEM_STATUS_REG (0x04 << MEM_MAP_SHIFT) // Not used in software
#define DDR3_CAL_DONE_OFST (0) // Not used in software
#define DDR3_CAL_DONE_MSK \
(0x00000001 << DDR3_CAL_DONE_OFST) // Not used in software
#define DDR3_CAL_FAIL_OFST (1) // Not used in software
#define DDR3_CAL_FAIL_MSK \
(0x00000001 << DDR3_CAL_FAIL_OFST) // Not used in software
#define DDR3_INIT_DONE_OFST (2) // Not used in software
#define DDR3_INIT_DONE_MSK \
(0x00000001 << DDR3_INIT_DONE_OFST) // Not used in software
#define RECONFIG_PLL_LCK_OFST (3) // Not used in software
#define RECONFIG_PLL_LCK_MSK \
(0x00000001 << RECONFIG_PLL_LCK_OFST) // Not used in software
#define PLL_A_LCK_OFST (4) // Not used in software
#define PLL_A_LCK_MSK (0x00000001 << PLL_A_LCK_OFST) // Not used in software
#define DD3_PLL_LCK_OFST (5) // Not used in software
#define DD3_PLL_LCK_MSK (0x00000001 << DD3_PLL_LCK_OFST) // Not used in software
/* Module Control Board Serial Number Register */
#define MOD_SERIAL_NUM_REG (0x0A << MEM_MAP_SHIFT)
@@ -62,16 +63,17 @@
#define HARDWARE_SERIAL_NUM_MSK (0x000000FF << HARDWARE_SERIAL_NUM_OFST)
#define HARDWARE_VERSION_NUM_OFST (16)
#define HARDWARE_VERSION_NUM_MSK (0x0000003F << HARDWARE_VERSION_NUM_OFST)
#define HARDWARE_VERSION_2_VAL ((0x2 << HARDWARE_VERSION_NUM_OFST) & HARDWARE_VERSION_NUM_MSK)
#define HARDWARE_VERSION_2_VAL \
((0x2 << HARDWARE_VERSION_NUM_OFST) & HARDWARE_VERSION_NUM_MSK)
/* API Version Register */
#define API_VERSION_REG (0x0F << MEM_MAP_SHIFT)
#define API_VERSION_OFST (0)
#define API_VERSION_MSK (0x00FFFFFF << API_VERSION_OFST)
#define API_VERSION_DETECTOR_TYPE_OFST (24) //Not used in software
#define API_VERSION_DETECTOR_TYPE_MSK (0x000000FF << API_VERSION_DETECTOR_TYPE_OFST) //Not used in software
#define API_VERSION_DETECTOR_TYPE_OFST (24) // Not used in software
#define API_VERSION_DETECTOR_TYPE_MSK \
(0x000000FF << API_VERSION_DETECTOR_TYPE_OFST) // Not used in software
/* Time from Start 64 bit register */
#define TIME_FROM_START_LSB_REG (0x10 << MEM_MAP_SHIFT)
@@ -94,14 +96,17 @@
#define GET_PERIOD_MSB_REG (0x19 << MEM_MAP_SHIFT)
/** Get Temperature Carlos, incorrectl as get gates */
#define GET_TEMPERATURE_TMP112_REG (0x1c << MEM_MAP_SHIFT) // (after multiplying by 625) in 10ths of millidegrees of TMP112
#define GET_TEMPERATURE_TMP112_REG \
(0x1c << MEM_MAP_SHIFT) // (after multiplying by 625) in 10ths of
// millidegrees of TMP112
#define TEMPERATURE_VALUE_BIT (0)
#define TEMPERATURE_VALUE_MSK (0x000007FF << TEMPERATURE_VALUE_BIT)
#define TEMPERATURE_POLARITY_BIT (11)
#define TEMPERATURE_POLARITY_MSK (0x00000001 << TEMPERATURE_POLARITY_BIT)
/* Get Frames from Start 64 bit register (frames from last reset using CONTROL_CRST) */
/* Get Frames from Start 64 bit register (frames from last reset using
* CONTROL_CRST) */
#define FRAMES_FROM_START_LSB_REG (0x22 << MEM_MAP_SHIFT)
#define FRAMES_FROM_START_MSB_REG (0x23 << MEM_MAP_SHIFT)
@@ -157,19 +162,25 @@
/* Configuration Register */
#define CONFIG_REG (0x4D << MEM_MAP_SHIFT)
// readout timer (from chip) to stabilize (esp in burst acquisition mode) tRDT = (RDT + 1) * 25ns
// readout timer (from chip) to stabilize (esp in burst acquisition mode) tRDT =
// (RDT + 1) * 25ns
#define CONFIG_RDT_TMR_OFST (0)
#define CONFIG_RDT_TMR_MSK (0x0000FFFF << CONFIG_RDT_TMR_OFST)
#define CONFIG_OPRTN_MDE_2_X_10GbE_OFST (16)
#define CONFIG_OPRTN_MDE_2_X_10GbE_MSK (0x00000001 << CONFIG_OPRTN_MDE_2_X_10GbE_OFST)
#define CONFIG_OPRTN_MDE_2_X_10GbE_MSK \
(0x00000001 << CONFIG_OPRTN_MDE_2_X_10GbE_OFST)
// if 0, outer is the primary interface
#define CONFIG_INNR_PRIMRY_INTRFCE_OFST (17)
#define CONFIG_INNR_PRIMRY_INTRFCE_MSK (0x00000001 << CONFIG_INNR_PRIMRY_INTRFCE_OFST)
#define CONFIG_INNR_PRIMRY_INTRFCE_MSK \
(0x00000001 << CONFIG_INNR_PRIMRY_INTRFCE_OFST)
#define CONFIG_READOUT_SPEED_OFST (20)
#define CONFIG_READOUT_SPEED_MSK (0x00000003 << CONFIG_READOUT_SPEED_OFST)
#define CONFIG_QUARTER_SPEED_10MHZ_VAL ((0x0 << CONFIG_READOUT_SPEED_OFST) & CONFIG_READOUT_SPEED_MSK)
#define CONFIG_HALF_SPEED_20MHZ_VAL ((0x1 << CONFIG_READOUT_SPEED_OFST) & CONFIG_READOUT_SPEED_MSK)
#define CONFIG_FULL_SPEED_40MHZ_VAL ((0x2 << CONFIG_READOUT_SPEED_OFST) & CONFIG_READOUT_SPEED_MSK)
#define CONFIG_QUARTER_SPEED_10MHZ_VAL \
((0x0 << CONFIG_READOUT_SPEED_OFST) & CONFIG_READOUT_SPEED_MSK)
#define CONFIG_HALF_SPEED_20MHZ_VAL \
((0x1 << CONFIG_READOUT_SPEED_OFST) & CONFIG_READOUT_SPEED_MSK)
#define CONFIG_FULL_SPEED_40MHZ_VAL \
((0x2 << CONFIG_READOUT_SPEED_OFST) & CONFIG_READOUT_SPEED_MSK)
#define CONFIG_TDMA_ENABLE_OFST (24)
#define CONFIG_TDMA_ENABLE_MSK (0x00000001 << CONFIG_TDMA_ENABLE_OFST)
#define CONFIG_TDMA_TIMESLOT_OFST (25) // 1ms
@@ -192,29 +203,34 @@
#define CONTROL_STOP_ACQ_MSK (0x00000001 << CONTROL_STOP_ACQ_OFST)
#define CONTROL_CORE_RST_OFST (10)
#define CONTROL_CORE_RST_MSK (0x00000001 << CONTROL_CORE_RST_OFST)
#define CONTROL_PERIPHERAL_RST_OFST (11) //DDR3 HMem Ctrlr, GBE, Temp
#define CONTROL_PERIPHERAL_RST_MSK (0x00000001 << CONTROL_PERIPHERAL_RST_OFST) //DDR3 HMem Ctrlr, GBE, Temp
#define CONTROL_DDR3_MEM_RST_OFST (12) //only PHY, not DDR3 PLL ,Not used in software
#define CONTROL_DDR3_MEM_RST_MSK (0x00000001 << CONTROL_DDR3_MEM_RST_OFST) //only PHY, not DDR3 PLL ,Not used in software
#define CONTROL_PERIPHERAL_RST_OFST (11) // DDR3 HMem Ctrlr, GBE, Temp
#define CONTROL_PERIPHERAL_RST_MSK \
(0x00000001 << CONTROL_PERIPHERAL_RST_OFST) // DDR3 HMem Ctrlr, GBE, Temp
#define CONTROL_DDR3_MEM_RST_OFST \
(12) // only PHY, not DDR3 PLL ,Not used in software
#define CONTROL_DDR3_MEM_RST_MSK \
(0x00000001 << CONTROL_DDR3_MEM_RST_OFST) // only PHY, not DDR3 PLL ,Not
// used in software
#define CONTROL_ACQ_FIFO_CLR_OFST (14)
#define CONTROL_ACQ_FIFO_CLR_MSK (0x00000001 << CONTROL_ACQ_FIFO_CLR_OFST)
#define CONTROL_STORAGE_CELL_NUM_OFST (16)
#define CONTROL_STORAGE_CELL_NUM_MSK (0x0000000F << CONTROL_STORAGE_CELL_NUM_OFST)
#define CONTROL_STORAGE_CELL_NUM_MSK \
(0x0000000F << CONTROL_STORAGE_CELL_NUM_OFST)
#define CONTROL_RX_ADDTNL_ENDPTS_NUM_OFST (20)
#define CONTROL_RX_ADDTNL_ENDPTS_NUM_MSK (0x0000003F << CONTROL_RX_ADDTNL_ENDPTS_NUM_OFST)
#define CONTROL_RX_ADDTNL_ENDPTS_NUM_MSK \
(0x0000003F << CONTROL_RX_ADDTNL_ENDPTS_NUM_OFST)
#define CONTROL_RX_ENDPTS_START_OFST (26)
#define CONTROL_RX_ENDPTS_START_MSK (0x0000003F << CONTROL_RX_ENDPTS_START_OFST)
/* Reconfiguratble PLL Paramater Register */
#define PLL_PARAM_REG (0x50 << MEM_MAP_SHIFT)
/* Reconfiguratble PLL Control Regiser */
#define PLL_CNTRL_REG (0x51 << MEM_MAP_SHIFT)
#define PLL_CNTRL_RCNFG_PRMTR_RST_OFST (0) //parameter reset
#define PLL_CNTRL_RCNFG_PRMTR_RST_MSK (0x00000001 << PLL_CNTRL_RCNFG_PRMTR_RST_OFST) //parameter reset
#define PLL_CNTRL_RCNFG_PRMTR_RST_OFST (0) // parameter reset
#define PLL_CNTRL_RCNFG_PRMTR_RST_MSK \
(0x00000001 << PLL_CNTRL_RCNFG_PRMTR_RST_OFST) // parameter reset
#define PLL_CNTRL_WR_PRMTR_OFST (2)
#define PLL_CNTRL_WR_PRMTR_MSK (0x00000001 << PLL_CNTRL_WR_PRMTR_OFST)
#define PLL_CNTRL_PLL_RST_OFST (3)
@@ -229,50 +245,86 @@
#define SAMPLE_ADC_SAMPLE_SEL_OFST (0)
#define SAMPLE_ADC_SAMPLE_SEL_MSK (0x00000007 << SAMPLE_ADC_SAMPLE_SEL_OFST)
#define SAMPLE_ADC_SAMPLE_0_VAL ((0x0 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
#define SAMPLE_ADC_SAMPLE_1_VAL ((0x1 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
#define SAMPLE_ADC_SAMPLE_2_VAL ((0x2 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
#define SAMPLE_ADC_SAMPLE_3_VAL ((0x3 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
#define SAMPLE_ADC_SAMPLE_4_VAL ((0x4 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
#define SAMPLE_ADC_SAMPLE_5_VAL ((0x5 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
#define SAMPLE_ADC_SAMPLE_6_VAL ((0x6 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
#define SAMPLE_ADC_SAMPLE_7_VAL ((0x7 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
#define SAMPLE_ADC_SAMPLE_0_VAL \
((0x0 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
#define SAMPLE_ADC_SAMPLE_1_VAL \
((0x1 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
#define SAMPLE_ADC_SAMPLE_2_VAL \
((0x2 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
#define SAMPLE_ADC_SAMPLE_3_VAL \
((0x3 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
#define SAMPLE_ADC_SAMPLE_4_VAL \
((0x4 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
#define SAMPLE_ADC_SAMPLE_5_VAL \
((0x5 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
#define SAMPLE_ADC_SAMPLE_6_VAL \
((0x6 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
#define SAMPLE_ADC_SAMPLE_7_VAL \
((0x7 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
// Decimation = ADF + 1
#define SAMPLE_ADC_DECMT_FACTOR_OFST (4)
#define SAMPLE_ADC_DECMT_FACTOR_MSK (0x00000007 << SAMPLE_ADC_DECMT_FACTOR_OFST)
#define SAMPLE_ADC_DECMT_FACTOR_0_VAL ((0x0 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
#define SAMPLE_ADC_DECMT_FACTOR_1_VAL ((0x1 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
#define SAMPLE_ADC_DECMT_FACTOR_2_VAL ((0x2 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
#define SAMPLE_ADC_DECMT_FACTOR_3_VAL ((0x3 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
#define SAMPLE_ADC_DECMT_FACTOR_4_VAL ((0x4 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
#define SAMPLE_ADC_DECMT_FACTOR_5_VAL ((0x5 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
#define SAMPLE_ADC_DECMT_FACTOR_6_VAL ((0x6 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
#define SAMPLE_ADC_DECMT_FACTOR_7_VAL ((0x7 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
#define SAMPLE_ADC_DECMT_FACTOR_0_VAL \
((0x0 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
#define SAMPLE_ADC_DECMT_FACTOR_1_VAL \
((0x1 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
#define SAMPLE_ADC_DECMT_FACTOR_2_VAL \
((0x2 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
#define SAMPLE_ADC_DECMT_FACTOR_3_VAL \
((0x3 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
#define SAMPLE_ADC_DECMT_FACTOR_4_VAL \
((0x4 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
#define SAMPLE_ADC_DECMT_FACTOR_5_VAL \
((0x5 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
#define SAMPLE_ADC_DECMT_FACTOR_6_VAL \
((0x6 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
#define SAMPLE_ADC_DECMT_FACTOR_7_VAL \
((0x7 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
#define SAMPLE_DGTL_SAMPLE_SEL_OFST (8)
#define SAMPLE_DGTL_SAMPLE_SEL_MSK (0x0000000F << SAMPLE_DGTL_SAMPLE_SEL_OFST)
#define SAMPLE_DGTL_SAMPLE_0_VAL ((0x0 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_1_VAL ((0x1 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_2_VAL ((0x2 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_3_VAL ((0x3 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_4_VAL ((0x4 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_5_VAL ((0x5 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_6_VAL ((0x6 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_7_VAL ((0x7 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_8_VAL ((0x8 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_9_VAL ((0x9 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_10_VAL ((0xa << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_11_VAL ((0xb << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_12_VAL ((0xc << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_13_VAL ((0xd << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_14_VAL ((0xe << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_15_VAL ((0xf << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_0_VAL \
((0x0 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_1_VAL \
((0x1 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_2_VAL \
((0x2 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_3_VAL \
((0x3 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_4_VAL \
((0x4 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_5_VAL \
((0x5 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_6_VAL \
((0x6 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_7_VAL \
((0x7 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_8_VAL \
((0x8 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_9_VAL \
((0x9 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_10_VAL \
((0xa << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_11_VAL \
((0xb << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_12_VAL \
((0xc << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_13_VAL \
((0xd << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_14_VAL \
((0xe << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_15_VAL \
((0xf << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_DECMT_FACTOR_OFST (12)
#define SAMPLE_DGTL_DECMT_FACTOR_MSK (0x00000003 << SAMPLE_DGTL_DECMT_FACTOR_OFST)
#define SAMPLE_DECMT_FACTOR_FULL_VAL ((0x0 << SAMPLE_DGTL_DECMT_FACTOR_OFST) & SAMPLE_DGTL_DECMT_FACTOR_MSK)
#define SAMPLE_DECMT_FACTOR_HALF_VAL ((0x1 << SAMPLE_DGTL_DECMT_FACTOR_OFST) & SAMPLE_DGTL_DECMT_FACTOR_MSK)
#define SAMPLE_DECMT_FACTOR_QUARTER_VAL ((0x2 << SAMPLE_DGTL_DECMT_FACTOR_OFST) & SAMPLE_DGTL_DECMT_FACTOR_MSK)
#define SAMPLE_DGTL_DECMT_FACTOR_MSK \
(0x00000003 << SAMPLE_DGTL_DECMT_FACTOR_OFST)
#define SAMPLE_DECMT_FACTOR_FULL_VAL \
((0x0 << SAMPLE_DGTL_DECMT_FACTOR_OFST) & SAMPLE_DGTL_DECMT_FACTOR_MSK)
#define SAMPLE_DECMT_FACTOR_HALF_VAL \
((0x1 << SAMPLE_DGTL_DECMT_FACTOR_OFST) & SAMPLE_DGTL_DECMT_FACTOR_MSK)
#define SAMPLE_DECMT_FACTOR_QUARTER_VAL \
((0x2 << SAMPLE_DGTL_DECMT_FACTOR_OFST) & SAMPLE_DGTL_DECMT_FACTOR_MSK)
/** Vref Comp Mod Register */
#define EXT_DAQ_CTRL_REG (0x5C << MEM_MAP_SHIFT)
@@ -280,21 +332,25 @@
#define EXT_DAQ_CTRL_VREF_COMP_OFST (0)
#define EXT_DAQ_CTRL_VREF_COMP_MSK (0x00000FFF << EXT_DAQ_CTRL_VREF_COMP_OFST)
#define EXT_DAQ_CTRL_CMP_LGC_ENBL_OFST (15)
#define EXT_DAQ_CTRL_CMP_LGC_ENBL_MSK (0x00000001 << EXT_DAQ_CTRL_CMP_LGC_ENBL_OFST)
#define EXT_DAQ_CTRL_CMP_LGC_ENBL_MSK \
(0x00000001 << EXT_DAQ_CTRL_CMP_LGC_ENBL_OFST)
#define EXT_DAQ_CTRL_INPT_DETECT_OFST (16)
#define EXT_DAQ_CTRL_INPT_DETECT_MSK (0x00000007 << EXT_DAQ_CTRL_INPT_DETECT_OFST)
#define EXT_DAQ_CTRL_INPT_DETECT_MSK \
(0x00000007 << EXT_DAQ_CTRL_INPT_DETECT_OFST)
#define EXT_DAQ_CTRL_INPT_DETECT_ENBL_OFST (19)
#define EXT_DAQ_CTRL_INPT_DETECT_ENBL_MSK (0x00000001 << EXT_DAQ_CTRL_INPT_DETECT_ENBL_OFST)
#define EXT_DAQ_CTRL_INPT_DETECT_ENBL_MSK \
(0x00000001 << EXT_DAQ_CTRL_INPT_DETECT_ENBL_OFST)
/** DAQ Register */
#define DAQ_REG (0x5D << MEM_MAP_SHIFT)
#define DAQ_SETTINGS_MSK (DAQ_HIGH_GAIN_MSK | DAQ_FIX_GAIN_MSK | DAQ_FRCE_SWTCH_GAIN_MSK)
#define DAQ_SETTINGS_MSK \
(DAQ_HIGH_GAIN_MSK | DAQ_FIX_GAIN_MSK | DAQ_FRCE_SWTCH_GAIN_MSK)
#define DAQ_HIGH_GAIN_OFST (0)
#define DAQ_HIGH_GAIN_MSK (0x00000001 << DAQ_HIGH_GAIN_OFST)
#define DAQ_FIX_GAIN_DYNMC_VAL ((0x0 << DAQ_HIGH_GAIN_OFST) & DAQ_HIGH_GAIN_MSK)
#define DAQ_FIX_GAIN_HIGHGAIN_VAL ((0x1 << DAQ_HIGH_GAIN_OFST) & DAQ_HIGH_GAIN_MSK)
#define DAQ_FIX_GAIN_HIGHGAIN_VAL \
((0x1 << DAQ_HIGH_GAIN_OFST) & DAQ_HIGH_GAIN_MSK)
#define DAQ_FIX_GAIN_OFST (1)
#define DAQ_FIX_GAIN_MSK (0x00000003 << DAQ_FIX_GAIN_OFST)
#define DAQ_FIX_GAIN_STG_1_VAL ((0x1 << DAQ_FIX_GAIN_OFST) & DAQ_FIX_GAIN_MSK)
@@ -305,8 +361,10 @@
#define DAQ_STRG_CELL_SLCT_MSK (0x0000000F << DAQ_STRG_CELL_SLCT_OFST)
#define DAQ_FRCE_SWTCH_GAIN_OFST (12)
#define DAQ_FRCE_SWTCH_GAIN_MSK (0x00000003 << DAQ_FRCE_SWTCH_GAIN_OFST)
#define DAQ_FRCE_GAIN_STG_1_VAL ((0x1 << DAQ_FRCE_SWTCH_GAIN_OFST) & DAQ_FRCE_SWTCH_GAIN_MSK)
#define DAQ_FRCE_GAIN_STG_2_VAL ((0x3 << DAQ_FRCE_SWTCH_GAIN_OFST) & DAQ_FRCE_SWTCH_GAIN_MSK)
#define DAQ_FRCE_GAIN_STG_1_VAL \
((0x1 << DAQ_FRCE_SWTCH_GAIN_OFST) & DAQ_FRCE_SWTCH_GAIN_MSK)
#define DAQ_FRCE_GAIN_STG_2_VAL \
((0x3 << DAQ_FRCE_SWTCH_GAIN_OFST) & DAQ_FRCE_SWTCH_GAIN_MSK)
#define DAQ_ELCTRN_CLLCTN_MDE_OFST (14)
#define DAQ_ELCTRN_CLLCTN_MDE_MSK (0x00000001 << DAQ_ELCTRN_CLLCTN_MDE_OFST)
#define DAQ_G2_CNNT_OFST (15)
@@ -326,19 +384,18 @@
#define CHIP_POWER_STATUS_OFST (1)
#define CHIP_POWER_STATUS_MSK (0x00000001 << CHIP_POWER_STATUS_OFST)
/** Temperature Control Register */
#define TEMP_CTRL_REG (0x5F << MEM_MAP_SHIFT)
#define TEMP_CTRL_PROTCT_THRSHLD_OFST (0)
#define TEMP_CTRL_PROTCT_THRSHLD_MSK (0x000007FF << TEMP_CTRL_PROTCT_THRSHLD_OFST)
#define TEMP_CTRL_PROTCT_THRSHLD_MSK \
(0x000007FF << TEMP_CTRL_PROTCT_THRSHLD_OFST)
#define TEMP_CTRL_PROTCT_ENABLE_OFST (16)
#define TEMP_CTRL_PROTCT_ENABLE_MSK (0x00000001 << TEMP_CTRL_PROTCT_ENABLE_OFST)
// set when temp higher than over threshold, write 1 to clear it
#define TEMP_CTRL_OVR_TMP_EVNT_OFST (31)
#define TEMP_CTRL_OVR_TMP_EVNT_MSK (0x00000001 << TEMP_CTRL_OVR_TMP_EVNT_OFST)
/* Set Delay 64 bit register */
#define SET_DELAY_LSB_REG (0x60 << MEM_MAP_SHIFT) // different kind of delay
#define SET_DELAY_MSB_REG (0x61 << MEM_MAP_SHIFT) // different kind of delay
@@ -383,7 +440,6 @@
#define COORD_COL_INNER_OFST (16)
#define COORD_COL_INNER_MSK (0x0000FFFF << COORD_COL_INNER_OFST)
/** Module column coordinates */
#define COORD_RESERVED_REG (0x7E << MEM_MAP_SHIFT)
@@ -397,39 +453,42 @@
// tPC = (PCT + 1) * 25ns
#define ASIC_CTRL_PRCHRG_TMR_OFST (0)
#define ASIC_CTRL_PRCHRG_TMR_MSK (0x000000FF << ASIC_CTRL_PRCHRG_TMR_OFST)
#define ASIC_CTRL_PRCHRG_TMR_VAL ((0x1F << ASIC_CTRL_PRCHRG_TMR_OFST) & ASIC_CTRL_PRCHRG_TMR_MSK)
#define ASIC_CTRL_PRCHRG_TMR_VAL \
((0x1F << ASIC_CTRL_PRCHRG_TMR_OFST) & ASIC_CTRL_PRCHRG_TMR_MSK)
// tDS = (DST + 1) * 25ns
#define ASIC_CTRL_DS_TMR_OFST (8)
#define ASIC_CTRL_DS_TMR_MSK (0x000000FF << ASIC_CTRL_DS_TMR_OFST)
#define ASIC_CTRL_DS_TMR_VAL ((0x1F << ASIC_CTRL_DS_TMR_OFST) & ASIC_CTRL_DS_TMR_MSK)
// tET = (ET + 1) * 25ns (increase timeout range between 2 consecutive storage cells)
#define ASIC_CTRL_DS_TMR_VAL \
((0x1F << ASIC_CTRL_DS_TMR_OFST) & ASIC_CTRL_DS_TMR_MSK)
// tET = (ET + 1) * 25ns (increase timeout range between 2 consecutive storage
// cells)
#define ASIC_CTRL_EXPSRE_TMR_OFST (16)
#define ASIC_CTRL_EXPSRE_TMR_MSK (0x0000FFFF << ASIC_CTRL_EXPSRE_TMR_OFST)
#define ASIC_CTRL_EXPSRE_TMR_MAX_VAL (0x0000FFFF / (CLK_RUN * 1E-3))
/* ADC 0 Deserializer Control */
#define ADC_DSRLZR_0_REG (0xF0 << MEM_MAP_SHIFT)
#define ADC_DSRLZR_0_RFRSH_ALGNMNT_OFST (31) /* Refresh alignment */
#define ADC_DSRLZR_0_RFRSH_ALGNMNT_MSK (0x00000001 << ADC_DSRLZR_0_RFRSH_ALGNMNT_OFST)
#define ADC_DSRLZR_0_RFRSH_ALGNMNT_MSK \
(0x00000001 << ADC_DSRLZR_0_RFRSH_ALGNMNT_OFST)
/* ADC 0 Deserializer Control */
#define ADC_DSRLZR_1_REG (0xF1 << MEM_MAP_SHIFT)
#define ADC_DSRLZR_1_RFRSH_ALGNMNT_OFST (31)
#define ADC_DSRLZR_1_RFRSH_ALGNMNT_MSK (0x00000001 << ADC_DSRLZR_1_RFRSH_ALGNMNT_OFST)
#define ADC_DSRLZR_1_RFRSH_ALGNMNT_MSK \
(0x00000001 << ADC_DSRLZR_1_RFRSH_ALGNMNT_OFST)
/* ADC 0 Deserializer Control */
#define ADC_DSRLZR_2_REG (0xF2 << MEM_MAP_SHIFT)
#define ADC_DSRLZR_2_RFRSH_ALGNMNT_OFST (31)
#define ADC_DSRLZR_2_RFRSH_ALGNMNT_MSK (0x00000001 << ADC_DSRLZR_2_RFRSH_ALGNMNT_OFST)
#define ADC_DSRLZR_2_RFRSH_ALGNMNT_MSK \
(0x00000001 << ADC_DSRLZR_2_RFRSH_ALGNMNT_OFST)
/* ADC 0 Deserializer Control */
#define ADC_DSRLZR_3_REG (0xF3 << MEM_MAP_SHIFT)
#define ADC_DSRLZR_3_RFRSH_ALGNMNT_OFST (31)
#define ADC_DSRLZR_3_RFRSH_ALGNMNT_MSK (0x00000001 << ADC_DSRLZR_3_RFRSH_ALGNMNT_OFST)
#define ADC_DSRLZR_3_RFRSH_ALGNMNT_MSK \
(0x00000001 << ADC_DSRLZR_3_RFRSH_ALGNMNT_OFST)
/* Round Robin */
#define RXR_ENDPOINTS_MAX (64)
@@ -437,8 +496,3 @@
#define RXR_ENDPOINT_INNER_START_REG (0x2000 << MEM_MAP_SHIFT)
#define RXR_ENDPOINT_OFST (0x10 << MEM_MAP_SHIFT)

877
slsDetectorServers/jungfrauDetectorServer/slsDetectorFunctionList.c Executable file → Normal file
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File diff suppressed because it is too large Load Diff

66
slsDetectorServers/jungfrauDetectorServer/slsDetectorServer_defs.h Executable file → Normal file
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@@ -1,7 +1,6 @@
#pragma once
#include "sls_detector_defs.h"
#include "RegisterDefs.h"
#include "sls_detector_defs.h"
#define MIN_REQRD_VRSN_T_RD_API 0x171220
#define REQRD_FRMWRE_VRSN_BOARD2 0x190716 // old
@@ -16,13 +15,13 @@ typedef struct udp_header_struct {
uint16_t udp_destmac_lsb;
uint32_t udp_srcmac_lsb;
uint8_t ip_tos;
uint8_t ip_ihl: 4, ip_ver: 4;
uint8_t ip_ihl : 4, ip_ver : 4;
uint16_t udp_ethertype;
uint16_t ip_identification;
uint16_t ip_totallength;
uint8_t ip_protocol;
uint8_t ip_ttl;
uint16_t ip_fragmentoffset: 13, ip_flags: 3;
uint16_t ip_fragmentoffset : 13, ip_flags : 3;
uint16_t ip_srcip_msb;
uint16_t ip_checksum;
uint16_t ip_destip_msb;
@@ -36,11 +35,21 @@ typedef struct udp_header_struct {
#define IP_HEADER_SIZE (20)
#define UDP_IP_HEADER_LENGTH_BYTES (28)
/* Enums */
enum ADCINDEX {TEMP_FPGA, TEMP_ADC};
enum DACINDEX {J_VB_COMP, J_VDD_PROT, J_VIN_COM, J_VREF_PRECH, J_VB_PIXBUF, J_VB_DS, J_VREF_DS, J_VREF_COMP };
#define DEFAULT_DAC_VALS { 1220, /* J_VB_COMP */ \
enum ADCINDEX { TEMP_FPGA, TEMP_ADC };
enum DACINDEX {
J_VB_COMP,
J_VDD_PROT,
J_VIN_COM,
J_VREF_PRECH,
J_VB_PIXBUF,
J_VB_DS,
J_VREF_DS,
J_VREF_COMP
};
#define DEFAULT_DAC_VALS \
{ \
1220, /* J_VB_COMP */ \
3000, /* J_VDD_PROT */ \
1053, /* J_VIN_COM */ \
1450, /* J_VREF_PRECH */ \
@@ -50,7 +59,7 @@ enum DACINDEX {J_VB_COMP, J_VDD_PROT, J_VIN_COM, J_VREF_PRECH, J_VB_PIXBUF, J
420 /* J_VREF_COMP */ \
};
enum NETWORKINDEX { TXN_FRAME, FLOWCTRL_10G };
enum CLKINDEX {RUN_CLK, ADC_CLK, DBIT_CLK, NUM_CLOCKS};
enum CLKINDEX { RUN_CLK, ADC_CLK, DBIT_CLK, NUM_CLOCKS };
#define CLK_NAMES "run", "adc", "dbit"
/* Hardware Definitions */
@@ -67,17 +76,17 @@ enum CLKINDEX {RUN_CLK, ADC_CLK, DBIT_CLK, NUM_CLOCKS};
#define DBIT_CLK_INDEX (0)
/** Default Parameters */
#define DEFAULT_NUM_FRAMES (100*1000*1000)
#define DEFAULT_NUM_FRAMES (100 * 1000 * 1000)
#define DEFAULT_STARTING_FRAME_NUMBER (1)
#define DEFAULT_NUM_CYCLES (1)
#define DEFAULT_EXPTIME (10*1000) //ns
#define DEFAULT_PERIOD (2*1000*1000) //ns
#define DEFAULT_EXPTIME (10 * 1000) // ns
#define DEFAULT_PERIOD (2 * 1000 * 1000) // ns
#define DEFAULT_DELAY (0)
#define DEFAULT_HIGH_VOLTAGE (0)
#define DEFAULT_TIMING_MODE (AUTO_TIMING)
#define DEFAULT_SETTINGS (DYNAMICGAIN)
#define DEFAULT_TX_UDP_PORT (0x7e9a)
#define DEFAULT_TMP_THRSHLD (65*1000) //milli degree Celsius
#define DEFAULT_TMP_THRSHLD (65 * 1000) // milli degree Celsius
#define DEFAULT_NUM_STRG_CLLS (0)
#define DEFAULT_STRG_CLL_STRT (0xf)
#define DEFAULT_STRG_CLL_DLY (0)
@@ -89,16 +98,14 @@ enum CLKINDEX {RUN_CLK, ADC_CLK, DBIT_CLK, NUM_CLOCKS};
/* Defines in the Firmware */
#define MAX_TIMESLOT_VAL (0x1F)
#define MAX_THRESHOLD_TEMP_VAL (127999) //millidegrees
#define MAX_STORAGE_CELL_VAL (15) //0xF
#define MAX_THRESHOLD_TEMP_VAL (127999) // millidegrees
#define MAX_STORAGE_CELL_VAL (15) // 0xF
#define MAX_STORAGE_CELL_DLY_NS_VAL (ASIC_CTRL_EXPSRE_TMR_MAX_VAL)
#define ACQ_TIME_MIN_CLOCK (2)
#define MAX_PHASE_SHIFTS (160)
#define BIT16_MASK (0xFFFF)
#define ADC_OFST_FULL_SPEED_VAL (0xf)
#define ADC_OFST_HALF_SPEED_VAL (0xb)
#define ADC_OFST_QUARTER_SPEED_VAL (0x7)
@@ -108,18 +115,27 @@ enum CLKINDEX {RUN_CLK, ADC_CLK, DBIT_CLK, NUM_CLOCKS};
#define ADC_PORT_INVERT_VAL (0x5A5A5A5A)
#define ADC_PORT_INVERT_BOARD2_VAL (0x453b2a9c)
#define SAMPLE_ADC_FULL_SPEED (SAMPLE_ADC_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_0_VAL + SAMPLE_DGTL_SAMPLE_2_VAL + SAMPLE_DECMT_FACTOR_FULL_VAL) // 0x200
#define SAMPLE_ADC_HALF_SPEED (SAMPLE_ADC_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_1_VAL + SAMPLE_DGTL_SAMPLE_3_VAL + SAMPLE_DECMT_FACTOR_HALF_VAL) // 0x1310
#define SAMPLE_ADC_QUARTER_SPEED (SAMPLE_ADC_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_3_VAL + SAMPLE_DGTL_SAMPLE_6_VAL + SAMPLE_DECMT_FACTOR_QUARTER_VAL) // 0x2630
#define SAMPLE_ADC_HALF_SPEED_BOARD2 (SAMPLE_ADC_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_0_VAL + SAMPLE_DGTL_SAMPLE_6_VAL + SAMPLE_DECMT_FACTOR_HALF_VAL) // 0x1600
#define SAMPLE_ADC_QUARTER_SPEED_BOARD2 (SAMPLE_ADC_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_1_VAL + SAMPLE_DGTL_SAMPLE_11_VAL + SAMPLE_DECMT_FACTOR_QUARTER_VAL) // 0x2b10
#define SAMPLE_ADC_FULL_SPEED \
(SAMPLE_ADC_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_0_VAL + \
SAMPLE_DGTL_SAMPLE_2_VAL + SAMPLE_DECMT_FACTOR_FULL_VAL) // 0x200
#define SAMPLE_ADC_HALF_SPEED \
(SAMPLE_ADC_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_1_VAL + \
SAMPLE_DGTL_SAMPLE_3_VAL + SAMPLE_DECMT_FACTOR_HALF_VAL) // 0x1310
#define SAMPLE_ADC_QUARTER_SPEED \
(SAMPLE_ADC_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_3_VAL + \
SAMPLE_DGTL_SAMPLE_6_VAL + SAMPLE_DECMT_FACTOR_QUARTER_VAL) // 0x2630
#define SAMPLE_ADC_HALF_SPEED_BOARD2 \
(SAMPLE_ADC_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_0_VAL + \
SAMPLE_DGTL_SAMPLE_6_VAL + SAMPLE_DECMT_FACTOR_HALF_VAL) // 0x1600
#define SAMPLE_ADC_QUARTER_SPEED_BOARD2 \
(SAMPLE_ADC_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_1_VAL + \
SAMPLE_DGTL_SAMPLE_11_VAL + SAMPLE_DECMT_FACTOR_QUARTER_VAL) // 0x2b10
#define ADC_PHASE_FULL_SPEED (28)
#define ADC_PHASE_HALF_SPEED (35)
#define ADC_PHASE_QUARTER_SPEED (35)
#define ADC_PHASE_HALF_SPEED_BOARD2 (0x1E) //30
#define ADC_PHASE_QUARTER_SPEED_BOARD2 (0x1E) //30
#define ADC_PHASE_HALF_SPEED_BOARD2 (0x1E) // 30
#define ADC_PHASE_QUARTER_SPEED_BOARD2 (0x1E) // 30
#define DBIT_PHASE_FULL_SPEED (37)
#define DBIT_PHASE_HALF_SPEED (37)

136
slsDetectorServers/moenchDetectorServer/RegisterDefs.h Executable file → Normal file
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@@ -3,7 +3,6 @@
/* Definitions for FPGA */
#define MEM_MAP_SHIFT 1
/* FPGA Version RO register */
#define FPGA_VERSION_REG (0x00 << MEM_MAP_SHIFT)
@@ -11,7 +10,8 @@
#define FPGA_VERSION_BRD_RVSN_MSK (0x00FFFFFF << FPGA_VERSION_BRD_RVSN_OFST)
#define FPGA_VERSION_DTCTR_TYP_OFST (24)
#define FPGA_VERSION_DTCTR_TYP_MSK (0x000000FF << FPGA_VERSION_DTCTR_TYP_OFST)
#define FPGA_VERSION_DTCTR_TYP_MOENCH_VAL ((0x5 << FPGA_VERSION_DTCTR_TYP_OFST) & FPGA_VERSION_DTCTR_TYP_MSK)
#define FPGA_VERSION_DTCTR_TYP_MOENCH_VAL \
((0x5 << FPGA_VERSION_DTCTR_TYP_OFST) & FPGA_VERSION_DTCTR_TYP_MSK)
/* Fix pattern RO register */
#define FIX_PATT_REG (0x01 << MEM_MAP_SHIFT)
@@ -58,7 +58,8 @@
#define STATUS_PLL_PHS_DN_OFST (23)
#define STATUS_PLL_PHS_DN_MSK (0x00000001 << STATUS_PLL_PHS_DN_OFST)
#define STATUS_PT_CNTRL_STTS_OFF_OFST (24)
#define STATUS_PT_CNTRL_STTS_OFF_MSK (0x000000FF << STATUS_PT_CNTRL_STTS_OFF_OFST)
#define STATUS_PT_CNTRL_STTS_OFF_MSK \
(0x000000FF << STATUS_PT_CNTRL_STTS_OFF_OFST)
#define STATUS_IDLE_MSK (0x677FF)
/* Look at me RO register TODO */
@@ -68,24 +69,30 @@
#define SYSTEM_STATUS_REG (0x04 << MEM_MAP_SHIFT)
#define SYSTEM_STATUS_DDR3_CLBRTN_OK_OFST (0)
#define SYSTEM_STATUS_DDR3_CLBRTN_OK_MSK (0x00000001 << SYSTEM_STATUS_DDR3_CLBRTN_OK_OFST)
#define SYSTEM_STATUS_DDR3_CLBRTN_OK_MSK \
(0x00000001 << SYSTEM_STATUS_DDR3_CLBRTN_OK_OFST)
#define SYSTEM_STATUS_DDR3_CLBRTN_FL_OFST (1)
#define SYSTEM_STATUS_DDR3_CLBRTN_FL_MSK (0x00000001 << SYSTEM_STATUS_DDR3_CLBRTN_FL_OFST)
#define SYSTEM_STATUS_DDR3_CLBRTN_FL_MSK \
(0x00000001 << SYSTEM_STATUS_DDR3_CLBRTN_FL_OFST)
#define SYSTEM_STATUS_DDR3_INT_DN_OFST (2)
#define SYSTEM_STATUS_DDR3_INT_DN_MSK (0x00000001 << SYSTEM_STATUS_DDR3_INT_DN_OFST)
#define SYSTEM_STATUS_DDR3_INT_DN_MSK \
(0x00000001 << SYSTEM_STATUS_DDR3_INT_DN_OFST)
#define SYSTEM_STATUS_RCNFG_PLL_LCK_OFST (3)
#define SYSTEM_STATUS_RCNFG_PLL_LCK_MSK (0x00000001 << SYSTEM_STATUS_RCNFG_PLL_LCK_OFST)
#define SYSTEM_STATUS_RCNFG_PLL_LCK_MSK \
(0x00000001 << SYSTEM_STATUS_RCNFG_PLL_LCK_OFST)
#define SYSTEM_STATUS_PLL_A_LCK_OFST (4)
#define SYSTEM_STATUS_PLL_A_LCK_MSK (0x00000001 << SYSTEM_STATUS_PLL_A_LCK_OFST)
/* PLL Param (Reconfiguratble PLL Parameter) RO register TODO FIXME: Same as PLL_PARAM_REG 0x50 */
/* PLL Param (Reconfiguratble PLL Parameter) RO register TODO FIXME: Same as
* PLL_PARAM_REG 0x50 */
//#define PLL_PARAM_REG (0x05 << MEM_MAP_SHIFT)
/* FIFO Data RO register TODO */
#define FIFO_DATA_REG (0x06 << MEM_MAP_SHIFT)
#define FIFO_DATA_HRDWR_SRL_NMBR_OFST (0)
#define FIFO_DATA_HRDWR_SRL_NMBR_MSK (0x0000FFFF << FIFO_DATA_HRDWR_SRL_NMBR_OFST)
#define FIFO_DATA_HRDWR_SRL_NMBR_MSK \
(0x0000FFFF << FIFO_DATA_HRDWR_SRL_NMBR_OFST)
//#define FIFO_DATA_WRD_OFST (16)
//#define FIFO_DATA_WRD_MSK (0x0000FFFF << FIFO_DATA_WRD_OFST)
@@ -115,7 +122,8 @@
#define API_VERSION_DTCTR_TYP_OFST (24)
#define API_VERSION_DTCTR_TYP_MSK (0x000000FF << API_VERSION_DTCTR_TYP_OFST)
/* Time from Start 64 bit RO register. t = GCLK x 50 ns. Reset using CONTROL_CRST. TODO */
/* Time from Start 64 bit RO register. t = GCLK x 50 ns. Reset using
* CONTROL_CRST. TODO */
#define TIME_FROM_START_LSB_REG (0x10 << MEM_MAP_SHIFT)
#define TIME_FROM_START_MSB_REG (0x11 << MEM_MAP_SHIFT)
@@ -136,12 +144,16 @@
#define PERIOD_LEFT_MSB_REG (0x19 << MEM_MAP_SHIFT)
/* Exposure Time Left 64 bit RO register */
//#define EXPTIME_LEFT_LSB_REG (0x1A << MEM_MAP_SHIFT) // Not used in FW
//#define EXPTIME_LEFT_MSB_REG (0x1B << MEM_MAP_SHIFT) // Not used in FW
//#define EXPTIME_LEFT_LSB_REG (0x1A << MEM_MAP_SHIFT) // Not
// used in FW #define EXPTIME_LEFT_MSB_REG (0x1B <<
// MEM_MAP_SHIFT)
//// Not used in FW
/* Gates Left 64 bit RO register */
//#define GATES_LEFT_LSB_REG (0x1C << MEM_MAP_SHIFT) // Not used in FW
//#define GATES_LEFT_MSB_REG (0x1D << MEM_MAP_SHIFT) // Not used in FW
//#define GATES_LEFT_LSB_REG (0x1C << MEM_MAP_SHIFT) // Not
// used in FW #define GATES_LEFT_MSB_REG (0x1D <<
// MEM_MAP_SHIFT)
//// Not used in FW
/* Data In 64 bit RO register TODO */
#define DATA_IN_LSB_REG (0x1E << MEM_MAP_SHIFT)
@@ -152,14 +164,17 @@
#define PATTERN_OUT_MSB_REG (0x21 << MEM_MAP_SHIFT)
/* Frames From Start 64 bit RO register TODO */
//#define FRAMES_FROM_START_LSB_REG (0x22 << MEM_MAP_SHIFT) // Not used in FW
//#define FRAMES_FROM_START_MSB_REG (0x23 << MEM_MAP_SHIFT) // Not used in FW
//#define FRAMES_FROM_START_LSB_REG (0x22 << MEM_MAP_SHIFT) // Not
// used in FW #define FRAMES_FROM_START_MSB_REG (0x23 <<
// MEM_MAP_SHIFT)
//// Not used in FW
/* Frames From Start PG 64 bit RO register. Reset using CONTROL_CRST. TODO */
#define FRAMES_FROM_START_PG_LSB_REG (0x24 << MEM_MAP_SHIFT)
#define FRAMES_FROM_START_PG_MSB_REG (0x25 << MEM_MAP_SHIFT)
/* Start Frame Time (Measurement Time) 64 bit register (timestamp at a frame start until reset) TODO */
/* Start Frame Time (Measurement Time) 64 bit register (timestamp at a frame
* start until reset) TODO */
#define START_FRAME_TIME_LSB_REG (0x26 << MEM_MAP_SHIFT)
#define START_FRAME_TIME_MSB_REG (0x27 << MEM_MAP_SHIFT)
@@ -178,9 +193,11 @@
/* FIFO Digital In Status RO register */
#define FIFO_DIN_STATUS_REG (0x3B << MEM_MAP_SHIFT)
#define FIFO_DIN_STATUS_FIFO_FULL_OFST (30)
#define FIFO_DIN_STATUS_FIFO_FULL_MSK (0x00000001 << FIFO_DIN_STATUS_FIFO_FULL_OFST)
#define FIFO_DIN_STATUS_FIFO_FULL_MSK \
(0x00000001 << FIFO_DIN_STATUS_FIFO_FULL_OFST)
#define FIFO_DIN_STATUS_FIFO_EMPTY_OFST (31)
#define FIFO_DIN_STATUS_FIFO_EMPTY_MSK (0x00000001 << FIFO_DIN_STATUS_FIFO_EMPTY_OFST)
#define FIFO_DIN_STATUS_FIFO_EMPTY_MSK \
(0x00000001 << FIFO_DIN_STATUS_FIFO_EMPTY_OFST)
/* FIFO Digital In 64 bit RO register */
#define FIFO_DIN_LSB_REG (0x3C << MEM_MAP_SHIFT)
@@ -244,9 +261,11 @@
#define DUMMY_FIFO_CHNNL_SLCT_OFST (0)
#define DUMMY_FIFO_CHNNL_SLCT_MSK (0x0000003F << DUMMY_FIFO_CHNNL_SLCT_OFST)
#define DUMMY_ANLG_FIFO_RD_STRBE_OFST (8)
#define DUMMY_ANLG_FIFO_RD_STRBE_MSK (0x00000001 << DUMMY_ANLG_FIFO_RD_STRBE_OFST)
#define DUMMY_ANLG_FIFO_RD_STRBE_MSK \
(0x00000001 << DUMMY_ANLG_FIFO_RD_STRBE_OFST)
#define DUMMY_DGTL_FIFO_RD_STRBE_OFST (9)
#define DUMMY_DGTL_FIFO_RD_STRBE_MSK (0x00000001 << DUMMY_DGTL_FIFO_RD_STRBE_OFST)
#define DUMMY_DGTL_FIFO_RD_STRBE_MSK \
(0x00000001 << DUMMY_DGTL_FIFO_RD_STRBE_OFST)
/* Receiver IP Address RW register */
#define RX_IP_REG (0x45 << MEM_MAP_SHIFT)
@@ -314,21 +333,23 @@
#define CONTROL_STP_ACQSTN_OFST (1)
#define CONTROL_STP_ACQSTN_MSK (0x00000001 << CONTROL_STP_ACQSTN_OFST)
//#define CONTROL_STRT_FF_TST_OFST (2)
//#define CONTROL_STRT_FF_TST_MSK (0x00000001 << CONTROL_STRT_FF_TST_OFST)
//#define CONTROL_STP_FF_TST_OFST (3)
//#define CONTROL_STP_FF_TST_MSK (0x00000001 << CONTROL_STP_FF_TST_OFST)
//#define CONTROL_STRT_RDT_OFST (4)
//#define CONTROL_STRT_RDT_MSK (0x00000001 << CONTROL_STRT_RDT_OFST)
//#define CONTROL_STP_RDT_OFST (5)
//#define CONTROL_STP_RDT_MSK (0x00000001 << CONTROL_STP_RDT_OFST)
//#define CONTROL_STRT_FF_TST_MSK (0x00000001 <<
// CONTROL_STRT_FF_TST_OFST) #define CONTROL_STP_FF_TST_OFST (3)
//#define CONTROL_STP_FF_TST_MSK (0x00000001 <<
// CONTROL_STP_FF_TST_OFST) #define CONTROL_STRT_RDT_OFST (4)
//#define CONTROL_STRT_RDT_MSK (0x00000001 <<
// CONTROL_STRT_RDT_OFST) #define CONTROL_STP_RDT_OFST (5)
// #define CONTROL_STP_RDT_MSK (0x00000001 <<
// CONTROL_STP_RDT_OFST)
#define CONTROL_STRT_EXPSR_OFST (6)
#define CONTROL_STRT_EXPSR_MSK (0x00000001 << CONTROL_STRT_EXPSR_OFST)
//#define CONTROL_STP_EXPSR_OFST (7)
//#define CONTROL_STP_EXPSR_MSK (0x00000001 << CONTROL_STP_RDT_OFST)
//#define CONTROL_STRT_TRN_OFST (8)
//#define CONTROL_STRT_TRN_MSK (0x00000001 << CONTROL_STRT_RDT_OFST)
//#define CONTROL_STP_EXPSR_MSK (0x00000001 <<
// CONTROL_STP_RDT_OFST) #define CONTROL_STRT_TRN_OFST (8) #define
// CONTROL_STRT_TRN_MSK (0x00000001 << CONTROL_STRT_RDT_OFST)
//#define CONTROL_STP_TRN_OFST (9)
//#define CONTROL_STP_TRN_MSK (0x00000001 << CONTROL_STP_RDT_OFST)
//#define CONTROL_STP_TRN_MSK (0x00000001 <<
// CONTROL_STP_RDT_OFST)
#define CONTROL_CRE_RST_OFST (10)
#define CONTROL_CRE_RST_MSK (0x00000001 << CONTROL_CRE_RST_OFST)
#define CONTROL_PRPHRL_RST_OFST (11) // Only GBE10?
@@ -336,7 +357,8 @@
#define CONTROL_MMRY_RST_OFST (12)
#define CONTROL_MMRY_RST_MSK (0x00000001 << CONTROL_MMRY_RST_OFST)
//#define CONTROL_PLL_RCNFG_WR_OFST (13)
//#define CONTROL_PLL_RCNFG_WR_MSK (0x00000001 << CONTROL_PLL_RCNFG_WR_OFST)
//#define CONTROL_PLL_RCNFG_WR_MSK (0x00000001 <<
// CONTROL_PLL_RCNFG_WR_OFST)
#define CONTROL_SND_10GB_PCKT_OFST (14)
#define CONTROL_SND_10GB_PCKT_MSK (0x00000001 << CONTROL_SND_10GB_PCKT_OFST)
#define CONTROL_CLR_ACQSTN_FIFO_OFST (15)
@@ -349,7 +371,8 @@
#define PLL_CNTRL_REG (0x51 << MEM_MAP_SHIFT)
#define PLL_CNTRL_RCNFG_PRMTR_RST_OFST (0)
#define PLL_CNTRL_RCNFG_PRMTR_RST_MSK (0x00000001 << PLL_CNTRL_RCNFG_PRMTR_RST_OFST)
#define PLL_CNTRL_RCNFG_PRMTR_RST_MSK \
(0x00000001 << PLL_CNTRL_RCNFG_PRMTR_RST_OFST)
#define PLL_CNTRL_WR_PRMTR_OFST (2)
#define PLL_CNTRL_WR_PRMTR_MSK (0x00000001 << PLL_CNTRL_WR_PRMTR_OFST)
#define PLL_CNTRL_PLL_RST_OFST (3)
@@ -379,7 +402,8 @@
#define PATTERN_LOOP_0_ADDR_REG (0x54 << MEM_MAP_SHIFT)
#define PATTERN_LOOP_0_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_0_ADDR_STRT_MSK (0x00001FFF << PATTERN_LOOP_0_ADDR_STRT_OFST)
#define PATTERN_LOOP_0_ADDR_STRT_MSK \
(0x00001FFF << PATTERN_LOOP_0_ADDR_STRT_OFST)
#define PATTERN_LOOP_0_ADDR_STP_OFST (16)
#define PATTERN_LOOP_0_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_0_ADDR_STP_OFST)
@@ -390,7 +414,8 @@
#define PATTERN_LOOP_1_ADDR_REG (0x56 << MEM_MAP_SHIFT)
#define PATTERN_LOOP_1_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_1_ADDR_STRT_MSK (0x00001FFF << PATTERN_LOOP_1_ADDR_STRT_OFST)
#define PATTERN_LOOP_1_ADDR_STRT_MSK \
(0x00001FFF << PATTERN_LOOP_1_ADDR_STRT_OFST)
#define PATTERN_LOOP_1_ADDR_STP_OFST (16)
#define PATTERN_LOOP_1_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_1_ADDR_STP_OFST)
@@ -401,7 +426,8 @@
#define PATTERN_LOOP_2_ADDR_REG (0x58 << MEM_MAP_SHIFT)
#define PATTERN_LOOP_2_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_2_ADDR_STRT_MSK (0x00001FFF << PATTERN_LOOP_2_ADDR_STRT_OFST)
#define PATTERN_LOOP_2_ADDR_STRT_MSK \
(0x00001FFF << PATTERN_LOOP_2_ADDR_STRT_OFST)
#define PATTERN_LOOP_2_ADDR_STP_OFST (16)
#define PATTERN_LOOP_2_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_2_ADDR_STP_OFST)
@@ -413,7 +439,7 @@
#define PATTERN_WAIT_0_ADDR_OFST (0)
#define PATTERN_WAIT_0_ADDR_MSK (0x00001FFF << PATTERN_WAIT_0_ADDR_OFST)
//FIXME: is mask 3FF
// FIXME: is mask 3FF
/* Pattern Wait 1 RW regiser */
#define PATTERN_WAIT_1_ADDR_REG (0x5B << MEM_MAP_SHIFT)
@@ -446,7 +472,6 @@
/* Number of Words RW register TODO */
#define NUMBER_OF_WORDS_REG (0x5F << MEM_MAP_SHIFT)
/* Delay 64 bit RW register. t = DLY x 50 ns. */
#define DELAY_LSB_REG (0x60 << MEM_MAP_SHIFT)
#define DELAY_MSB_REG (0x61 << MEM_MAP_SHIFT)
@@ -464,12 +489,14 @@
#define PERIOD_MSB_REG (0x67 << MEM_MAP_SHIFT)
/* Period 64 bit RW register */
//#define EXPTIME_LSB_REG (0x68 << MEM_MAP_SHIFT) // Not used in FW
//#define EXPTIME_MSB_REG (0x69 << MEM_MAP_SHIFT) // Not used in FW
//#define EXPTIME_LSB_REG (0x68 << MEM_MAP_SHIFT) //
// Not used in FW #define EXPTIME_MSB_REG (0x69 <<
// MEM_MAP_SHIFT) // Not used in FW
/* Gates 64 bit RW register */
//#define GATES_LSB_REG (0x6A << MEM_MAP_SHIFT) // Not used in FW
//#define GATES_MSB_REG (0x6B << MEM_MAP_SHIFT) // Not used in FW
//#define GATES_LSB_REG (0x6A << MEM_MAP_SHIFT) // Not used
// in FW #define GATES_MSB_REG (0x6B << MEM_MAP_SHIFT) //
// Not used in FW
/* Pattern IO Control 64 bit RW regiser
* Each bit configured as output(1)/ input(0) */
@@ -507,7 +534,8 @@
#define READOUT_10G_ENABLE_DGTL_MSK (0x00000001 << READOUT_10G_ENABLE_DGTL_OFST)
/* Digital Bit External Trigger RW register */
#define DBIT_EXT_TRG_REG (0x7B << MEM_MAP_SHIFT) // Not used in firmware or software
#define DBIT_EXT_TRG_REG \
(0x7B << MEM_MAP_SHIFT) // Not used in firmware or software
#define DBIT_EXT_TRG_SRC_OFST (0)
#define DBIT_EXT_TRG_SRC_MSK (0x0000003F << DBIT_EXT_TRG_SRC_OFST)
@@ -515,20 +543,26 @@
#define DBIT_EXT_TRG_OPRTN_MD_MSK (0x00000001 << DBIT_EXT_TRG_OPRTN_MD_OFST)
/* Pin Delay 0 RW register */
#define OUTPUT_DELAY_0_REG (0x7C << MEM_MAP_SHIFT) // Not used in firmware or software
#define OUTPUT_DELAY_0_REG \
(0x7C << MEM_MAP_SHIFT) // Not used in firmware or software
#define OUTPUT_DELAY_0_OTPT_STTNG_STEPS (25)
#define OUTPUT_DELAY_0_OTPT_STTNG_OFST (0) //t = OTPT_STTNG * 25 ps, max for Cyclone V = 775 ps
#define OUTPUT_DELAY_0_OTPT_STTNG_MSK (0x0000001F << OUTPUT_DELAY_0_OTPT_STTNG_OFST)
// 1: load dynamic output settings, 0: trigger start of dynamic output delay configuration pn falling edge of ODT (output delay trigger) bit
#define OUTPUT_DELAY_0_OTPT_STTNG_OFST \
(0) // t = OTPT_STTNG * 25 ps, max for Cyclone V = 775 ps
#define OUTPUT_DELAY_0_OTPT_STTNG_MSK \
(0x0000001F << OUTPUT_DELAY_0_OTPT_STTNG_OFST)
// 1: load dynamic output settings, 0: trigger start of dynamic output delay
// configuration pn falling edge of ODT (output delay trigger) bit
#define OUTPUT_DELAY_0_OTPT_TRGGR_OFST (31)
#define OUTPUT_DELAY_0_OTPT_TRGGR_MSK (0x00000001 << OUTPUT_DELAY_0_OTPT_TRGGR_OFST)
#define OUTPUT_DELAY_0_OTPT_TRGGR_MSK \
(0x00000001 << OUTPUT_DELAY_0_OTPT_TRGGR_OFST)
#define OUTPUT_DELAY_0_OTPT_TRGGR_LD_VAL (1)
#define OUTPUT_DELAY_0_OTPT_TRGGR_STRT_VAL (0)
/* Pin Delay 1 RW register
* Each bit configured as enable for dynamic output delay configuration */
#define PIN_DELAY_1_REG (0x7D << MEM_MAP_SHIFT) // Not used in firmware or software
#define PIN_DELAY_1_REG \
(0x7D << MEM_MAP_SHIFT) // Not used in firmware or software
/** Pattern Mask 64 bit RW regiser */
#define PATTERN_MASK_LSB_REG (0x80 << MEM_MAP_SHIFT)
@@ -540,5 +574,3 @@
/* Round Robin */
#define RXR_ENDPOINT_START_REG (0x1000 << MEM_MAP_SHIFT)

705
slsDetectorServers/moenchDetectorServer/slsDetectorFunctionList.c Executable file → Normal file
View File

File diff suppressed because it is too large Load Diff

39
slsDetectorServers/moenchDetectorServer/slsDetectorServer_defs.h Executable file → Normal file
View File

@@ -1,7 +1,6 @@
#pragma once
#include "sls_detector_defs.h"
#include "RegisterDefs.h"
#include "sls_detector_defs.h"
#define MIN_REQRD_VRSN_T_RD_API 0x180314
#define REQRD_FRMWR_VRSN 0x200302
@@ -15,13 +14,13 @@ typedef struct udp_header_struct {
uint16_t udp_destmac_lsb;
uint32_t udp_srcmac_lsb;
uint8_t ip_tos;
uint8_t ip_ihl: 4, ip_ver: 4;
uint8_t ip_ihl : 4, ip_ver : 4;
uint16_t udp_ethertype;
uint16_t ip_identification;
uint16_t ip_totallength;
uint8_t ip_protocol;
uint8_t ip_ttl;
uint16_t ip_fragmentoffset: 13, ip_flags: 3;
uint16_t ip_fragmentoffset : 13, ip_flags : 3;
uint16_t ip_srcip_msb;
uint16_t ip_checksum;
uint16_t ip_destip_msb;
@@ -36,9 +35,22 @@ typedef struct udp_header_struct {
#define UDP_IP_HEADER_LENGTH_BYTES (28)
/* Enums */
enum DACINDEX {MO_VBP_COLBUF, MO_VIPRE, MO_VIN_CM, MO_VB_SDA, MO_VCASC_SFP, MO_VOUT_CM, MO_VIPRE_CDS, MO_IBIAS_SFP};
#define DAC_NAMES "vbp_colbuf", "vipre", "vin_cm", "vb_sda", "vcasc_sfp", "vout_cm", "vipre_cds", "ibias_sfp"
#define DEFAULT_DAC_VALS { 1300, /* MO_VBP_COLBUF */ \
enum DACINDEX {
MO_VBP_COLBUF,
MO_VIPRE,
MO_VIN_CM,
MO_VB_SDA,
MO_VCASC_SFP,
MO_VOUT_CM,
MO_VIPRE_CDS,
MO_IBIAS_SFP
};
#define DAC_NAMES \
"vbp_colbuf", "vipre", "vin_cm", "vb_sda", "vcasc_sfp", "vout_cm", \
"vipre_cds", "ibias_sfp"
#define DEFAULT_DAC_VALS \
{ \
1300, /* MO_VBP_COLBUF */ \
1000, /* MO_VIPRE */ \
1400, /* MO_VIN_CM */ \
680, /* MO_VB_SDA */ \
@@ -48,7 +60,7 @@ enum DACINDEX {MO_VBP_COLBUF, MO_VIPRE, MO_VIN_CM, MO_VB_SDA, MO_V
900 /* MO_IBIAS_SFP */ \
};
enum CLKINDEX {RUN_CLK, ADC_CLK, SYNC_CLK, DBIT_CLK, NUM_CLOCKS};
enum CLKINDEX { RUN_CLK, ADC_CLK, SYNC_CLK, DBIT_CLK, NUM_CLOCKS };
#define CLK_NAMES "run", "adc", "sync", "dbit"
/* Hardware Definitions */
@@ -68,7 +80,7 @@ enum CLKINDEX {RUN_CLK, ADC_CLK, SYNC_CLK, DBIT_CLK, NUM_CLOCKS};
#define DEFAULT_EXPTIME (0)
#define DEFAULT_NUM_FRAMES (1)
#define DEFAULT_NUM_CYCLES (1)
#define DEFAULT_PERIOD (1 * 1000 * 1000) //ns
#define DEFAULT_PERIOD (1 * 1000 * 1000) // ns
#define DEFAULT_DELAY (0)
#define DEFAULT_HIGH_VOLTAGE (0)
#define DEFAULT_VLIMIT (-100)
@@ -106,10 +118,14 @@ enum CLKINDEX {RUN_CLK, ADC_CLK, SYNC_CLK, DBIT_CLK, NUM_CLOCKS};
/* Defines in the Firmware */
#define MAX_PATTERN_LENGTH (0x2000)
#define DIGITAL_IO_DELAY_MAXIMUM_PS ((OUTPUT_DELAY_0_OTPT_STTNG_MSK >> OUTPUT_DELAY_0_OTPT_STTNG_OFST) * OUTPUT_DELAY_0_OTPT_STTNG_STEPS)
#define DIGITAL_IO_DELAY_MAXIMUM_PS \
((OUTPUT_DELAY_0_OTPT_STTNG_MSK >> OUTPUT_DELAY_0_OTPT_STTNG_OFST) * \
OUTPUT_DELAY_0_OTPT_STTNG_STEPS)
#define MAX_PHASE_SHIFTS_STEPS (8)
#define WAIT_TME_US_FR_ACQDONE_REG (100) // wait time in us after acquisition done to ensure there is no data in fifo
#define WAIT_TME_US_FR_ACQDONE_REG \
(100) // wait time in us after acquisition done to ensure there is no data
// in fifo
#define WAIT_TIME_US_PLL (10 * 1000)
#define WAIT_TIME_US_STP_ACQ (100)
#define WAIT_TIME_CONFIGURE_MAC (2 * 1000 * 1000)
@@ -125,4 +141,3 @@ enum CLKINDEX {RUN_CLK, ADC_CLK, SYNC_CLK, DBIT_CLK, NUM_CLOCKS};
#define ADC_PORT_INVERT_VAL (0x4a342593)
#define MAXIMUM_ADC_CLK (20)
#define PLL_VCO_FREQ_MHZ (800)

77
slsDetectorServers/mythen3DetectorServer/RegisterDefs.h
View File

@@ -1,6 +1,5 @@
#pragma once
#define REG_OFFSET (4)
/* Base addresses 0x1804 0000 ---------------------------------------------*/
@@ -43,9 +42,8 @@
/* Pattern RAM. Pattern table */
#define BASE_PATTERN_RAM (0x10000) // 0x1807_0000 - 0x1807_FFFF
/* Clock Generation registers ------------------------------------------------------*/
/* Clock Generation registers
* ------------------------------------------------------*/
#define PLL_RESET_REG (0x00 * REG_OFFSET + BASE_CLK_GENERATION)
#define PLL_RESET_READOUT_OFST (0)
@@ -53,8 +51,6 @@
#define PLL_RESET_SYSTEM_OFST (1)
#define PLL_RESET_SYSTEM_MSK (0x00000001 << PLL_RESET_SYSTEM_OFST)
/* Control registers --------------------------------------------------*/
/* Module Control Board Serial Number Register */
@@ -71,14 +67,14 @@
#define DETECTOR_TYPE_OFST (24)
#define DETECTOR_TYPE_MSK (0x000000FF << DETECTOR_TYPE_OFST)
/* API Version Register */
#define API_VERSION_REG (0x02 * REG_OFFSET + BASE_CONTROL)
#define API_VERSION_OFST (0)
#define API_VERSION_MSK (0x00FFFFFF << API_VERSION_OFST)
#define API_VERSION_DETECTOR_TYPE_OFST (24) //Not used in software
#define API_VERSION_DETECTOR_TYPE_MSK (0x000000FF << API_VERSION_DETECTOR_TYPE_OFST) //Not used in software
#define API_VERSION_DETECTOR_TYPE_OFST (24) // Not used in software
#define API_VERSION_DETECTOR_TYPE_MSK \
(0x000000FF << API_VERSION_DETECTOR_TYPE_OFST) // Not used in software
/* Fix pattern register */
#define FIX_PATT_REG (0x03 * REG_OFFSET + BASE_CONTROL)
@@ -88,25 +84,35 @@
#define STATUS_REG (0x04 * REG_OFFSET + BASE_CONTROL)
/* Look at me register, read only */
#define LOOK_AT_ME_REG (0x05 * REG_OFFSET + BASE_CONTROL) //Not used in firmware or software, good to play with
#define SYSTEM_STATUS_REG (0x06 * REG_OFFSET + BASE_CONTROL) //Not used in software
#define LOOK_AT_ME_REG \
(0x05 * REG_OFFSET + \
BASE_CONTROL) // Not used in firmware or software, good to play with
#define SYSTEM_STATUS_REG \
(0x06 * REG_OFFSET + BASE_CONTROL) // Not used in software
/* Config RW regiseter */
#define CONFIG_REG (0x20 * REG_OFFSET + BASE_CONTROL)
#define CONFIG_COUNTER_ENA_OFST (0)
#define CONFIG_COUNTER_ENA_MSK (0x00000003 << CONFIG_COUNTER_ENA_OFST)
#define CONFIG_COUNTER_ENA_DEFAULT_VAL ((0x0 << CONFIG_COUNTER_ENA_OFST) & CONFIG_COUNTER_ENA_MSK)
#define CONFIG_COUNTER_ENA_1_VAL ((0x1 << CONFIG_COUNTER_ENA_OFST) & CONFIG_COUNTER_ENA_MSK)
#define CONFIG_COUNTER_ENA_2_VAL ((0x2 << CONFIG_COUNTER_ENA_OFST) & CONFIG_COUNTER_ENA_MSK)
#define CONFIG_COUNTER_ENA_ALL_VAL ((0x3 << CONFIG_COUNTER_ENA_OFST) & CONFIG_COUNTER_ENA_MSK)
#define CONFIG_COUNTER_ENA_DEFAULT_VAL \
((0x0 << CONFIG_COUNTER_ENA_OFST) & CONFIG_COUNTER_ENA_MSK)
#define CONFIG_COUNTER_ENA_1_VAL \
((0x1 << CONFIG_COUNTER_ENA_OFST) & CONFIG_COUNTER_ENA_MSK)
#define CONFIG_COUNTER_ENA_2_VAL \
((0x2 << CONFIG_COUNTER_ENA_OFST) & CONFIG_COUNTER_ENA_MSK)
#define CONFIG_COUNTER_ENA_ALL_VAL \
((0x3 << CONFIG_COUNTER_ENA_OFST) & CONFIG_COUNTER_ENA_MSK)
#define CONFIG_DYNAMIC_RANGE_OFST (4)
#define CONFIG_DYNAMIC_RANGE_MSK (0x00000003 << CONFIG_DYNAMIC_RANGE_OFST)
#define CONFIG_DYNAMIC_RANGE_1_VAL ((0x0 << CONFIG_DYNAMIC_RANGE_OFST) & CONFIG_DYNAMIC_RANGE_MSK)
#define CONFIG_DYNAMIC_RANGE_4_VAL ((0x1 << CONFIG_DYNAMIC_RANGE_OFST) & CONFIG_DYNAMIC_RANGE_MSK)
#define CONFIG_DYNAMIC_RANGE_16_VAL ((0x2 << CONFIG_DYNAMIC_RANGE_OFST) & CONFIG_DYNAMIC_RANGE_MSK)
#define CONFIG_DYNAMIC_RANGE_24_VAL ((0x3 << CONFIG_DYNAMIC_RANGE_OFST) & CONFIG_DYNAMIC_RANGE_MSK)
#define CONFIG_DYNAMIC_RANGE_1_VAL \
((0x0 << CONFIG_DYNAMIC_RANGE_OFST) & CONFIG_DYNAMIC_RANGE_MSK)
#define CONFIG_DYNAMIC_RANGE_4_VAL \
((0x1 << CONFIG_DYNAMIC_RANGE_OFST) & CONFIG_DYNAMIC_RANGE_MSK)
#define CONFIG_DYNAMIC_RANGE_16_VAL \
((0x2 << CONFIG_DYNAMIC_RANGE_OFST) & CONFIG_DYNAMIC_RANGE_MSK)
#define CONFIG_DYNAMIC_RANGE_24_VAL \
((0x3 << CONFIG_DYNAMIC_RANGE_OFST) & CONFIG_DYNAMIC_RANGE_MSK)
/* Control RW register */
#define CONTROL_REG (0x21 * REG_OFFSET + BASE_CONTROL)
@@ -130,8 +136,6 @@
#define DTA_OFFSET_REG (0x24 * REG_OFFSET + BASE_CONTROL)
/* Packetizer -------------------------------------------------------------*/
/* Packetizer Config Register */
@@ -154,23 +158,27 @@
#define COORD_RESERVED_OFST (0)
#define COORD_RESERVED_MSK (0x0000FFFF << COORD_RESERVED_OFST)
#define COORD_ID_OFST (16) // Not connected in firmware TODO
#define COORD_ID_MSK (0x0000FFFF << COORD_ID_OFST) // Not connected in firmware TODO
#define COORD_ID_MSK \
(0x0000FFFF << COORD_ID_OFST) // Not connected in firmware TODO
/* Pattern Control registers --------------------------------------------------*/
/* Pattern Control registers
* --------------------------------------------------*/
/* Pattern status Register*/
#define PAT_STATUS_REG (0x00 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define PAT_STATUS_RUN_BUSY_OFST (0)
#define PAT_STATUS_RUN_BUSY_MSK (0x00000001 << PAT_STATUS_RUN_BUSY_OFST)
#define PAT_STATUS_WAIT_FOR_TRGGR_OFST (3)
#define PAT_STATUS_WAIT_FOR_TRGGR_MSK (0x00000001 << PAT_STATUS_WAIT_FOR_TRGGR_OFST)
#define PAT_STATUS_WAIT_FOR_TRGGR_MSK \
(0x00000001 << PAT_STATUS_WAIT_FOR_TRGGR_OFST)
#define PAT_STATUS_DLY_BFRE_TRGGR_OFST (4)
#define PAT_STATUS_DLY_BFRE_TRGGR_MSK (0x00000001 << PAT_STATUS_DLY_BFRE_TRGGR_OFST)
#define PAT_STATUS_DLY_BFRE_TRGGR_MSK \
(0x00000001 << PAT_STATUS_DLY_BFRE_TRGGR_OFST)
#define PAT_STATUS_FIFO_FULL_OFST (5)
#define PAT_STATUS_FIFO_FULL_MSK (0x00000001 << PAT_STATUS_FIFO_FULL_OFST)
#define PAT_STATUS_DLY_AFTR_TRGGR_OFST (15)
#define PAT_STATUS_DLY_AFTR_TRGGR_MSK (0x00000001 << PAT_STATUS_DLY_AFTR_TRGGR_OFST)
#define PAT_STATUS_DLY_AFTR_TRGGR_MSK \
(0x00000001 << PAT_STATUS_DLY_AFTR_TRGGR_OFST)
#define PAT_STATUS_CSM_BUSY_OFST (17)
#define PAT_STATUS_CSM_BUSY_MSK (0x00000001 << PAT_STATUS_CSM_BUSY_OFST)
@@ -194,7 +202,8 @@
#define TIME_FROM_START_LSB_REG (0x0A * REG_OFFSET + BASE_PATTERN_CONTROL)
#define TIME_FROM_START_MSB_REG (0x0B * REG_OFFSET + BASE_PATTERN_CONTROL)
/* Get Frames from Start 64 bit register (frames from last reset using CONTROL_CRST) */
/* Get Frames from Start 64 bit register (frames from last reset using
* CONTROL_CRST) */
#define FRAMES_FROM_START_LSB_REG (0x0C * REG_OFFSET + BASE_PATTERN_CONTROL)
#define FRAMES_FROM_START_MSB_REG (0x0D * REG_OFFSET + BASE_PATTERN_CONTROL)
@@ -261,7 +270,8 @@
#define PATTERN_LOOP_0_ADDR_REG (0x64 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define PATTERN_LOOP_0_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_0_ADDR_STRT_MSK (0x00001FFF << PATTERN_LOOP_0_ADDR_STRT_OFST)
#define PATTERN_LOOP_0_ADDR_STRT_MSK \
(0x00001FFF << PATTERN_LOOP_0_ADDR_STRT_OFST)
#define PATTERN_LOOP_0_ADDR_STP_OFST (16)
#define PATTERN_LOOP_0_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_0_ADDR_STP_OFST)
@@ -282,7 +292,8 @@
#define PATTERN_LOOP_1_ADDR_REG (0x69 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define PATTERN_LOOP_1_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_1_ADDR_STRT_MSK (0x00001FFF << PATTERN_LOOP_1_ADDR_STRT_OFST)
#define PATTERN_LOOP_1_ADDR_STRT_MSK \
(0x00001FFF << PATTERN_LOOP_1_ADDR_STRT_OFST)
#define PATTERN_LOOP_1_ADDR_STP_OFST (16)
#define PATTERN_LOOP_1_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_1_ADDR_STP_OFST)
@@ -303,11 +314,11 @@
#define PATTERN_LOOP_2_ADDR_REG (0x6E * REG_OFFSET + BASE_PATTERN_CONTROL)
#define PATTERN_LOOP_2_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_2_ADDR_STRT_MSK (0x00001FFF << PATTERN_LOOP_2_ADDR_STRT_OFST)
#define PATTERN_LOOP_2_ADDR_STRT_MSK \
(0x00001FFF << PATTERN_LOOP_2_ADDR_STRT_OFST)
#define PATTERN_LOOP_2_ADDR_STP_OFST (16)
#define PATTERN_LOOP_2_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_2_ADDR_STP_OFST)
/* Pattern RAM registers --------------------------------------------------*/
/* Register of first word */

506
slsDetectorServers/mythen3DetectorServer/slsDetectorFunctionList.c
View File

File diff suppressed because it is too large Load Diff

62
slsDetectorServers/mythen3DetectorServer/slsDetectorServer_defs.h
View File

@@ -22,22 +22,20 @@
#define TYPE_TOLERANCE (10)
#define TYPE_NO_MODULE_STARTING_VAL (800)
/** Default Parameters */
#define DEFAULT_DYNAMIC_RANGE (24)
#define DEFAULT_NUM_FRAMES (1)
#define DEFAULT_NUM_CYCLES (1)
#define DEFAULT_EXPTIME (100*1000*1000) //ns
#define DEFAULT_PERIOD (2*1000*1000) //ns
#define DEFAULT_EXPTIME (100 * 1000 * 1000) // ns
#define DEFAULT_PERIOD (2 * 1000 * 1000) // ns
#define DEFAULT_DELAY_AFTER_TRIGGER (0)
#define DEFAULT_HIGH_VOLTAGE (0)
#define DEFAULT_TIMING_MODE (AUTO_TIMING)
#define DEFAULT_READOUT_C0 (10)//(125000000) // rdo_clk, 125 MHz
#define DEFAULT_READOUT_C1 (10)//(125000000) // rdo_x2_clk, 125 MHz
#define DEFAULT_SYSTEM_C0 (5)//(250000000) // run_clk, 250 MHz
#define DEFAULT_SYSTEM_C1 (10)//(125000000) // chip_clk, 125 MHz
#define DEFAULT_SYSTEM_C2 (10)//(125000000) // sync_clk, 125 MHz
#define DEFAULT_READOUT_C0 (10) //(125000000) // rdo_clk, 125 MHz
#define DEFAULT_READOUT_C1 (10) //(125000000) // rdo_x2_clk, 125 MHz
#define DEFAULT_SYSTEM_C0 (5) //(250000000) // run_clk, 250 MHz
#define DEFAULT_SYSTEM_C1 (10) //(125000000) // chip_clk, 125 MHz
#define DEFAULT_SYSTEM_C2 (10) //(125000000) // sync_clk, 125 MHz
/* Firmware Definitions */
#define IP_HEADER_SIZE (20)
@@ -50,9 +48,31 @@
#define BIT16_MASK (0xFFFF)
/* Enums */
enum DACINDEX {M_CASSH, M_VTH2, M_VRFSH, M_VRFSHNPOL, M_VIPRE_OUT, M_VTH3, M_VTH1, M_VICIN, M_CAS, M_VRF, M_VPL, M_VIPRE, M_VIINSH, M_VPH, M_VTRIM, M_VDCSH};
#define DAC_NAMES "vcassh", "vth2", "vshaper", "vshaperneg", "vipre_out", "vth3", "vth1", "vicin", "vcas", "vpreamp", "vpl", "vipre", "viinsh", "vph", "vtrim", "vdcsh"
#define DEFAULT_DAC_VALS {1200, /* casSh */ \
enum DACINDEX {
M_CASSH,
M_VTH2,
M_VRFSH,
M_VRFSHNPOL,
M_VIPRE_OUT,
M_VTH3,
M_VTH1,
M_VICIN,
M_CAS,
M_VRF,
M_VPL,
M_VIPRE,
M_VIINSH,
M_VPH,
M_VTRIM,
M_VDCSH
};
#define DAC_NAMES \
"vcassh", "vth2", "vshaper", "vshaperneg", "vipre_out", "vth3", "vth1", \
"vicin", "vcas", "vpreamp", "vpl", "vipre", "viinsh", "vph", "vtrim", \
"vdcsh"
#define DEFAULT_DAC_VALS \
{ \
1200, /* casSh */ \
2800, /* Vth2 */ \
1280, /* VrfSh */ \
2800, /* VrfShNpol */ \
@@ -69,9 +89,17 @@ enum DACINDEX {M_CASSH, M_VTH2, M_VRFSH, M_VRFSHNPOL, M_VIPRE_OUT, M_VTH3
2800, /* vTrim */ \
800 /* VdcSh */ \
};
enum CLKINDEX {READOUT_C0, READOUT_C1, SYSTEM_C0, SYSTEM_C1, SYSTEM_C2, NUM_CLOCKS};
#define CLK_NAMES "READOUT_C0", "READOUT_C1", "SYSTEM_C0", "SYSTEM_C1", "SYSTEM_C2"
enum PLLINDEX {READOUT_PLL, SYSTEM_PLL};
enum CLKINDEX {
READOUT_C0,
READOUT_C1,
SYSTEM_C0,
SYSTEM_C1,
SYSTEM_C2,
NUM_CLOCKS
};
#define CLK_NAMES \
"READOUT_C0", "READOUT_C1", "SYSTEM_C0", "SYSTEM_C1", "SYSTEM_C2"
enum PLLINDEX { READOUT_PLL, SYSTEM_PLL };
/* Struct Definitions */
typedef struct udp_header_struct {
@@ -80,13 +108,13 @@ typedef struct udp_header_struct {
uint16_t udp_destmac_lsb;
uint32_t udp_srcmac_lsb;
uint8_t ip_tos;
uint8_t ip_ihl: 4, ip_ver: 4;
uint8_t ip_ihl : 4, ip_ver : 4;
uint16_t udp_ethertype;
uint16_t ip_identification;
uint16_t ip_totallength;
uint8_t ip_protocol;
uint8_t ip_ttl;
uint16_t ip_fragmentoffset: 13, ip_flags: 3;
uint16_t ip_fragmentoffset : 13, ip_flags : 3;
uint16_t ip_srcip_msb;
uint16_t ip_checksum;
uint16_t ip_destip_msb;

3
slsDetectorServers/slsDetectorServer/include/AD7689.h Executable file → Normal file
View File

@@ -11,7 +11,8 @@
* @param dmsk digital output mask
* @param dofst digital output offset
*/
void AD7689_SetDefines(uint32_t reg, uint32_t roreg, uint32_t cmsk, uint32_t clkmsk, uint32_t dmsk, int dofst);
void AD7689_SetDefines(uint32_t reg, uint32_t roreg, uint32_t cmsk,
uint32_t clkmsk, uint32_t dmsk, int dofst);
/**
* Disable SPI

3
slsDetectorServers/slsDetectorServer/include/AD9252.h Executable file → Normal file
View File

@@ -10,7 +10,8 @@
* @param dmsk digital output mask
* @param dofst digital output offset
*/
void AD9252_SetDefines(uint32_t reg, uint32_t cmsk, uint32_t clkmsk, uint32_t dmsk, int dofst);
void AD9252_SetDefines(uint32_t reg, uint32_t cmsk, uint32_t clkmsk,
uint32_t dmsk, int dofst);
/**
* Disable SPI

8
slsDetectorServers/slsDetectorServer/include/AD9257.h Executable file → Normal file
View File

@@ -10,12 +10,13 @@
* @param dmsk digital output mask
* @param dofst digital output offset
*/
void AD9257_SetDefines(uint32_t reg, uint32_t cmsk, uint32_t clkmsk, uint32_t dmsk, int dofst);
void AD9257_SetDefines(uint32_t reg, uint32_t cmsk, uint32_t clkmsk,
uint32_t dmsk, int dofst);
/**
* Disable SPI
*/
void AD9257_Disable() ;
void AD9257_Disable();
/**
* Get vref voltage
@@ -24,7 +25,8 @@ int AD9257_GetVrefVoltage(int mV);
/**
* Set vref voltage
* @param val voltage to be set (0 for 1.0V, 1 for 1.14V, 2 for 1.33V, 3 for 1.6V, 4 for 2.0V
* @param val voltage to be set (0 for 1.0V, 1 for 1.14V, 2 for 1.33V, 3
* for 1.6V, 4 for 2.0V
* @returns ok or fail
*/
int AD9257_SetVrefVoltage(int val, int mV);

21
slsDetectorServers/slsDetectorServer/include/ALTERA_PLL.h Executable file → Normal file
View File

@@ -15,7 +15,9 @@
* @param wd2msk write parameter mask for pll for dbit clock (Jungfrau only)
* @param clk2Index clkIndex of second pll (Jungfrau only)
*/
void ALTERA_PLL_SetDefines(uint32_t creg, uint32_t preg, uint32_t rprmsk, uint32_t wpmsk, uint32_t prmsk, uint32_t amsk, int aofst, uint32_t wd2msk, int clk2Index);
void ALTERA_PLL_SetDefines(uint32_t creg, uint32_t preg, uint32_t rprmsk,
uint32_t wpmsk, uint32_t prmsk, uint32_t amsk,
int aofst, uint32_t wd2msk, int clk2Index);
#else
/**
* Set Defines
@@ -27,26 +29,30 @@ void ALTERA_PLL_SetDefines(uint32_t creg, uint32_t preg, uint32_t rprmsk, uint32
* @param amsk address mask
* @param aofst address offset
*/
void ALTERA_PLL_SetDefines(uint32_t creg, uint32_t preg, uint32_t rprmsk, uint32_t wpmsk, uint32_t prmsk, uint32_t amsk, int aofst);
void ALTERA_PLL_SetDefines(uint32_t creg, uint32_t preg, uint32_t rprmsk,
uint32_t wpmsk, uint32_t prmsk, uint32_t amsk,
int aofst);
#endif
/**
* Reset only PLL
*/
void ALTERA_PLL_ResetPLL ();
void ALTERA_PLL_ResetPLL();
/**
* Reset PLL Reconfiguration and PLL
*/
void ALTERA_PLL_ResetPLLAndReconfiguration ();
void ALTERA_PLL_ResetPLLAndReconfiguration();
/**
* Set PLL Reconfig register
* @param reg register
* @param val value
* @param useDefaultWRMask only jungfrau for dbit clk (clkindex1, use second WR mask)
* @param useDefaultWRMask only jungfrau for dbit clk (clkindex1, use second WR
* mask)
*/
void ALTERA_PLL_SetPllReconfigReg(uint32_t reg, uint32_t val, int useSecondWRMask);
void ALTERA_PLL_SetPllReconfigReg(uint32_t reg, uint32_t val,
int useSecondWRMask);
/**
* Write Phase Shift
@@ -67,5 +73,4 @@ void ALTERA_PLL_SetModePolling();
* @param value frequency to set to
* @param frequency set
*/
int ALTERA_PLL_SetOuputFrequency (int clkIndex, int pllVCOFreqMhz, int value);
int ALTERA_PLL_SetOuputFrequency(int clkIndex, int pllVCOFreqMhz, int value);

13
slsDetectorServers/slsDetectorServer/include/ALTERA_PLL_CYCLONE10.h Executable file → Normal file
View File

@@ -14,7 +14,10 @@
* @param vcofreq0 vco frequency of pll 0
* @param vcofreq1 vco frequency of pll 1
*/
void ALTERA_PLL_C10_SetDefines(int regofst, uint32_t baseaddr0, uint32_t baseaddr1, uint32_t resetreg0, uint32_t resetreg1, uint32_t resetmsk0, uint32_t resetmsk1, int vcofreq0, int vcofreq1);
void ALTERA_PLL_C10_SetDefines(int regofst, uint32_t baseaddr0,
uint32_t baseaddr1, uint32_t resetreg0,
uint32_t resetreg1, uint32_t resetmsk0,
uint32_t resetmsk1, int vcofreq0, int vcofreq1);
/**
* Get Max Clock Divider
@@ -44,7 +47,7 @@ void ALTERA_PLL_C10_Reconfigure(int pllIndex);
* Reset pll
* @param pllIndex pll index
*/
void ALTERA_PLL_C10_ResetPLL (int pllIndex);
void ALTERA_PLL_C10_ResetPLL(int pllIndex);
/**
* Set Phase Shift
@@ -53,7 +56,8 @@ void ALTERA_PLL_C10_ResetPLL (int pllIndex);
* @param phase phase shift
* @param pos 1 if up down direction of shift is positive, else 0
*/
void ALTERA_PLL_C10_SetPhaseShift(int pllIndex, int clkIndex, int phase, int pos);
void ALTERA_PLL_C10_SetPhaseShift(int pllIndex, int clkIndex, int phase,
int pos);
/**
* Calculate and write output frequency
@@ -61,5 +65,4 @@ void ALTERA_PLL_C10_SetPhaseShift(int pllIndex, int clkIndex, int phase, int pos
* @param clkIndex clock index
* @param value clock divider to set to
*/
void ALTERA_PLL_C10_SetOuputClockDivider (int pllIndex, int clkIndex, int value);
void ALTERA_PLL_C10_SetOuputClockDivider(int pllIndex, int clkIndex, int value);

4
slsDetectorServers/slsDetectorServer/include/ASIC_Driver.h Executable file → Normal file
View File

@@ -6,7 +6,7 @@
* Set Defines
* @param driverfname driver file name
*/
void ASIC_Driver_SetDefines(char* driverfname);
void ASIC_Driver_SetDefines(char *driverfname);
/**
* Set value
@@ -15,4 +15,4 @@ void ASIC_Driver_SetDefines(char* driverfname);
* @param buffer buffer
* @return OK or FAIL
*/
int ASIC_Driver_Set(int index, int length, char* buffer);
int ASIC_Driver_Set(int index, int length, char *buffer);

7
slsDetectorServers/slsDetectorServer/include/DAC6571.h Executable file → Normal file
View File

@@ -7,14 +7,11 @@
* @param hardMaxV maximum hardware limit
* @param driverfname driver file name
*/
void DAC6571_SetDefines(int hardMaxV, char* driverfname);
void DAC6571_SetDefines(int hardMaxV, char *driverfname);
/**
* Set value
* @param val value to set
* @return OK or FAIL
*/
int DAC6571_Set (int val) ;
int DAC6571_Set(int val);

8
slsDetectorServers/slsDetectorServer/include/I2C.h Executable file → Normal file
View File

@@ -15,9 +15,9 @@
* @param sdreg sda hold register (defined in RegisterDefs.h)
* @param treg transfer command fifo register (defined in RegisterDefs.h)
*/
void I2C_ConfigureI2CCore(uint32_t creg, uint32_t sreg,
uint32_t rreg, uint32_t rlvlreg,
uint32_t slreg, uint32_t shreg, uint32_t sdreg, uint32_t treg);
void I2C_ConfigureI2CCore(uint32_t creg, uint32_t sreg, uint32_t rreg,
uint32_t rlvlreg, uint32_t slreg, uint32_t shreg,
uint32_t sdreg, uint32_t treg);
/**
* Read register
@@ -34,5 +34,3 @@ uint32_t I2C_Read(uint32_t devId, uint32_t addr);
* @param data data to be written (16 bit)
*/
void I2C_Write(uint32_t devId, uint32_t addr, uint16_t data);

7
slsDetectorServers/slsDetectorServer/include/INA226.h Executable file → Normal file
View File

@@ -4,7 +4,8 @@
/**
* Configure the I2C core and Enable core
* @param rOhm shunt resister value in Ohms (defined in slsDetectorServer_defs.h)
* @param rOhm shunt resister value in Ohms (defined in
* slsDetectorServer_defs.h)
* @param creg control register (defined in RegisterDefs.h)
* @param sreg status register (defined in RegisterDefs.h)
* @param rreg rx data fifo register (defined in RegisterDefs.h)
@@ -15,8 +16,8 @@
* @param treg transfer command fifo register (defined in RegisterDefs.h)
*/
void INA226_ConfigureI2CCore(double rOhm, uint32_t creg, uint32_t sreg,
uint32_t rreg, uint32_t rlvlreg,
uint32_t slreg, uint32_t shreg, uint32_t sdreg, uint32_t treg);
uint32_t rreg, uint32_t rlvlreg, uint32_t slreg,
uint32_t shreg, uint32_t sdreg, uint32_t treg);
/**
* Calibrate resolution of current register

19
slsDetectorServers/slsDetectorServer/include/LTC2620.h Executable file → Normal file
View File

@@ -9,11 +9,13 @@
* @param clkmsk clock output mask
* @param dmsk digital output mask
* @param dofst digital output offset
* @param nd total number of dacs for this board (for dac channel and daisy chain chip id)
* @param nd total number of dacs for this board (for dac channel and daisy
* chain chip id)
* @param minMV minimum voltage determined by hardware
* @param maxMV maximum voltage determined by hardware
*/
void LTC2620_SetDefines(uint32_t reg, uint32_t cmsk, uint32_t clkmsk, uint32_t dmsk, int dofst, int nd, int minMV, int maxMV);
void LTC2620_SetDefines(uint32_t reg, uint32_t cmsk, uint32_t clkmsk,
uint32_t dmsk, int dofst, int nd, int minMV, int maxMV);
/**
* Disable SPI
@@ -46,7 +48,7 @@ int LTC2620_GetMaxNumSteps();
* @param dacval pointer to value converted to dac units
* @returns FAIL when voltage outside limits, OK if conversion successful
*/
int LTC2620_VoltageToDac(int voltage, int* dacval);
int LTC2620_VoltageToDac(int voltage, int *dacval);
/**
* Convert dac units to voltage
@@ -54,7 +56,7 @@ int LTC2620_VoltageToDac(int voltage, int* dacval);
* @param voltage pointer to value converted to mV
* @returns FAIL when voltage outside limits, OK if conversion successful
*/
int LTC2620_DacToVoltage(int dacval, int* voltage);
int LTC2620_DacToVoltage(int dacval, int *voltage);
/**
* Set a single chip (all non ctb detectors use this)
@@ -70,7 +72,7 @@ void LTC2620_SetSingle(int cmd, int data, int dacaddr);
* @param valw current value of register while bit banging
* @param val data to be sent (data, dac addr and command)
*/
void LTC2620_SendDaisyData(uint32_t* valw, uint32_t val);
void LTC2620_SendDaisyData(uint32_t *valw, uint32_t val);
/**
* Set a single chip (all non ctb detectors use this)
@@ -84,7 +86,8 @@ void LTC2620_SetDaisy(int cmd, int data, int dacaddr, int chipIndex);
/**
* Sets a single chip (LTC2620_SetSingle) or multiple chip (LTC2620_SetDaisy)
* multiple chip is only for ctb where the multiple chips are connected in daisy fashion
* multiple chip is only for ctb where the multiple chips are connected in daisy
* fashion
* @param cmd command to send
* @param data dac value to be set
* @param dacaddr dac channel number for the chip
@@ -102,7 +105,7 @@ void LTC2620_Configure();
* @param dacnum dac number
* @param data dac value to set
*/
void LTC2620_SetDAC (int dacnum, int data);
void LTC2620_SetDAC(int dacnum, int data);
/**
* Set dac in dac units or mV
@@ -112,4 +115,4 @@ void LTC2620_SetDAC (int dacnum, int data);
* @param dacval pointer to value in dac units
* @returns OK or FAIL for success of operation
*/
int LTC2620_SetDACValue (int dacnum, int val, int mV, int* dacval);
int LTC2620_SetDACValue(int dacnum, int val, int mV, int *dacval);

10
slsDetectorServers/slsDetectorServer/include/LTC2620_Driver.h Executable file → Normal file
View File

@@ -8,8 +8,7 @@
* @param driverfname driver file name
* @param numdacs number of dacs
*/
void LTC2620_D_SetDefines(int hardMaxV, char* driverfname, int numdacs);
void LTC2620_D_SetDefines(int hardMaxV, char *driverfname, int numdacs);
/**
* Get max number of steps
@@ -22,7 +21,7 @@ int LTC2620_D_GetMaxNumSteps();
* @param dacval pointer to value converted to dac units
* @returns FAIL when voltage outside limits, OK if conversion successful
*/
int LTC2620_D_VoltageToDac(int voltage, int* dacval);
int LTC2620_D_VoltageToDac(int voltage, int *dacval);
/**
* Convert dac units to voltage
@@ -30,7 +29,7 @@ int LTC2620_D_VoltageToDac(int voltage, int* dacval);
* @param voltage pointer to value converted to mV
* @returns FAIL when voltage outside limits, OK if conversion successful
*/
int LTC2620_D_DacToVoltage(int dacval, int* voltage);
int LTC2620_D_DacToVoltage(int dacval, int *voltage);
/**
* Set value
@@ -41,4 +40,5 @@ int LTC2620_D_DacToVoltage(int dacval, int* voltage);
* @param dacval pointer to dac value
* @return OK or FAIL
*/
int LTC2620_D_SetDACValue(int dacnum, int val, int mV, char* dacname, int *dacval);
int LTC2620_D_SetDACValue(int dacnum, int val, int mV, char *dacname,
int *dacval);

9
slsDetectorServers/slsDetectorServer/include/MAX1932.h Executable file → Normal file
View File

@@ -12,8 +12,8 @@
* @param minMV minimum voltage determined by hardware
* @param maxMV maximum voltage determined by hardware
*/
void MAX1932_SetDefines(uint32_t reg, uint32_t cmsk, uint32_t clkmsk, uint32_t dmsk, int dofst,
int minMV, int maxMV);
void MAX1932_SetDefines(uint32_t reg, uint32_t cmsk, uint32_t clkmsk,
uint32_t dmsk, int dofst, int minMV, int maxMV);
/**
* Disable SPI
@@ -25,7 +25,4 @@ void MAX1932_Disable();
* @param val pointer to value to set
* @return OK or FAIL
*/
int MAX1932_Set (int* val) ;
int MAX1932_Set(int *val);

4
slsDetectorServers/slsDetectorServer/include/UDPPacketHeaderGenerator.h Executable file → Normal file
View File

@@ -17,10 +17,10 @@ uint64_t getUDPFrameNumber();
* @param buffer pointer to header
* @param id module id
*/
void createUDPPacketHeader(char* buffer, uint16_t id);
void createUDPPacketHeader(char *buffer, uint16_t id);
/**
* fill up the udp packet with data till its full
* @param buffer pointer to memory
*/
int fillUDPPacket(char* buffer);
int fillUDPPacket(char *buffer);

4
slsDetectorServers/slsDetectorServer/include/blackfin.h Executable file → Normal file
View File

@@ -1,7 +1,7 @@
#pragma once
#include <sys/types.h>
#include <inttypes.h>
#include <sys/types.h>
/** I2C defines */
#define I2C_CLOCK_MHZ (131.25)
@@ -98,7 +98,7 @@ u_int32_t writeRegister16(u_int32_t offset, u_int32_t data);
/**
* Get base address for memory copy
*/
uint32_t* Blackfin_getBaseAddress();
uint32_t *Blackfin_getBaseAddress();
/**
* Map FPGA
*/

92
slsDetectorServers/slsDetectorServer/include/clogger.h Executable file → Normal file
View File

@@ -2,10 +2,9 @@
#include "ansi.h"
#include <stdlib.h>
#include <stdio.h>
#include <stdarg.h>
#include <stdio.h>
#include <stdlib.h>
#ifdef FIFODEBUG
#define FILELOG_MAX_LEVEL logDEBUG5
@@ -21,48 +20,85 @@
#define FILELOG_MAX_LEVEL logINFO
#endif
enum TLogLevel{
logERROR, logWARNING, logINFOBLUE, logINFOGREEN, logINFORED, logINFO,
logDEBUG, logDEBUG1, logDEBUG2, logDEBUG3, logDEBUG4, logDEBUG5
enum TLogLevel {
logERROR,
logWARNING,
logINFOBLUE,
logINFOGREEN,
logINFORED,
logINFO,
logDEBUG,
logDEBUG1,
logDEBUG2,
logDEBUG3,
logDEBUG4,
logDEBUG5
};
#define ERROR_MSG_LENGTH 1000
#define LOG(lvl, fmt, ...) \
if (lvl > FILELOG_MAX_LEVEL); \
else {char* temp = FILELOG_BuildLog fmt; FILELOG_PrintLog(lvl, temp);free(temp);}
if (lvl > FILELOG_MAX_LEVEL) \
; \
else { \
char *temp = FILELOG_BuildLog fmt; \
FILELOG_PrintLog(lvl, temp); \
free(temp); \
}
static inline void FILELOG_PrintLog(enum TLogLevel level, char* m) {
switch(level) {
case logERROR: cprintf(RED BOLD, "ERROR: %s", m); break;
case logWARNING: cprintf(YELLOW BOLD, "WARNING: %s", m); break;
case logINFOBLUE: cprintf(BLUE, "INFO: %s", m); break;
case logINFOGREEN: cprintf(GREEN, "INFO: %s", m); break;
case logINFORED: cprintf(RED, "INFO: %s", m); break;
case logINFO: cprintf(RESET, "INFO: %s", m); break;
case logDEBUG: cprintf(MAGENTA, "DEBUG: %s", m); break;
case logDEBUG1: cprintf(MAGENTA, "DEBUG1: %s", m); break;
case logDEBUG2: cprintf(MAGENTA, "DEBUG2: %s", m); break;
case logDEBUG3: cprintf(MAGENTA, "DEBUG3: %s", m); break;
case logDEBUG4: cprintf(MAGENTA, "DEBUG4: %s", m); break;
case logDEBUG5: cprintf(MAGENTA, "DEBUG5: %s", m); break;
static inline void FILELOG_PrintLog(enum TLogLevel level, char *m) {
switch (level) {
case logERROR:
cprintf(RED BOLD, "ERROR: %s", m);
break;
case logWARNING:
cprintf(YELLOW BOLD, "WARNING: %s", m);
break;
case logINFOBLUE:
cprintf(BLUE, "INFO: %s", m);
break;
case logINFOGREEN:
cprintf(GREEN, "INFO: %s", m);
break;
case logINFORED:
cprintf(RED, "INFO: %s", m);
break;
case logINFO:
cprintf(RESET, "INFO: %s", m);
break;
case logDEBUG:
cprintf(MAGENTA, "DEBUG: %s", m);
break;
case logDEBUG1:
cprintf(MAGENTA, "DEBUG1: %s", m);
break;
case logDEBUG2:
cprintf(MAGENTA, "DEBUG2: %s", m);
break;
case logDEBUG3:
cprintf(MAGENTA, "DEBUG3: %s", m);
break;
case logDEBUG4:
cprintf(MAGENTA, "DEBUG4: %s", m);
break;
case logDEBUG5:
cprintf(MAGENTA, "DEBUG5: %s", m);
break;
}
fflush(stdout);
}
static inline char* FILELOG_BuildLog(const char* fmt, ...) {
char* p;
static inline char *FILELOG_BuildLog(const char *fmt, ...) {
char *p;
va_list ap;
p = malloc(ERROR_MSG_LENGTH);
va_start(ap, fmt);
int ret = vsnprintf(p, ERROR_MSG_LENGTH, fmt, ap);
va_end(ap);
if (ret < 0 || ret >= ERROR_MSG_LENGTH) {
FILELOG_PrintLog(logERROR, ("Could not print the "
FILELOG_PrintLog(logERROR,
("Could not print the "
"complete error message in the next print.\n"));
}
return p;
};

7
slsDetectorServers/slsDetectorServer/include/common.h Executable file → Normal file
View File

@@ -1,7 +1,8 @@
#pragma once
/**
* Convert a value from a range to a different range (eg voltage to dac or vice versa)
* Convert a value from a range to a different range (eg voltage to dac or vice
* versa)
* @param inputMin input minimum
* @param inputMax input maximum
* @param outputMin output minimum
@@ -10,5 +11,5 @@
* @param outputValue pointer to output value
* @returns FAIL if input value is out of bounds, else OK
*/
int ConvertToDifferentRange(int inputMin, int inputMax, int outputMin, int outputMax,
int inputValue, int* outputValue);
int ConvertToDifferentRange(int inputMin, int inputMax, int outputMin,
int outputMax, int inputValue, int *outputValue);

21
slsDetectorServers/slsDetectorServer/include/commonServerFunctions.h Executable file → Normal file
View File

@@ -2,14 +2,23 @@
#include <inttypes.h>
void SPIChipSelect (uint32_t* valw, uint32_t addr, uint32_t csmask, uint32_t clkmask, uint32_t digoutmask, int convBit);
void SPIChipSelect(uint32_t *valw, uint32_t addr, uint32_t csmask,
uint32_t clkmask, uint32_t digoutmask, int convBit);
void SPIChipDeselect (uint32_t* valw, uint32_t addr, uint32_t csmask, uint32_t clkmask, uint32_t digoutmask, int convBit);
void SPIChipDeselect(uint32_t *valw, uint32_t addr, uint32_t csmask,
uint32_t clkmask, uint32_t digoutmask, int convBit);
void sendDataToSPI (uint32_t* valw, uint32_t addr, uint32_t val, int numbitstosend, uint32_t clkmask, uint32_t digoutmask, int digofset);
void sendDataToSPI(uint32_t *valw, uint32_t addr, uint32_t val,
int numbitstosend, uint32_t clkmask, uint32_t digoutmask,
int digofset);
uint32_t receiveDataFromSPI (uint32_t* valw, uint32_t addr, int numbitstoreceive, uint32_t clkmask, uint32_t readaddr) ;
uint32_t receiveDataFromSPI(uint32_t *valw, uint32_t addr, int numbitstoreceive,
uint32_t clkmask, uint32_t readaddr);
void serializeToSPI(uint32_t addr, uint32_t val, uint32_t csmask, int numbitstosend, uint32_t clkmask, uint32_t digoutmask, int digofset, int convBit);
void serializeToSPI(uint32_t addr, uint32_t val, uint32_t csmask,
int numbitstosend, uint32_t clkmask, uint32_t digoutmask,
int digofset, int convBit);
uint32_t serializeFromSPI(uint32_t addr, uint32_t csmask, int numbitstoreceive, uint32_t clkmask, uint32_t digoutmask, uint32_t readaddr, int convBit);
uint32_t serializeFromSPI(uint32_t addr, uint32_t csmask, int numbitstoreceive,
uint32_t clkmask, uint32_t digoutmask,
uint32_t readaddr, int convBit);

36
slsDetectorServers/slsDetectorServer/include/communication_funcs.h Executable file → Normal file
View File

@@ -1,15 +1,9 @@
#ifndef COMMUNICATION_FUNCS_H
#define COMMUNICATION_FUNCS_H
#include "sls_detector_defs.h"
typedef enum{
INT16,
INT32,
INT64,
OTHER
}intType;
typedef enum { INT16, INT32, INT64, OTHER } intType;
// communciate with stop server
#ifdef VIRTUAL
@@ -24,14 +18,14 @@ int acceptConnection(int socketDescriptor);
void closeConnection(int file_Des);
void exitServer(int socketDescriptor);
void swapData(void* val,int length,intType itype);
int sendData(int file_des, void* buf,int length, intType itype);
int receiveData(int file_des, void* buf,int length, intType itype);
int sendDataOnly(int file_des, void* buf,int length);
int receiveDataOnly(int file_des, void* buf,int length);
void swapData(void *val, int length, intType itype);
int sendData(int file_des, void *buf, int length, intType itype);
int receiveData(int file_des, void *buf, int length, intType itype);
int sendDataOnly(int file_des, void *buf, int length);
int receiveDataOnly(int file_des, void *buf, int length);
int sendModule(int file_des, sls_detector_module *myMod);
int receiveModule(int file_des, sls_detector_module* myMod);
int receiveModule(int file_des, sls_detector_module *myMod);
/**
* Servers sets and prints error message for locked server
@@ -39,7 +33,6 @@ int receiveModule(int file_des, sls_detector_module* myMod);
*/
void Server_LockedError();
/**
* Server verifies if it is unlocked,
* sets and prints appropriate message if it is locked and different clients
@@ -47,16 +40,17 @@ void Server_LockedError();
*/
int Server_VerifyLock();
/**
* Server sends result to client (also set ret to force_update if different clients)
* Server sends result to client (also set ret to force_update if different
* clients)
* @param fileDes file descriptor for the socket
* @param itype 32 or 64 or others to determine to swap data from big endian to little endian
* @param itype 32 or 64 or others to determine to swap data from big endian to
* little endian
* @param retval pointer to result
* @param retvalSize size of result
* @returns result of operation
*/
int Server_SendResult(int fileDes, intType itype, void* retval, int retvalSize);
int Server_SendResult(int fileDes, intType itype, void *retval, int retvalSize);
/**
* Convert mac address from integer to char array
@@ -64,20 +58,20 @@ int Server_SendResult(int fileDes, intType itype, void* retval, int retvalSize);
* @param size size of char array result
* @param mac mac address as an integer
*/
void getMacAddressinString(char* cmac, int size, uint64_t mac);
void getMacAddressinString(char *cmac, int size, uint64_t mac);
/**
* Convert ip address from integer to char array
* @param cip char arrary result
* @param ip ip address as an integer
*/
void getIpAddressinString(char* cip, uint32_t ip);
void getIpAddressinString(char *cip, uint32_t ip);
/**
* Convert string to ip address
* @param cip string source
* @param ip result
*/
void getIpAddressFromString(char* cip, uint32_t* ip);
void getIpAddressFromString(char *cip, uint32_t *ip);
#endif

5
slsDetectorServers/slsDetectorServer/include/communication_funcs_UDP.h Executable file → Normal file
View File

@@ -11,7 +11,8 @@ int getUdPSocketDescriptor(int index);
* @param ip udp destination ip
* @param port udp destination port
*/
int setUDPDestinationDetails(int index, const char* ip, unsigned short int port);
int setUDPDestinationDetails(int index, const char *ip,
unsigned short int port);
/**
* Create udp socket
@@ -25,7 +26,7 @@ int createUDPSocket(int index);
* @param buf pointer to memory to write
* @param length length of buffer to write to socket
*/
int sendUDPPacket(int index, const char* buf, int length);
int sendUDPPacket(int index, const char *buf, int length);
/**
* Close udp socket

6
slsDetectorServers/slsDetectorServer/include/communication_virtual.h Executable file → Normal file
View File

@@ -8,7 +8,9 @@ void ComVirtual_setStatus(int value);
int ComVirtual_getStatus();
void ComVirtual_setStop(int value);
int ComVirtual_getStop();
int ComVirtual_writeToFile(int value, const char* fname, const char* serverName);
int ComVirtual_readFromFile(int* value, const char* fname, const char* serverName);
int ComVirtual_writeToFile(int value, const char *fname,
const char *serverName);
int ComVirtual_readFromFile(int *value, const char *fname,
const char *serverName);
#endif

4
slsDetectorServers/slsDetectorServer/include/nios.h Executable file → Normal file
View File

@@ -1,7 +1,7 @@
#pragma once
#include <sys/types.h>
#include <inttypes.h>
#include <sys/types.h>
/**
* Write into a 32 bit register for cspbase 1
@@ -86,4 +86,4 @@ int mapCSP0(void);
/**
* Get Nios base address
*/
u_int32_t* Nios_getBaseAddress();
u_int32_t *Nios_getBaseAddress();

8
slsDetectorServers/slsDetectorServer/include/programFpgaBlackfin.h Executable file → Normal file
View File

@@ -1,7 +1,7 @@
#pragma once
#include <stdio.h>
#include <stdint.h>
#include <stdio.h>
/**
* Define GPIO pins if not defined
@@ -34,14 +34,14 @@ void eraseFlash();
* @param filefp pointer to flash
* @return 0 for success, 1 for fail (cannot open file for writing program)
*/
int startWritingFPGAprogram(FILE** filefp);
int startWritingFPGAprogram(FILE **filefp);
/**
* When done writing the program, close file pointer and
* notify FPGA to pick up the program from flash
* @param filefp pointer to flash
*/
void stopWritingFPGAprogram(FILE* filefp);
void stopWritingFPGAprogram(FILE *filefp);
/**
* Write FPGA Program to flash
@@ -50,4 +50,4 @@ void stopWritingFPGAprogram(FILE* filefp);
* @param filefp pointer to flash
* @return 0 for success, 1 for fail (cannot write)
*/
int writeFPGAProgram(char* fpgasrc, uint64_t fsize, FILE* filefp);
int writeFPGAProgram(char *fpgasrc, uint64_t fsize, FILE *filefp);

13
slsDetectorServers/slsDetectorServer/include/programFpgaNios.h Executable file → Normal file
View File

@@ -1,14 +1,15 @@
#pragma once
#include <stdio.h>
#include <stdint.h>
#include <stdio.h>
#define NIOS_MAX_APP_IMAGE_SIZE (0x00580000)
/** Notify microcontroller of successful server start up */
void NotifyServerStartSuccess();
/** create notification file to notify watchdog of critical tasks (to not shutdown) */
/** create notification file to notify watchdog of critical tasks (to not
* shutdown) */
void CreateNotificationForCriticalTasks();
/** write 1 to notification file to postpone shut down process if requested*/
@@ -23,8 +24,8 @@ void rebootControllerAndFPGA();
/** finds the right mtd drive
* @param mess error message
* @returns ok or fail
*/
int findFlash(char* mess);
*/
int findFlash(char *mess);
/** erase flash */
void eraseFlash();
@@ -35,7 +36,7 @@ void eraseFlash();
* @param fsize file size
* @returns ok or fail
*/
int eraseAndWriteToFlash(char* mess, char* fpgasrc, uint64_t fsize);
int eraseAndWriteToFlash(char *mess, char *fpgasrc, uint64_t fsize);
/**
* Write FPGA Program to flash
@@ -45,4 +46,4 @@ int eraseAndWriteToFlash(char* mess, char* fpgasrc, uint64_t fsize);
* @param filefp pointer to flash
* @return ok or fail
*/
int writeFPGAProgram(char* mess, char* fpgasrc, uint64_t fsize, FILE* filefp);
int writeFPGAProgram(char *mess, char *fpgasrc, uint64_t fsize, FILE *filefp);

22
slsDetectorServers/slsDetectorServer/include/readDefaultPattern.h Executable file → Normal file
View File

@@ -1,22 +1,24 @@
#pragma once
#include <sys/types.h>
#include <inttypes.h>
#include <sys/types.h>
int loadDefaultPattern(char* fname);
int loadDefaultPattern(char *fname);
int default_writePatternWord(char* line, uint32_t addr, uint64_t word);
int default_writePatternWord(char *line, uint32_t addr, uint64_t word);
int default_writePatternIOControl(char* line, uint64_t arg);
int default_writePatternIOControl(char *line, uint64_t arg);
int default_writePatternClkControl(char* line, uint64_t arg);
int default_writePatternClkControl(char *line, uint64_t arg);
int default_setPatternLoopLimits(char* line, uint32_t startAddr, uint32_t stopAddr);
int default_setPatternLoopLimits(char *line, uint32_t startAddr,
uint32_t stopAddr);
int default_setPatternLoopAddresses(char* line, int level, uint32_t startAddr, uint32_t stopAddr);
int default_setPatternLoopAddresses(char *line, int level, uint32_t startAddr,
uint32_t stopAddr);
int default_setPatternLoopCycles(char* line, int level, int numLoops);
int default_setPatternLoopCycles(char *line, int level, int numLoops);
int default_setPatternWaitAddresses(char* line, int level, uint32_t addr);
int default_setPatternWaitAddresses(char *line, int level, uint32_t addr);
int default_setPatternWaitTime(char* line, int level, uint64_t waittime);
int default_setPatternWaitTime(char *line, int level, uint64_t waittime);

130
slsDetectorServers/slsDetectorServer/include/slsDetectorFunctionList.h Executable file → Normal file
View File

@@ -1,10 +1,11 @@
#include "sls_detector_defs.h"
#include "slsDetectorServer_defs.h" // DAC_INDEX, ADC_INDEX, also include RegisterDefs.h
#include "sls_detector_defs.h"
#ifdef GOTTHARDD
#include "clogger.h" // runState(enum TLogLevel)
#include "AD9252.h" // old board compatibility
#include "clogger.h" // runState(enum TLogLevel)
#endif
#if defined(GOTTHARDD) || defined(JUNGFRAUD) || defined(CHIPTESTBOARDD) || defined(MOENCHD)
#if defined(GOTTHARDD) || defined(JUNGFRAUD) || defined(CHIPTESTBOARDD) || \
defined(MOENCHD)
#include "AD9257.h" // commonServerFunctions.h, blackfin.h, ansi.h
#endif
#ifdef MOENCHD
@@ -19,22 +20,23 @@
#if defined(MYTHEN3D) || defined(GOTTHARD2D)
#include "nios.h"
#elif defined(GOTTHARDD) || defined(JUNGFRAUD) || defined(CHIPTESTBOARDD) || defined(MOENCHD)
#elif defined(GOTTHARDD) || defined(JUNGFRAUD) || defined(CHIPTESTBOARDD) || \
defined(MOENCHD)
#include "blackfin.h"
#endif
#include <stdlib.h>
#include <stdio.h> // FILE
#include <stdlib.h>
#include <sys/types.h>
/****************************************************
This functions are used by the slsDetectroServer_funcs interface.
Here are the definitions, but the actual implementation should be done for each single detector.
Here are the definitions, but the actual implementation should be done for each
single detector.
****************************************************/
enum interfaceType {OUTER, INNER};
enum interfaceType { OUTER, INNER };
typedef struct udpStruct_s {
int srcport;
int srcport2;
@@ -48,20 +50,21 @@ typedef struct udpStruct_s {
uint32_t srcip2;
uint32_t dstip;
uint32_t dstip2;
}udpStruct;
} udpStruct;
// basic tests
int isInitCheckDone();
int getInitResult(char** mess);
int getInitResult(char **mess);
void basictests();
#if defined(GOTTHARDD) || defined(JUNGFRAUD) || defined(CHIPTESTBOARDD) || defined(MOENCHD) || defined(MYTHEN3D) || defined(GOTTHARD2D)
#if defined(GOTTHARDD) || defined(JUNGFRAUD) || defined(CHIPTESTBOARDD) || \
defined(MOENCHD) || defined(MYTHEN3D) || defined(GOTTHARD2D)
int checkType();
int testFpga();
int testBus();
#endif
#if defined(GOTTHARDD) || ((defined(EIGERD) || defined(JUNGFRAUD)) && defined(VIRTUAL))
#if defined(GOTTHARDD) || \
((defined(EIGERD) || defined(JUNGFRAUD)) && defined(VIRTUAL))
void setTestImageMode(int ival);
int getTestImageMode();
#endif
@@ -71,7 +74,8 @@ u_int64_t getServerVersion();
u_int64_t getClientServerAPIVersion();
u_int64_t getFirmwareVersion();
u_int64_t getFirmwareAPIVersion();
#if defined(JUNGFRAUD) || defined(CHIPTESTBOARDD) || defined(MOENCHD) || defined(MYTHEN3D) || defined(GOTTHARD2D)
#if defined(JUNGFRAUD) || defined(CHIPTESTBOARDD) || defined(MOENCHD) || \
defined(MYTHEN3D) || defined(GOTTHARD2D)
u_int16_t getHardwareVersionNumber();
#endif
#if defined(JUNGFRAUD) || defined(CHIPTESTBOARDD) || defined(MOENCHD)
@@ -87,7 +91,6 @@ u_int32_t getDetectorIP();
u_int32_t getBoardRevision();
#endif
// initialization
void initControlServer();
void initStopServer();
@@ -105,26 +108,28 @@ int updateDatabytesandAllocateRAM();
void updateDataBytes();
#endif
#if defined(GOTTHARDD) || defined(JUNGFRAUD) || defined(MYTHEN3D) || defined(MOENCHD)
#if defined(GOTTHARDD) || defined(JUNGFRAUD) || defined(MYTHEN3D) || \
defined(MOENCHD)
int setDefaultDacs();
#endif
#ifdef GOTTHARD2D
int readConfigFile();
#endif
// advanced read/write reg
#ifdef EIGERD
int writeRegister(uint32_t offset, uint32_t data);
int readRegister(uint32_t offset, uint32_t* retval);
int readRegister(uint32_t offset, uint32_t *retval);
#elif GOTTHARDD
uint32_t writeRegister16And32(uint32_t offset, uint32_t data); //FIXME its not there in ctb or moench?
uint32_t
writeRegister16And32(uint32_t offset,
uint32_t data); // FIXME its not there in ctb or moench?
uint32_t readRegister16And32(uint32_t offset);
#endif
// firmware functions (resets)
#if defined(JUNGFRAUD) || defined(CHIPTESTBOARDD) || defined(MOENCHD) || defined(MYTHEN3D) || defined(GOTTHARD2D)
#if defined(JUNGFRAUD) || defined(CHIPTESTBOARDD) || defined(MOENCHD) || \
defined(MYTHEN3D) || defined(GOTTHARD2D)
void cleanFifos();
void resetCore();
void resetPeripheral();
@@ -141,7 +146,6 @@ int readConfigFile();
void setMasterSlaveConfiguration();
#endif
// parameters - dr, roi
int setDynamicRange(int dr);
#ifdef GOTTHARDD
@@ -179,15 +183,13 @@ int setReadoutMode(enum readoutMode mode);
int getReadoutMode();
#endif
// parameters - timer
#ifdef JUNGFRAUD
int selectStoragecellStart(int pos);
#endif
#if defined(JUNGFRAUD) || defined(EIGERD)
int setStartingFrameNumber(uint64_t value);
int getStartingFrameNumber(uint64_t* value);
int getStartingFrameNumber(uint64_t *value);
#endif
void setNumFrames(int64_t val);
int64_t getNumFrames();
@@ -230,7 +232,8 @@ void setCounterMask(uint32_t arg);
uint32_t getCounterMask();
#endif
#if defined(JUNGFRAUD) || defined(GOTTHARDD) || defined(CHIPTESTBOARDD) || defined(MOENCHD) || defined(MYTHEN3D) || defined(GOTTHARD2D)
#if defined(JUNGFRAUD) || defined(GOTTHARDD) || defined(CHIPTESTBOARDD) || \
defined(MOENCHD) || defined(MYTHEN3D) || defined(GOTTHARD2D)
int setDelayAfterTrigger(int64_t val);
int64_t getDelayAfterTrigger();
int64_t getNumFramesLeft();
@@ -241,17 +244,17 @@ int64_t getPeriodLeft();
#ifdef GOTTHARDD
int64_t getExpTimeLeft();
#endif
#if defined(JUNGFRAUD) || defined(CHIPTESTBOARDD) || defined(MOENCHD) || defined(MYTHEN3D) || defined(GOTTHARD2D)
#if defined(JUNGFRAUD) || defined(CHIPTESTBOARDD) || defined(MOENCHD) || \
defined(MYTHEN3D) || defined(GOTTHARD2D)
int64_t getFramesFromStart();
int64_t getActualTime();
int64_t getMeasurementTime();
#endif
// parameters - module, settings
#if (!defined(CHIPTESTBOARDD)) && (!defined(MOENCHD)) && (!defined(MYTHEN3D)) && (!defined(GOTTHARD2D))
int setModule(sls_detector_module myMod, char* mess);
#if (!defined(CHIPTESTBOARDD)) && (!defined(MOENCHD)) && \
(!defined(MYTHEN3D)) && (!defined(GOTTHARD2D))
int setModule(sls_detector_module myMod, char *mess);
int getModule(sls_detector_module *myMod);
#endif
#if (!defined(CHIPTESTBOARDD)) && (!defined(MYTHEN3D))
@@ -303,10 +306,8 @@ int getADC(enum ADCINDEX ind);
int setHighVoltage(int val);
// parameters - timing, extsig
void setTiming( enum timingMode arg);
void setTiming(enum timingMode arg);
enum timingMode getTiming();
#ifdef GOTTHARDD
void setExtSignal(enum externalSignalFlag mode);
@@ -315,27 +316,27 @@ int getExtSignal();
// configure mac
#ifdef GOTTHARDD
void calcChecksum(mac_conf* mac, int sourceip, int destip);
void calcChecksum(mac_conf *mac, int sourceip, int destip);
#elif JUNGFRAUD
void setNumberofUDPInterfaces(int val);
int getNumberofUDPInterfaces();
void selectPrimaryInterface(int val);
int getPrimaryInterface();
void setupHeader(int iRxEntry, enum interfaceType type, uint32_t destip, uint64_t destmac, uint32_t destport, uint64_t sourcemac, uint32_t sourceip, uint32_t sourceport);
void setupHeader(int iRxEntry, enum interfaceType type, uint32_t destip,
uint64_t destmac, uint32_t destport, uint64_t sourcemac,
uint32_t sourceip, uint32_t sourceport);
#endif
#if defined(JUNGFRAUD) || defined(GOTTHARD2D) || defined(MYTHEN3D) || defined(CHIPTESTBOARDD) || defined(MOENCHD)
void calcChecksum(udp_header* udp);
#if defined(JUNGFRAUD) || defined(GOTTHARD2D) || defined(MYTHEN3D) || \
defined(CHIPTESTBOARDD) || defined(MOENCHD)
void calcChecksum(udp_header *udp);
#endif
#ifdef GOTTHARDD
int getAdcConfigured();
#endif
int configureMAC();
int setDetectorPosition(int pos[]);
int* getDetectorPosition();
int *getDetectorPosition();
#ifdef EIGERD
int setQuad(int value);
@@ -349,16 +350,16 @@ int getReadNLines();
int enableTenGigabitEthernet(int val);
#endif
// very detector specific
// moench specific - powerchip
#ifdef MOENCHD
int powerChip (int on);
int powerChip(int on);
int setAnalogOnlyReadout();
#endif
// chip test board or moench specific - configure frequency, phase, pll, flashing firmware
// chip test board or moench specific - configure frequency, phase, pll,
// flashing firmware
#if defined(CHIPTESTBOARDD) || defined(MOENCHD)
int setPhase(enum CLKINDEX ind, int val, int degrees);
int getPhase(enum CLKINDEX ind, int degrees);
@@ -387,10 +388,11 @@ void setPatternBitMask(uint64_t mask);
uint64_t getPatternBitMask();
#endif
// jungfrau specific - powerchip, autocompdisable, clockdiv, asictimer, clock, pll, flashing firmware
// jungfrau specific - powerchip, autocompdisable, clockdiv, asictimer, clock,
// pll, flashing firmware
#ifdef JUNGFRAUD
void initReadoutConfiguration();
int powerChip (int on);
int powerChip(int on);
int autoCompDisable(int on);
void configureASICTimer();
int setClockDivider(enum CLKINDEX ind, int val);
@@ -413,8 +415,8 @@ int setCounterBit(int val);
int pulsePixel(int n, int x, int y);
int pulsePixelNMove(int n, int x, int y);
int pulseChip(int n);
int updateRateCorrection(char* mess);
int validateAndSetRateCorrection(int64_t tau_ns, char* mess);
int updateRateCorrection(char *mess);
int validateAndSetRateCorrection(int64_t tau_ns, char *mess);
int setRateCorrection(int64_t custom_tau_in_nsec);
int getRateCorrectionEnable();
int getDefaultSettingsTau_in_nsec();
@@ -441,12 +443,12 @@ uint64_t getPatternMask();
void setPatternBitMask(uint64_t mask);
uint64_t getPatternBitMask();
int checkDetectorType();
int powerChip (int on);
int powerChip(int on);
int setPhase(enum CLKINDEX ind, int val, int degrees);
int getPhase(enum CLKINDEX ind, int degrees);
int getMaxPhase(enum CLKINDEX ind);
int validatePhaseinDegrees(enum CLKINDEX ind, int val, int retval);
//void setFrequency(enum CLKINDEX ind, int val);
// void setFrequency(enum CLKINDEX ind, int val);
int getFrequency(enum CLKINDEX ind);
int getVCOFrequency(enum CLKINDEX ind);
int getMaxClockDivider();
@@ -455,22 +457,22 @@ int getClockDivider(enum CLKINDEX ind);
#elif GOTTHARD2D
int checkDetectorType();
int powerChip (int on);
int powerChip(int on);
int setPhase(enum CLKINDEX ind, int val, int degrees);
int getPhase(enum CLKINDEX ind, int degrees);
int getMaxPhase(enum CLKINDEX ind);
int validatePhaseinDegrees(enum CLKINDEX ind, int val, int retval);
//void setFrequency(enum CLKINDEX ind, int val);
// void setFrequency(enum CLKINDEX ind, int val);
int getFrequency(enum CLKINDEX ind);
int getVCOFrequency(enum CLKINDEX ind);
int getMaxClockDivider();
int setClockDivider(enum CLKINDEX ind, int val);
int getClockDivider(enum CLKINDEX ind);
int setInjectChannel(int offset, int increment);
void getInjectedChannels(int* offset, int* increment);
void getInjectedChannels(int *offset, int *increment);
int setVetoReference(int gainIndex, int value);
int setVetoPhoton(int chipIndex, int gainIndex, int* values);
int getVetoPhoton(int chipIndex, int* retvals);
int setVetoPhoton(int chipIndex, int gainIndex, int *values);
int getVetoPhoton(int chipIndex, int *retvals);
int configureSingleADCDriver(int chipIndex);
int configureADC();
int setBurstModeinFPGA(enum burstMode value);
@@ -495,16 +497,13 @@ int getTransmissionDelayRight();
int setTransmissionDelayRight(int value);
#endif
// aquisition
#ifdef EIGERD
int prepareAcquisition();
#endif
int startStateMachine();
#ifdef VIRTUAL
void* start_timer(void* arg);
void *start_timer(void *arg);
#endif
int stopStateMachine();
#ifdef EIGERD
@@ -525,7 +524,8 @@ int checkFifoForEndOfAcquisition();
int readFrameFromFifo();
#endif
#if defined(GOTTHARDD) || defined(JUNGFRAUD) || defined(CHIPTESTBOARDD) || defined(MOENCHD) || defined(MYTHEN3D) || defined(GOTTHARD2D)
#if defined(GOTTHARDD) || defined(JUNGFRAUD) || defined(CHIPTESTBOARDD) || \
defined(MOENCHD) || defined(MYTHEN3D) || defined(GOTTHARD2D)
u_int32_t runBusy();
#endif
@@ -533,19 +533,15 @@ u_int32_t runBusy();
u_int32_t runState(enum TLogLevel lev);
#endif
//common
// common
#ifdef EIGERD
int copyModule(sls_detector_module *destMod, sls_detector_module *srcMod);
#endif
int calculateDataBytes();
int getTotalNumberOfChannels();
#if defined(MOENCHD) || defined(CHIPTESTBOARDD)
void getNumberOfChannels(int* nchanx, int* nchany);
void getNumberOfChannels(int *nchanx, int *nchany);
#endif
int getNumberOfChips();
int getNumberOfDACs();
int getNumberOfChannelsPerChip();

18
slsDetectorServers/slsDetectorServer/include/slsDetectorServer_funcs.h Executable file → Normal file
View File

@@ -1,8 +1,8 @@
#pragma once
#include "sls_detector_defs.h"
#include "clogger.h"
#include "sls_detector_defs.h"
enum numberMode {DEC, HEX};
enum numberMode { DEC, HEX };
#define GOODBYE (-200)
#define REBOOT (-400)
@@ -10,14 +10,15 @@ enum numberMode {DEC, HEX};
int printSocketReadError();
void init_detector();
int decode_function(int);
const char* getRetName();
const char* getFunctionName(enum detFuncs func);
const char *getRetName();
const char *getFunctionName(enum detFuncs func);
void function_table();
void functionNotImplemented();
void modeNotImplemented(char* modename, int mode);
void validate(int arg, int retval, char* modename, enum numberMode nummode);
void validate64(int64_t arg, int64_t retval, char* modename, enum numberMode nummode);
int executeCommand(char* command, char* result, enum TLogLevel level);
void modeNotImplemented(char *modename, int mode);
void validate(int arg, int retval, char *modename, enum numberMode nummode);
void validate64(int64_t arg, int64_t retval, char *modename,
enum numberMode nummode);
int executeCommand(char *command, char *result, enum TLogLevel level);
int M_nofunc(int);
#if defined(MYTHEN3D) || defined(GOTTHARD2D)
void rebootNiosControllerAndFPGA();
@@ -217,4 +218,3 @@ int set_timing_source(int);
int get_num_channels(int);
int update_rate_correction(int);
int get_receiver_parameters(int);

130
slsDetectorServers/slsDetectorServer/src/AD7689.c Executable file → Normal file
View File

@@ -1,9 +1,8 @@
#include "AD7689.h"
#include "commonServerFunctions.h" // blackfin.h, ansi.h
#include "common.h"
#include "blackfin.h"
#include "clogger.h"
#include "common.h"
#include "commonServerFunctions.h" // blackfin.h, ansi.h
/* AD7689 ADC DEFINES */
@@ -14,31 +13,45 @@
/** Channel sequencer */
#define AD7689_CFG_SEQ_OFST (1)
#define AD7689_CFG_SEQ_MSK (0x00000003 << AD7689_CFG_SEQ_OFST)
#define AD7689_CFG_SEQ_DSBLE_VAL ((0x0 << AD7689_CFG_SEQ_OFST) & AD7689_CFG_SEQ_MSK)
#define AD7689_CFG_SEQ_UPDTE_DRNG_SQNCE_VAL ((0x1 << AD7689_CFG_SEQ_OFST) & AD7689_CFG_SEQ_MSK)
#define AD7689_CFG_SEQ_SCN_WTH_TMP_VAL ((0x2 << AD7689_CFG_SEQ_OFST) & AD7689_CFG_SEQ_MSK)
#define AD7689_CFG_SEQ_SCN_WTHT_TMP_VAL ((0x3 << AD7689_CFG_SEQ_OFST) & AD7689_CFG_SEQ_MSK)
#define AD7689_CFG_SEQ_DSBLE_VAL \
((0x0 << AD7689_CFG_SEQ_OFST) & AD7689_CFG_SEQ_MSK)
#define AD7689_CFG_SEQ_UPDTE_DRNG_SQNCE_VAL \
((0x1 << AD7689_CFG_SEQ_OFST) & AD7689_CFG_SEQ_MSK)
#define AD7689_CFG_SEQ_SCN_WTH_TMP_VAL \
((0x2 << AD7689_CFG_SEQ_OFST) & AD7689_CFG_SEQ_MSK)
#define AD7689_CFG_SEQ_SCN_WTHT_TMP_VAL \
((0x3 << AD7689_CFG_SEQ_OFST) & AD7689_CFG_SEQ_MSK)
/** Reference/ buffer selection */
#define AD7689_CFG_REF_OFST (3)
#define AD7689_CFG_REF_MSK (0x00000007 << AD7689_CFG_REF_OFST)
/** Internal reference. REF = 2.5V buffered output. Temperature sensor enabled. */
#define AD7689_CFG_REF_INT_2500MV_VAL ((0x0 << AD7689_CFG_REF_OFST) & AD7689_CFG_REF_OFST)
/** Internal reference. REF = 4.096V buffered output. Temperature sensor enabled. */
#define AD7689_CFG_REF_INT_4096MV_VAL ((0x1 << AD7689_CFG_REF_OFST) & AD7689_CFG_REF_MSK)
/** Internal reference. REF = 2.5V buffered output. Temperature sensor enabled.
*/
#define AD7689_CFG_REF_INT_2500MV_VAL \
((0x0 << AD7689_CFG_REF_OFST) & AD7689_CFG_REF_OFST)
/** Internal reference. REF = 4.096V buffered output. Temperature sensor
* enabled. */
#define AD7689_CFG_REF_INT_4096MV_VAL \
((0x1 << AD7689_CFG_REF_OFST) & AD7689_CFG_REF_MSK)
/** External reference. Temperature sensor enabled. Internal buffer disabled. */
#define AD7689_CFG_REF_EXT_TMP_VAL ((0x2 << AD7689_CFG_REF_OFST) & AD7689_CFG_REF_MSK)
#define AD7689_CFG_REF_EXT_TMP_VAL \
((0x2 << AD7689_CFG_REF_OFST) & AD7689_CFG_REF_MSK)
/** External reference. Temperature sensor enabled. Internal buffer enabled. */
#define AD7689_CFG_REF_EXT_TMP_INTBUF_VAL ((0x3 << AD7689_CFG_REF_OFST) & AD7689_CFG_REF_MSK)
/** External reference. Temperature sensor disabled. Internal buffer disabled. */
#define AD7689_CFG_REF_EXT_VAL ((0x6 << AD7689_CFG_REF_OFST) & AD7689_CFG_REF_MSK)
#define AD7689_CFG_REF_EXT_TMP_INTBUF_VAL \
((0x3 << AD7689_CFG_REF_OFST) & AD7689_CFG_REF_MSK)
/** External reference. Temperature sensor disabled. Internal buffer disabled.
*/
#define AD7689_CFG_REF_EXT_VAL \
((0x6 << AD7689_CFG_REF_OFST) & AD7689_CFG_REF_MSK)
/** External reference. Temperature sensor disabled. Internal buffer enabled. */
#define AD7689_CFG_REF_EXT_INTBUF_VAL ((0x7 << AD7689_CFG_REF_OFST) & AD7689_CFG_REF_MSK)
#define AD7689_CFG_REF_EXT_INTBUF_VAL \
((0x7 << AD7689_CFG_REF_OFST) & AD7689_CFG_REF_MSK)
/** bandwidth of low pass filter */
#define AD7689_CFG_BW_OFST (6)
#define AD7689_CFG_BW_MSK (0x00000001 << AD7689_CFG_REF_OFST)
#define AD7689_CFG_BW_ONE_FOURTH_VAL ((0x0 << AD7689_CFG_BW_OFST) & AD7689_CFG_BW_MSK)
#define AD7689_CFG_BW_ONE_FOURTH_VAL \
((0x0 << AD7689_CFG_BW_OFST) & AD7689_CFG_BW_MSK)
#define AD7689_CFG_BW_FULL_VAL ((0x1 << AD7689_CFG_BW_OFST) & AD7689_CFG_BW_MSK)
/** input channel selection IN0 - IN7 */
@@ -48,25 +61,34 @@
/** input channel configuration */
#define AD7689_CFG_INCC_OFST (10)
#define AD7689_CFG_INCC_MSK (0x00000007 << AD7689_CFG_INCC_OFST)
#define AD7689_CFG_INCC_BPLR_DFFRNTL_PRS_VAL ((0x0 << AD7689_CFG_INCC_OFST) & AD7689_CFG_INCC_MSK)
#define AD7689_CFG_INCC_BPLR_IN_COM_VAL ((0x2 << AD7689_CFG_INCC_OFST) & AD7689_CFG_INCC_MSK)
#define AD7689_CFG_INCC_TMP_VAL ((0x3 << AD7689_CFG_INCC_OFST) & AD7689_CFG_INCC_MSK)
#define AD7689_CFG_INCC_UNPLR_DFFRNTL_PRS_VAL ((0x4 << AD7689_CFG_INCC_OFST) & AD7689_CFG_INCC_MSK)
#define AD7689_CFG_INCC_UNPLR_IN_COM_VAL ((0x6 << AD7689_CFG_INCC_OFST) & AD7689_CFG_INCC_MSK)
#define AD7689_CFG_INCC_UNPLR_IN_GND_VAL ((0x7 << AD7689_CFG_INCC_OFST) & AD7689_CFG_INCC_MSK)
#define AD7689_CFG_INCC_BPLR_DFFRNTL_PRS_VAL \
((0x0 << AD7689_CFG_INCC_OFST) & AD7689_CFG_INCC_MSK)
#define AD7689_CFG_INCC_BPLR_IN_COM_VAL \
((0x2 << AD7689_CFG_INCC_OFST) & AD7689_CFG_INCC_MSK)
#define AD7689_CFG_INCC_TMP_VAL \
((0x3 << AD7689_CFG_INCC_OFST) & AD7689_CFG_INCC_MSK)
#define AD7689_CFG_INCC_UNPLR_DFFRNTL_PRS_VAL \
((0x4 << AD7689_CFG_INCC_OFST) & AD7689_CFG_INCC_MSK)
#define AD7689_CFG_INCC_UNPLR_IN_COM_VAL \
((0x6 << AD7689_CFG_INCC_OFST) & AD7689_CFG_INCC_MSK)
#define AD7689_CFG_INCC_UNPLR_IN_GND_VAL \
((0x7 << AD7689_CFG_INCC_OFST) & AD7689_CFG_INCC_MSK)
/** configuration update */
#define AD7689_CFG_CFG_OFST (13)
#define AD7689_CFG_CFG_MSK (0x00000001 << AD7689_CFG_CFG_OFST)
#define AD7689_CFG_CFG_NO_UPDATE_VAL ((0x0 << AD7689_CFG_CFG_OFST) & AD7689_CFG_CFG_MSK)
#define AD7689_CFG_CFG_OVRWRTE_VAL ((0x1 << AD7689_CFG_CFG_OFST) & AD7689_CFG_CFG_MSK)
#define AD7689_CFG_CFG_NO_UPDATE_VAL \
((0x0 << AD7689_CFG_CFG_OFST) & AD7689_CFG_CFG_MSK)
#define AD7689_CFG_CFG_OVRWRTE_VAL \
((0x1 << AD7689_CFG_CFG_OFST) & AD7689_CFG_CFG_MSK)
#define AD7689_ADC_CFG_NUMBITS (14)
#define AD7689_ADC_DATA_NUMBITS (16)
#define AD7689_NUM_CHANNELS (8)
#define AD7689_NUM_INVALID_CONVERSIONS (3)
#define AD7689_INT_REF_MAX_MV (2500) // chosen using reference buffer selection in config reg
#define AD7689_INT_REF_MAX_MV \
(2500) // chosen using reference buffer selection in config reg
#define AD7689_INT_REF_MIN_MV (0)
#define AD7689_INT_REF_MAX_UV (2500 * 1000)
#define AD7689_INT_REF_MIN_UV (0)
@@ -81,8 +103,10 @@ uint32_t AD7689_ClkMask = 0x0;
uint32_t AD7689_DigMask = 0x0;
int AD7689_DigOffset = 0x0;
void AD7689_SetDefines(uint32_t reg, uint32_t roreg, uint32_t cmsk, uint32_t clkmsk, uint32_t dmsk, int dofst) {
LOG(logDEBUG, ("AD7689: reg:0x%x roreg:0x%x cmsk:0x%x clkmsk:0x%x dmsk:0x%x dofst:%d\n",
void AD7689_SetDefines(uint32_t reg, uint32_t roreg, uint32_t cmsk,
uint32_t clkmsk, uint32_t dmsk, int dofst) {
LOG(logDEBUG, ("AD7689: reg:0x%x roreg:0x%x cmsk:0x%x clkmsk:0x%x "
"dmsk:0x%x dofst:%d\n",
reg, roreg, cmsk, clkmsk, dmsk, dofst));
AD7689_Reg = reg;
AD7689_ROReg = roreg;
@@ -93,22 +117,22 @@ void AD7689_SetDefines(uint32_t reg, uint32_t roreg, uint32_t cmsk, uint32_t clk
}
void AD7689_Disable() {
bus_w(AD7689_Reg, (bus_r(AD7689_Reg)
&~(AD7689_CnvMask)
&~AD7689_ClkMask
&~(AD7689_DigMask)));
bus_w(AD7689_Reg, (bus_r(AD7689_Reg) & ~(AD7689_CnvMask) & ~AD7689_ClkMask &
~(AD7689_DigMask)));
}
void AD7689_Set(uint32_t codata) {
LOG(logINFO, ("\tSetting ADC SPI Register. Writing 0x%08x to Config Reg\n", codata));
LOG(logINFO,
("\tSetting ADC SPI Register. Writing 0x%08x to Config Reg\n", codata));
serializeToSPI(AD7689_Reg, codata, AD7689_CnvMask, AD7689_ADC_CFG_NUMBITS,
AD7689_ClkMask, AD7689_DigMask, AD7689_DigOffset, 1);
}
uint16_t AD7689_Get() {
LOG(logINFO, ("\tGetting ADC SPI Register.\n"));
return (uint16_t)serializeFromSPI(AD7689_Reg, AD7689_CnvMask, AD7689_ADC_DATA_NUMBITS,
AD7689_ClkMask, AD7689_DigMask, AD7689_ROReg, 1);
return (uint16_t)serializeFromSPI(AD7689_Reg, AD7689_CnvMask,
AD7689_ADC_DATA_NUMBITS, AD7689_ClkMask,
AD7689_DigMask, AD7689_ROReg, 1);
}
int AD7689_GetTemperature() {
@@ -117,7 +141,8 @@ int AD7689_GetTemperature() {
AD7689_CFG_RB_MSK |
// disable sequencer (different from config)
AD7689_CFG_SEQ_DSBLE_VAL |
// Internal reference. REF = 2.5V buffered output. Temperature sensor enabled.
// Internal reference. REF = 2.5V buffered output. Temperature sensor
// enabled.
AD7689_CFG_REF_INT_2500MV_VAL |
// full bandwidth of low pass filter
AD7689_CFG_BW_FULL_VAL |
@@ -130,11 +155,11 @@ int AD7689_GetTemperature() {
int regval = AD7689_Get();
// value in mV FIXME: page 17? reference voltage temperature coefficient or t do with -40 to 85 °C
// value in mV FIXME: page 17? reference voltage temperature coefficient or
// t do with -40 to 85 °C
int retval = 0;
ConvertToDifferentRange(0, AD7689_INT_MAX_STEPS,
AD7689_INT_REF_MIN_MV, AD7689_INT_REF_MAX_MV,
regval, &retval);
ConvertToDifferentRange(0, AD7689_INT_MAX_STEPS, AD7689_INT_REF_MIN_MV,
AD7689_INT_REF_MAX_MV, regval, &retval);
LOG(logDEBUG1, ("voltage read for temp: %d mV\n", retval));
// value in °C
@@ -142,14 +167,14 @@ int AD7689_GetTemperature() {
LOG(logINFO, ("\ttemp read : %f °C (%d unit)\n", tempValue, regval));
return tempValue;
}
int AD7689_GetChannel(int ichan) {
// filter channels val
if (ichan < 0 || ichan >= AD7689_NUM_CHANNELS) {
LOG(logERROR, ("Cannot get slow adc channel. "
"%d out of bounds (0 to %d)\n", ichan, AD7689_NUM_CHANNELS - 1));
"%d out of bounds (0 to %d)\n",
ichan, AD7689_NUM_CHANNELS - 1));
return -1;
}
@@ -158,7 +183,8 @@ int AD7689_GetChannel(int ichan) {
AD7689_CFG_RB_MSK |
// disable sequencer (different from config)
AD7689_CFG_SEQ_DSBLE_VAL |
// Internal reference. REF = 2.5V buffered output. Temperature sensor enabled.
// Internal reference. REF = 2.5V buffered output. Temperature sensor
// enabled.
AD7689_CFG_REF_INT_2500MV_VAL |
// full bandwidth of low pass filter
AD7689_CFG_BW_FULL_VAL |
@@ -172,22 +198,27 @@ int AD7689_GetChannel(int ichan) {
int regval = AD7689_Get();
// value in uV
int retval = ((double)(regval - 0) * (double)(AD7689_INT_REF_MAX_UV - AD7689_INT_REF_MIN_UV))
/ (double)(AD7689_INT_MAX_STEPS - 0) + AD7689_INT_REF_MIN_UV;
int retval = ((double)(regval - 0) *
(double)(AD7689_INT_REF_MAX_UV - AD7689_INT_REF_MIN_UV)) /
(double)(AD7689_INT_MAX_STEPS - 0) +
AD7689_INT_REF_MIN_UV;
/*ConvertToDifferentRange(0, AD7689_INT_MAX_STEPS,
AD7689_INT_REF_MIN_MV, AD7689_INT_REF_MAX_MV,
regval, &retval);*/
LOG(logINFO, ("\tvoltage read for chan %d: %d uV (regVal: %d)\n", ichan, retval, regval));
LOG(logINFO, ("\tvoltage read for chan %d: %d uV (regVal: %d)\n", ichan,
retval, regval));
return retval;
}
void AD7689_Configure(){
void AD7689_Configure() {
LOG(logINFOBLUE, ("Configuring AD7689 (Slow ADCs): \n"));
// from power up, 3 invalid conversions
LOG(logINFO, ("\tConfiguring %d x due to invalid conversions from power up\n", AD7689_NUM_INVALID_CONVERSIONS));
LOG(logINFO,
("\tConfiguring %d x due to invalid conversions from power up\n",
AD7689_NUM_INVALID_CONVERSIONS));
int i = 0;
for (i = 0; i < AD7689_NUM_INVALID_CONVERSIONS; ++i) {
AD7689_Set(
@@ -195,7 +226,8 @@ void AD7689_Configure(){
AD7689_CFG_RB_MSK |
// scan sequence IN0-IN7 then temperature sensor
AD7689_CFG_SEQ_SCN_WTH_TMP_VAL |
// Internal reference. REF = 2.5V buffered output. Temperature sensor enabled.
// Internal reference. REF = 2.5V buffered output. Temperature
// sensor enabled.
AD7689_CFG_REF_INT_2500MV_VAL |
// full bandwidth of low pass filter
AD7689_CFG_BW_FULL_VAL |

134
slsDetectorServers/slsDetectorServer/src/AD9252.c Executable file → Normal file
View File

@@ -1,7 +1,7 @@
#include "AD9252.h"
#include "commonServerFunctions.h" // blackfin.h, ansi.h
#include "blackfin.h"
#include "clogger.h"
#include "commonServerFunctions.h" // blackfin.h, ansi.h
/* AD9252 ADC DEFINES */
#define AD9252_ADC_NUMBITS (24)
@@ -36,67 +36,99 @@
#define AD9252_POWER_MODE_REG (0x08)
#define AD9252_POWER_INTERNAL_OFST (0)
#define AD9252_POWER_INTERNAL_MSK (0x00000007 << AD9252_POWER_INTERNAL_OFST)
#define AD9252_INT_CHIP_RUN_VAL ((0x0 << AD9252_POWER_INTERNAL_OFST) & AD9252_POWER_INTERNAL_MSK)
#define AD9252_INT_FULL_PWR_DWN_VAL ((0x1 << AD9252_POWER_INTERNAL_OFST) & AD9252_POWER_INTERNAL_MSK)
#define AD9252_INT_STANDBY_VAL ((0x2 << AD9252_POWER_INTERNAL_OFST) & AD9252_POWER_INTERNAL_MSK)
#define AD9252_INT_RESET_VAL ((0x3 << AD9252_POWER_INTERNAL_OFST) & AD9252_POWER_INTERNAL_MSK)
#define AD9252_INT_CHIP_RUN_VAL \
((0x0 << AD9252_POWER_INTERNAL_OFST) & AD9252_POWER_INTERNAL_MSK)
#define AD9252_INT_FULL_PWR_DWN_VAL \
((0x1 << AD9252_POWER_INTERNAL_OFST) & AD9252_POWER_INTERNAL_MSK)
#define AD9252_INT_STANDBY_VAL \
((0x2 << AD9252_POWER_INTERNAL_OFST) & AD9252_POWER_INTERNAL_MSK)
#define AD9252_INT_RESET_VAL \
((0x3 << AD9252_POWER_INTERNAL_OFST) & AD9252_POWER_INTERNAL_MSK)
// default value is 0x0
#define AD9252_TEST_MODE_REG (0x0D)
#define AD9252_OUT_TEST_OFST (0)
#define AD9252_OUT_TEST_MSK (0x0000000F << AD9252_OUT_TEST_OFST)
#define AD9252_TST_OFF_VAL ((0x0 << AD9252_OUT_TEST_OFST) & AD9252_OUT_TEST_MSK)
#define AD9252_TST_MDSCL_SHRT_VAL ((0x1 << AD9252_OUT_TEST_OFST) & AD9252_OUT_TEST_MSK)
#define AD9252_TST_PSTV_FS_VAL ((0x2 << AD9252_OUT_TEST_OFST) & AD9252_OUT_TEST_MSK)
#define AD9252_TST_NGTV_FS_VAL ((0x3 << AD9252_OUT_TEST_OFST) & AD9252_OUT_TEST_MSK)
#define AD9252_TST_ALTRNTNG_CHKRBRD_VAL ((0x4 << AD9252_OUT_TEST_OFST) & AD9252_OUT_TEST_MSK)
#define AD9252_TST_PN_23_SQNC_VAL ((0x5 << AD9252_OUT_TEST_OFST) & AD9252_OUT_TEST_MSK)
#define AD9252_TST_PN_9_SQNC__VAL ((0x6 << AD9252_OUT_TEST_OFST) & AD9252_OUT_TEST_MSK)
#define AD9252_TST_1_0_WRD_TGGL_VAL ((0x7 << AD9252_OUT_TEST_OFST) & AD9252_OUT_TEST_MSK)
#define AD9252_TST_USR_INPT_VAL ((0x8 << AD9252_OUT_TEST_OFST) & AD9252_OUT_TEST_MSK)
#define AD9252_TST_1_0_BT_TGGL_VAL ((0x9 << AD9252_OUT_TEST_OFST) & AD9252_OUT_TEST_MSK)
#define AD9252_TST_1_x_SYNC_VAL ((0xa << AD9252_OUT_TEST_OFST) & AD9252_OUT_TEST_MSK)
#define AD9252_TST_1_BIT_HGH_VAL ((0xb << AD9252_OUT_TEST_OFST) & AD9252_OUT_TEST_MSK)
#define AD9252_TST_MXD_BT_FRQ_VAL ((0xc << AD9252_OUT_TEST_OFST) & AD9252_OUT_TEST_MSK)
#define AD9252_TST_MDSCL_SHRT_VAL \
((0x1 << AD9252_OUT_TEST_OFST) & AD9252_OUT_TEST_MSK)
#define AD9252_TST_PSTV_FS_VAL \
((0x2 << AD9252_OUT_TEST_OFST) & AD9252_OUT_TEST_MSK)
#define AD9252_TST_NGTV_FS_VAL \
((0x3 << AD9252_OUT_TEST_OFST) & AD9252_OUT_TEST_MSK)
#define AD9252_TST_ALTRNTNG_CHKRBRD_VAL \
((0x4 << AD9252_OUT_TEST_OFST) & AD9252_OUT_TEST_MSK)
#define AD9252_TST_PN_23_SQNC_VAL \
((0x5 << AD9252_OUT_TEST_OFST) & AD9252_OUT_TEST_MSK)
#define AD9252_TST_PN_9_SQNC__VAL \
((0x6 << AD9252_OUT_TEST_OFST) & AD9252_OUT_TEST_MSK)
#define AD9252_TST_1_0_WRD_TGGL_VAL \
((0x7 << AD9252_OUT_TEST_OFST) & AD9252_OUT_TEST_MSK)
#define AD9252_TST_USR_INPT_VAL \
((0x8 << AD9252_OUT_TEST_OFST) & AD9252_OUT_TEST_MSK)
#define AD9252_TST_1_0_BT_TGGL_VAL \
((0x9 << AD9252_OUT_TEST_OFST) & AD9252_OUT_TEST_MSK)
#define AD9252_TST_1_x_SYNC_VAL \
((0xa << AD9252_OUT_TEST_OFST) & AD9252_OUT_TEST_MSK)
#define AD9252_TST_1_BIT_HGH_VAL \
((0xb << AD9252_OUT_TEST_OFST) & AD9252_OUT_TEST_MSK)
#define AD9252_TST_MXD_BT_FRQ_VAL \
((0xc << AD9252_OUT_TEST_OFST) & AD9252_OUT_TEST_MSK)
#define AD9252_TST_RST_SHRT_GN_OFST (4)
#define AD9252_TST_RST_SHRT_GN_MSK (0x00000001 << AD9252_TST_RST_SHRT_GN_OFST)
#define AD9252_TST_RST_LNG_GN_OFST (5)
#define AD9252_TST_RST_LNG_GN_MSK (0x00000001 << AD9252_TST_RST_LNG_GN_OFST)
#define AD9252_USER_IN_MODE_OFST (6)
#define AD9252_USER_IN_MODE_MSK (0x00000003 << AD9252_USER_IN_MODE_OFST)
#define AD9252_USR_IN_SNGL_VAL ((0x0 << AD9252_USER_IN_MODE_OFST) & AD9252_USER_IN_MODE_MSK)
#define AD9252_USR_IN_ALTRNT_VAL ((0x1 << AD9252_USER_IN_MODE_OFST) & AD9252_USER_IN_MODE_MSK)
#define AD9252_USR_IN_SNGL_ONC_VAL ((0x2 << AD9252_USER_IN_MODE_OFST) & AD9252_USER_IN_MODE_MSK)
#define AD9252_USR_IN_ALTRNT_ONC_VAL ((0x3 << AD9252_USER_IN_MODE_OFST) & AD9252_USER_IN_MODE_MSK)
#define AD9252_USR_IN_SNGL_VAL \
((0x0 << AD9252_USER_IN_MODE_OFST) & AD9252_USER_IN_MODE_MSK)
#define AD9252_USR_IN_ALTRNT_VAL \
((0x1 << AD9252_USER_IN_MODE_OFST) & AD9252_USER_IN_MODE_MSK)
#define AD9252_USR_IN_SNGL_ONC_VAL \
((0x2 << AD9252_USER_IN_MODE_OFST) & AD9252_USER_IN_MODE_MSK)
#define AD9252_USR_IN_ALTRNT_ONC_VAL \
((0x3 << AD9252_USER_IN_MODE_OFST) & AD9252_USER_IN_MODE_MSK)
// default value is 0x00
#define AD9252_OUT_MODE_REG (0x14)
#define AD9252_OUT_FORMAT_OFST (0)
#define AD9252_OUT_FORMAT_MSK (0x00000003 << AD9252_OUT_FORMAT_OFST)
#define AD9252_OUT_BINARY_OFST_VAL ((0x0 << AD9252_OUT_FORMAT_OFST) & AD9252_OUT_FORMAT_MSK)
#define AD9252_OUT_TWOS_COMPL_VAL ((0x1 << AD9252_OUT_FORMAT_OFST) & AD9252_OUT_FORMAT_MSK)
#define AD9252_OUT_BINARY_OFST_VAL \
((0x0 << AD9252_OUT_FORMAT_OFST) & AD9252_OUT_FORMAT_MSK)
#define AD9252_OUT_TWOS_COMPL_VAL \
((0x1 << AD9252_OUT_FORMAT_OFST) & AD9252_OUT_FORMAT_MSK)
#define AD9252_OUT_OTPT_INVRT_OFST (2)
#define AD9252_OUT_OTPT_INVRT_MSK (0x00000001 << AD9252_OUT_OTPT_INVRT_OFST)
#define AD9252_OUT_LVDS_OPT_OFST (6)
#define AD9252_OUT_LVDS_OPT_MSK (0x00000001 << AD9252_OUT_LVDS_OPT_OFST)
#define AD9252_OUT_LVDS_ANSI_VAL ((0x0 << AD9252_OUT_LVDS_OPT_OFST) & AD9252_OUT_LVDS_OPT_MSK)
#define AD9252_OUT_LVDS_IEEE_VAL ((0x1 << AD9252_OUT_LVDS_OPT_OFST) & AD9252_OUT_LVDS_OPT_MSK)
#define AD9252_OUT_LVDS_ANSI_VAL \
((0x0 << AD9252_OUT_LVDS_OPT_OFST) & AD9252_OUT_LVDS_OPT_MSK)
#define AD9252_OUT_LVDS_IEEE_VAL \
((0x1 << AD9252_OUT_LVDS_OPT_OFST) & AD9252_OUT_LVDS_OPT_MSK)
// default value is 0x3
#define AD9252_OUT_PHASE_REG (0x16)
#define AD9252_OUT_CLK_OFST (0)
#define AD9252_OUT_CLK_MSK (0x0000000F << AD9252_OUT_CLK_OFST)
#define AD9252_OUT_CLK_0_VAL ((0x0 << AD9252_OUT_CLK_OFST) & AD9252_OUT_CLK_MSK)
#define AD9252_OUT_CLK_60_VAL ((0x1 << AD9252_OUT_CLK_OFST) & AD9252_OUT_CLK_MSK)
#define AD9252_OUT_CLK_120_VAL ((0x2 << AD9252_OUT_CLK_OFST) & AD9252_OUT_CLK_MSK)
#define AD9252_OUT_CLK_180_VAL ((0x3 << AD9252_OUT_CLK_OFST) & AD9252_OUT_CLK_MSK)
#define AD9252_OUT_CLK_300_VAL ((0x5 << AD9252_OUT_CLK_OFST) & AD9252_OUT_CLK_MSK)
#define AD9252_OUT_CLK_360_VAL ((0x6 << AD9252_OUT_CLK_OFST) & AD9252_OUT_CLK_MSK)
#define AD9252_OUT_CLK_480_VAL ((0x8 << AD9252_OUT_CLK_OFST) & AD9252_OUT_CLK_MSK)
#define AD9252_OUT_CLK_540_VAL ((0x9 << AD9252_OUT_CLK_OFST) & AD9252_OUT_CLK_MSK)
#define AD9252_OUT_CLK_600_VAL ((0xa << AD9252_OUT_CLK_OFST) & AD9252_OUT_CLK_MSK)
#define AD9252_OUT_CLK_660_VAL ((0xb << AD9252_OUT_CLK_OFST) & AD9252_OUT_CLK_MSK) // 0xb - 0xf is 660
#define AD9252_OUT_CLK_60_VAL \
((0x1 << AD9252_OUT_CLK_OFST) & AD9252_OUT_CLK_MSK)
#define AD9252_OUT_CLK_120_VAL \
((0x2 << AD9252_OUT_CLK_OFST) & AD9252_OUT_CLK_MSK)
#define AD9252_OUT_CLK_180_VAL \
((0x3 << AD9252_OUT_CLK_OFST) & AD9252_OUT_CLK_MSK)
#define AD9252_OUT_CLK_300_VAL \
((0x5 << AD9252_OUT_CLK_OFST) & AD9252_OUT_CLK_MSK)
#define AD9252_OUT_CLK_360_VAL \
((0x6 << AD9252_OUT_CLK_OFST) & AD9252_OUT_CLK_MSK)
#define AD9252_OUT_CLK_480_VAL \
((0x8 << AD9252_OUT_CLK_OFST) & AD9252_OUT_CLK_MSK)
#define AD9252_OUT_CLK_540_VAL \
((0x9 << AD9252_OUT_CLK_OFST) & AD9252_OUT_CLK_MSK)
#define AD9252_OUT_CLK_600_VAL \
((0xa << AD9252_OUT_CLK_OFST) & AD9252_OUT_CLK_MSK)
#define AD9252_OUT_CLK_660_VAL \
((0xb << AD9252_OUT_CLK_OFST) & AD9252_OUT_CLK_MSK) // 0xb - 0xf is 660
// defines from the fpga
uint32_t AD9252_Reg = 0x0;
@@ -105,7 +137,8 @@ uint32_t AD9252_ClkMask = 0x0;
uint32_t AD9252_DigMask = 0x0;
int AD9252_DigOffset = 0x0;
void AD9252_SetDefines(uint32_t reg, uint32_t cmsk, uint32_t clkmsk, uint32_t dmsk, int dofst) {
void AD9252_SetDefines(uint32_t reg, uint32_t cmsk, uint32_t clkmsk,
uint32_t dmsk, int dofst) {
AD9252_Reg = reg;
AD9252_CsMask = cmsk;
AD9252_ClkMask = clkmsk;
@@ -114,29 +147,28 @@ void AD9252_SetDefines(uint32_t reg, uint32_t cmsk, uint32_t clkmsk, uint32_t dm
}
void AD9252_Disable() {
bus_w(AD9252_Reg, (bus_r(AD9252_Reg)
| AD9252_CsMask
| AD9252_ClkMask)
&~(AD9252_DigMask));
bus_w(AD9252_Reg, (bus_r(AD9252_Reg) | AD9252_CsMask | AD9252_ClkMask) &
~(AD9252_DigMask));
}
void AD9252_Set(int addr, int val) {
u_int32_t codata;
codata = val + (addr << 8);
LOG(logINFO, ("\tSetting ADC SPI Register. Wrote 0x%04x at 0x%04x\n", val, addr));
LOG(logINFO,
("\tSetting ADC SPI Register. Wrote 0x%04x at 0x%04x\n", val, addr));
serializeToSPI(AD9252_Reg, codata, AD9252_CsMask, AD9252_ADC_NUMBITS,
AD9252_ClkMask, AD9252_DigMask, AD9252_DigOffset, 0);
}
void AD9252_Configure(){
void AD9252_Configure() {
LOG(logINFOBLUE, ("Configuring ADC9252:\n"));
//power mode reset
// power mode reset
LOG(logINFO, ("\tPower mode reset\n"));
AD9252_Set(AD9252_POWER_MODE_REG, AD9252_INT_RESET_VAL);
//power mode chip run
// power mode chip run
LOG(logINFO, ("\tPower mode chip run\n"));
AD9252_Set(AD9252_POWER_MODE_REG, AD9252_INT_CHIP_RUN_VAL);
@@ -144,7 +176,7 @@ void AD9252_Configure(){
LOG(logINFO, ("\tBinary offset\n"));
AD9252_Set(AD9252_OUT_MODE_REG, AD9252_OUT_BINARY_OFST_VAL);
//output clock phase
// output clock phase
#ifdef GOTTHARDD
LOG(logINFO, ("\tOutput clock phase is at default: 180\n"));
#else
@@ -158,11 +190,12 @@ void AD9252_Configure(){
// all devices on chip to receive next command
LOG(logINFO, ("\tAll devices on chip to receive next command\n"));
AD9252_Set(AD9252_DEV_IND_2_REG,
AD9252_CHAN_H_MSK | AD9252_CHAN_G_MSK | AD9252_CHAN_F_MSK | AD9252_CHAN_E_MSK);
AD9252_Set(AD9252_DEV_IND_1_REG,
AD9252_CHAN_D_MSK | AD9252_CHAN_C_MSK | AD9252_CHAN_B_MSK | AD9252_CHAN_A_MSK |
AD9252_CLK_CH_DCO_MSK | AD9252_CLK_CH_IFCO_MSK);
AD9252_Set(AD9252_DEV_IND_2_REG, AD9252_CHAN_H_MSK | AD9252_CHAN_G_MSK |
AD9252_CHAN_F_MSK | AD9252_CHAN_E_MSK);
AD9252_Set(AD9252_DEV_IND_1_REG, AD9252_CHAN_D_MSK | AD9252_CHAN_C_MSK |
AD9252_CHAN_B_MSK | AD9252_CHAN_A_MSK |
AD9252_CLK_CH_DCO_MSK |
AD9252_CLK_CH_IFCO_MSK);
// no test mode
LOG(logINFO, ("\tNo test mode\n"));
@@ -175,4 +208,3 @@ void AD9252_Configure(){
AD9252_Set(AD9252_TEST_MODE_REG, AD9252_TST_MXD_BT_FRQ_VAL);
#endif
}

153
slsDetectorServers/slsDetectorServer/src/AD9257.c Executable file → Normal file
View File

@@ -1,7 +1,7 @@
#include "AD9257.h"
#include "commonServerFunctions.h" // blackfin.h, ansi.h
#include "blackfin.h"
#include "clogger.h"
#include "commonServerFunctions.h" // blackfin.h, ansi.h
#include "sls_detector_defs.h"
/* AD9257 ADC DEFINES */
@@ -37,72 +37,109 @@
#define AD9257_POWER_MODE_REG (0x08)
#define AD9257_POWER_INTERNAL_OFST (0)
#define AD9257_POWER_INTERNAL_MSK (0x00000003 << AD9257_POWER_INTERNAL_OFST)
#define AD9257_INT_CHIP_RUN_VAL ((0x0 << AD9257_POWER_INTERNAL_OFST) & AD9257_POWER_INTERNAL_MSK)
#define AD9257_INT_FULL_PWR_DWN_VAL ((0x1 << AD9257_POWER_INTERNAL_OFST) & AD9257_POWER_INTERNAL_MSK)
#define AD9257_INT_STANDBY_VAL ((0x2 << AD9257_POWER_INTERNAL_OFST) & AD9257_POWER_INTERNAL_MSK)
#define AD9257_INT_RESET_VAL ((0x3 << AD9257_POWER_INTERNAL_OFST) & AD9257_POWER_INTERNAL_MSK)
#define AD9257_INT_CHIP_RUN_VAL \
((0x0 << AD9257_POWER_INTERNAL_OFST) & AD9257_POWER_INTERNAL_MSK)
#define AD9257_INT_FULL_PWR_DWN_VAL \
((0x1 << AD9257_POWER_INTERNAL_OFST) & AD9257_POWER_INTERNAL_MSK)
#define AD9257_INT_STANDBY_VAL \
((0x2 << AD9257_POWER_INTERNAL_OFST) & AD9257_POWER_INTERNAL_MSK)
#define AD9257_INT_RESET_VAL \
((0x3 << AD9257_POWER_INTERNAL_OFST) & AD9257_POWER_INTERNAL_MSK)
#define AD9257_POWER_EXTERNAL_OFST (5)
#define AD9257_POWER_EXTERNAL_MSK (0x00000001 << AD9257_POWER_EXTERNAL_OFST)
#define AD9257_EXT_FULL_POWER_VAL ((0x0 << AD9257_POWER_EXTERNAL_OFST) & AD9257_POWER_EXTERNAL_MSK)
#define AD9257_EXT_STANDBY_VAL ((0x1 << AD9257_POWER_EXTERNAL_OFST) & AD9257_POWER_EXTERNAL_MSK)
#define AD9257_EXT_FULL_POWER_VAL \
((0x0 << AD9257_POWER_EXTERNAL_OFST) & AD9257_POWER_EXTERNAL_MSK)
#define AD9257_EXT_STANDBY_VAL \
((0x1 << AD9257_POWER_EXTERNAL_OFST) & AD9257_POWER_EXTERNAL_MSK)
// default value is 0x0
#define AD9257_TEST_MODE_REG (0x0D)
#define AD9257_OUT_TEST_OFST (0)
#define AD9257_OUT_TEST_MSK (0x0000000F << AD9257_OUT_TEST_OFST)
#define AD9257_TST_OFF_VAL ((0x0 << AD9257_OUT_TEST_OFST) & AD9257_OUT_TEST_MSK)
#define AD9257_TST_MDSCL_SHRT_VAL ((0x1 << AD9257_OUT_TEST_OFST) & AD9257_OUT_TEST_MSK)
#define AD9257_TST_PSTV_FS_VAL ((0x2 << AD9257_OUT_TEST_OFST) & AD9257_OUT_TEST_MSK)
#define AD9257_TST_NGTV_FS_VAL ((0x3 << AD9257_OUT_TEST_OFST) & AD9257_OUT_TEST_MSK)
#define AD9257_TST_ALTRNTNG_CHKRBRD_VAL ((0x4 << AD9257_OUT_TEST_OFST) & AD9257_OUT_TEST_MSK)
#define AD9257_TST_PN_23_SQNC_VAL ((0x5 << AD9257_OUT_TEST_OFST) & AD9257_OUT_TEST_MSK)
#define AD9257_TST_PN_9_SQNC__VAL ((0x6 << AD9257_OUT_TEST_OFST) & AD9257_OUT_TEST_MSK)
#define AD9257_TST_1_0_WRD_TGGL_VAL ((0x7 << AD9257_OUT_TEST_OFST) & AD9257_OUT_TEST_MSK)
#define AD9257_TST_USR_INPT_VAL ((0x8 << AD9257_OUT_TEST_OFST) & AD9257_OUT_TEST_MSK)
#define AD9257_TST_1_0_BT_TGGL_VAL ((0x9 << AD9257_OUT_TEST_OFST) & AD9257_OUT_TEST_MSK)
#define AD9257_TST_1_x_SYNC_VAL ((0xa << AD9257_OUT_TEST_OFST) & AD9257_OUT_TEST_MSK)
#define AD9257_TST_1_BIT_HGH_VAL ((0xb << AD9257_OUT_TEST_OFST) & AD9257_OUT_TEST_MSK)
#define AD9257_TST_MXD_BT_FRQ_VAL ((0xc << AD9257_OUT_TEST_OFST) & AD9257_OUT_TEST_MSK)
#define AD9257_TST_MDSCL_SHRT_VAL \
((0x1 << AD9257_OUT_TEST_OFST) & AD9257_OUT_TEST_MSK)
#define AD9257_TST_PSTV_FS_VAL \
((0x2 << AD9257_OUT_TEST_OFST) & AD9257_OUT_TEST_MSK)
#define AD9257_TST_NGTV_FS_VAL \
((0x3 << AD9257_OUT_TEST_OFST) & AD9257_OUT_TEST_MSK)
#define AD9257_TST_ALTRNTNG_CHKRBRD_VAL \
((0x4 << AD9257_OUT_TEST_OFST) & AD9257_OUT_TEST_MSK)
#define AD9257_TST_PN_23_SQNC_VAL \
((0x5 << AD9257_OUT_TEST_OFST) & AD9257_OUT_TEST_MSK)
#define AD9257_TST_PN_9_SQNC__VAL \
((0x6 << AD9257_OUT_TEST_OFST) & AD9257_OUT_TEST_MSK)
#define AD9257_TST_1_0_WRD_TGGL_VAL \
((0x7 << AD9257_OUT_TEST_OFST) & AD9257_OUT_TEST_MSK)
#define AD9257_TST_USR_INPT_VAL \
((0x8 << AD9257_OUT_TEST_OFST) & AD9257_OUT_TEST_MSK)
#define AD9257_TST_1_0_BT_TGGL_VAL \
((0x9 << AD9257_OUT_TEST_OFST) & AD9257_OUT_TEST_MSK)
#define AD9257_TST_1_x_SYNC_VAL \
((0xa << AD9257_OUT_TEST_OFST) & AD9257_OUT_TEST_MSK)
#define AD9257_TST_1_BIT_HGH_VAL \
((0xb << AD9257_OUT_TEST_OFST) & AD9257_OUT_TEST_MSK)
#define AD9257_TST_MXD_BT_FRQ_VAL \
((0xc << AD9257_OUT_TEST_OFST) & AD9257_OUT_TEST_MSK)
#define AD9257_TST_RST_SHRT_GN_OFST (4)
#define AD9257_TST_RST_SHRT_GN_MSK (0x00000001 << AD9257_TST_RST_SHRT_GN_OFST)
#define AD9257_TST_RST_LNG_GN_OFST (5)
#define AD9257_TST_RST_LNG_GN_MSK (0x00000001 << AD9257_TST_RST_LNG_GN_OFST)
#define AD9257_USER_IN_MODE_OFST (6)
#define AD9257_USER_IN_MODE_MSK (0x00000003 << AD9257_USER_IN_MODE_OFST)
#define AD9257_USR_IN_SNGL_VAL ((0x0 << AD9257_USER_IN_MODE_OFST) & AD9257_USER_IN_MODE_MSK)
#define AD9257_USR_IN_ALTRNT_VAL ((0x1 << AD9257_USER_IN_MODE_OFST) & AD9257_USER_IN_MODE_MSK)
#define AD9257_USR_IN_SNGL_ONC_VAL ((0x2 << AD9257_USER_IN_MODE_OFST) & AD9257_USER_IN_MODE_MSK)
#define AD9257_USR_IN_ALTRNT_ONC_VAL ((0x3 << AD9257_USER_IN_MODE_OFST) & AD9257_USER_IN_MODE_MSK)
#define AD9257_USR_IN_SNGL_VAL \
((0x0 << AD9257_USER_IN_MODE_OFST) & AD9257_USER_IN_MODE_MSK)
#define AD9257_USR_IN_ALTRNT_VAL \
((0x1 << AD9257_USER_IN_MODE_OFST) & AD9257_USER_IN_MODE_MSK)
#define AD9257_USR_IN_SNGL_ONC_VAL \
((0x2 << AD9257_USER_IN_MODE_OFST) & AD9257_USER_IN_MODE_MSK)
#define AD9257_USR_IN_ALTRNT_ONC_VAL \
((0x3 << AD9257_USER_IN_MODE_OFST) & AD9257_USER_IN_MODE_MSK)
// default value is 0x01
#define AD9257_OUT_MODE_REG (0x14)
#define AD9257_OUT_FORMAT_OFST (0)
#define AD9257_OUT_FORMAT_MSK (0x00000001 << AD9257_OUT_FORMAT_OFST)
#define AD9257_OUT_BINARY_OFST_VAL ((0x0 << AD9257_OUT_FORMAT_OFST) & AD9257_OUT_FORMAT_MSK)
#define AD9257_OUT_TWOS_COMPL_VAL ((0x1 << AD9257_OUT_FORMAT_OFST) & AD9257_OUT_FORMAT_MSK)
#define AD9257_OUT_BINARY_OFST_VAL \
((0x0 << AD9257_OUT_FORMAT_OFST) & AD9257_OUT_FORMAT_MSK)
#define AD9257_OUT_TWOS_COMPL_VAL \
((0x1 << AD9257_OUT_FORMAT_OFST) & AD9257_OUT_FORMAT_MSK)
#define AD9257_OUT_OTPT_INVRT_OFST (2)
#define AD9257_OUT_OTPT_INVRT_MSK (0x00000001 << AD9257_OUT_OTPT_INVRT_OFST)
#define AD9257_OUT_LVDS_OPT_OFST (6)
#define AD9257_OUT_LVDS_OPT_MSK (0x00000001 << AD9257_OUT_LVDS_OPT_OFST)
#define AD9257_OUT_LVDS_ANSI_VAL ((0x0 << AD9257_OUT_LVDS_OPT_OFST) & AD9257_OUT_LVDS_OPT_MSK)
#define AD9257_OUT_LVDS_IEEE_VAL ((0x1 << AD9257_OUT_LVDS_OPT_OFST) & AD9257_OUT_LVDS_OPT_MSK)
#define AD9257_OUT_LVDS_ANSI_VAL \
((0x0 << AD9257_OUT_LVDS_OPT_OFST) & AD9257_OUT_LVDS_OPT_MSK)
#define AD9257_OUT_LVDS_IEEE_VAL \
((0x1 << AD9257_OUT_LVDS_OPT_OFST) & AD9257_OUT_LVDS_OPT_MSK)
// default value is 0x3
#define AD9257_OUT_PHASE_REG (0x16)
#define AD9257_OUT_CLK_OFST (0)
#define AD9257_OUT_CLK_MSK (0x0000000F << AD9257_OUT_CLK_OFST)
#define AD9257_OUT_CLK_0_VAL ((0x0 << AD9257_OUT_CLK_OFST) & AD9257_OUT_CLK_MSK)
#define AD9257_OUT_CLK_60_VAL ((0x1 << AD9257_OUT_CLK_OFST) & AD9257_OUT_CLK_MSK)
#define AD9257_OUT_CLK_120_VAL ((0x2 << AD9257_OUT_CLK_OFST) & AD9257_OUT_CLK_MSK)
#define AD9257_OUT_CLK_180_VAL ((0x3 << AD9257_OUT_CLK_OFST) & AD9257_OUT_CLK_MSK)
#define AD9257_OUT_CLK_240_VAL ((0x4 << AD9257_OUT_CLK_OFST) & AD9257_OUT_CLK_MSK)
#define AD9257_OUT_CLK_300_VAL ((0x5 << AD9257_OUT_CLK_OFST) & AD9257_OUT_CLK_MSK)
#define AD9257_OUT_CLK_360_VAL ((0x6 << AD9257_OUT_CLK_OFST) & AD9257_OUT_CLK_MSK)
#define AD9257_OUT_CLK_420_VAL ((0x7 << AD9257_OUT_CLK_OFST) & AD9257_OUT_CLK_MSK)
#define AD9257_OUT_CLK_480_VAL ((0x8 << AD9257_OUT_CLK_OFST) & AD9257_OUT_CLK_MSK)
#define AD9257_OUT_CLK_540_VAL ((0x9 << AD9257_OUT_CLK_OFST) & AD9257_OUT_CLK_MSK)
#define AD9257_OUT_CLK_600_VAL ((0xa << AD9257_OUT_CLK_OFST) & AD9257_OUT_CLK_MSK)
#define AD9257_OUT_CLK_660_VAL ((0xb << AD9257_OUT_CLK_OFST) & AD9257_OUT_CLK_MSK)
#define AD9257_OUT_CLK_60_VAL \
((0x1 << AD9257_OUT_CLK_OFST) & AD9257_OUT_CLK_MSK)
#define AD9257_OUT_CLK_120_VAL \
((0x2 << AD9257_OUT_CLK_OFST) & AD9257_OUT_CLK_MSK)
#define AD9257_OUT_CLK_180_VAL \
((0x3 << AD9257_OUT_CLK_OFST) & AD9257_OUT_CLK_MSK)
#define AD9257_OUT_CLK_240_VAL \
((0x4 << AD9257_OUT_CLK_OFST) & AD9257_OUT_CLK_MSK)
#define AD9257_OUT_CLK_300_VAL \
((0x5 << AD9257_OUT_CLK_OFST) & AD9257_OUT_CLK_MSK)
#define AD9257_OUT_CLK_360_VAL \
((0x6 << AD9257_OUT_CLK_OFST) & AD9257_OUT_CLK_MSK)
#define AD9257_OUT_CLK_420_VAL \
((0x7 << AD9257_OUT_CLK_OFST) & AD9257_OUT_CLK_MSK)
#define AD9257_OUT_CLK_480_VAL \
((0x8 << AD9257_OUT_CLK_OFST) & AD9257_OUT_CLK_MSK)
#define AD9257_OUT_CLK_540_VAL \
((0x9 << AD9257_OUT_CLK_OFST) & AD9257_OUT_CLK_MSK)
#define AD9257_OUT_CLK_600_VAL \
((0xa << AD9257_OUT_CLK_OFST) & AD9257_OUT_CLK_MSK)
#define AD9257_OUT_CLK_660_VAL \
((0xb << AD9257_OUT_CLK_OFST) & AD9257_OUT_CLK_MSK)
#define AD9257_IN_CLK_OFST (4)
#define AD9257_IN_CLK_MSK (0x00000007 << AD9257_IN_CLK_OFST)
#define AD9257_IN_CLK_0_VAL ((0x0 << AD9257_IN_CLK_OFST) & AD9257_IN_CLK_MSK)
@@ -133,7 +170,8 @@ uint32_t AD9257_DigMask = 0x0;
int AD9257_DigOffset = 0x0;
int AD9257_VrefVoltage = 0;
void AD9257_SetDefines(uint32_t reg, uint32_t cmsk, uint32_t clkmsk, uint32_t dmsk, int dofst) {
void AD9257_SetDefines(uint32_t reg, uint32_t cmsk, uint32_t clkmsk,
uint32_t dmsk, int dofst) {
AD9257_Reg = reg;
AD9257_CsMask = cmsk;
AD9257_ClkMask = clkmsk;
@@ -142,16 +180,14 @@ void AD9257_SetDefines(uint32_t reg, uint32_t cmsk, uint32_t clkmsk, uint32_t dm
}
void AD9257_Disable() {
bus_w(AD9257_Reg, (bus_r(AD9257_Reg)
| AD9257_CsMask
| AD9257_ClkMask)
& ~(AD9257_DigMask));
bus_w(AD9257_Reg, (bus_r(AD9257_Reg) | AD9257_CsMask | AD9257_ClkMask) &
~(AD9257_DigMask));
}
int AD9257_GetVrefVoltage(int mV) {
if (mV == 0)
return AD9257_VrefVoltage;
switch(AD9257_VrefVoltage) {
switch (AD9257_VrefVoltage) {
case 0:
return 1000;
case 1:
@@ -172,7 +208,7 @@ int AD9257_SetVrefVoltage(int val, int mV) {
int mode = val;
// convert to mode
if (mV) {
switch(val) {
switch (val) {
case 1000:
mode = 0;
break;
@@ -196,7 +232,7 @@ int AD9257_SetVrefVoltage(int val, int mV) {
}
// validation for mode
switch(mode) {
switch (mode) {
case 0:
LOG(logINFO, ("Setting ADC Vref to 1.0 V (Mode:%d)\n", mode));
break;
@@ -225,38 +261,41 @@ void AD9257_Set(int addr, int val) {
u_int32_t codata;
codata = val + (addr << 8);
LOG(logINFO, ("\tSetting ADC SPI Register. Wrote 0x%04x at 0x%04x\n", val, addr));
LOG(logINFO,
("\tSetting ADC SPI Register. Wrote 0x%04x at 0x%04x\n", val, addr));
serializeToSPI(AD9257_Reg, codata, AD9257_CsMask, AD9257_ADC_NUMBITS,
AD9257_ClkMask, AD9257_DigMask, AD9257_DigOffset, 0);
}
void AD9257_Configure(){
void AD9257_Configure() {
LOG(logINFOBLUE, ("Configuring ADC9257:\n"));
//power mode reset
// power mode reset
LOG(logINFO, ("\tPower mode reset\n"));
AD9257_Set(AD9257_POWER_MODE_REG, AD9257_INT_RESET_VAL);
//power mode chip run
// power mode chip run
LOG(logINFO, ("\tPower mode chip run\n"));
AD9257_Set(AD9257_POWER_MODE_REG, AD9257_INT_CHIP_RUN_VAL);
// binary offset, lvds-iee reduced
LOG(logINFO, ("\tBinary offset, Lvds-ieee reduced\n"));
AD9257_Set(AD9257_OUT_MODE_REG, AD9257_OUT_BINARY_OFST_VAL | AD9257_OUT_LVDS_IEEE_VAL);
AD9257_Set(AD9257_OUT_MODE_REG,
AD9257_OUT_BINARY_OFST_VAL | AD9257_OUT_LVDS_IEEE_VAL);
//output clock phase
// output clock phase
LOG(logINFO, ("\tOutput clock phase: 180\n"));
AD9257_Set(AD9257_OUT_PHASE_REG, AD9257_OUT_CLK_180_VAL);
// all devices on chip to receive next command
LOG(logINFO, ("\tAll devices on chip to receive next command\n"));
AD9257_Set(AD9257_DEV_IND_2_REG,
AD9257_CHAN_H_MSK | AD9257_CHAN_G_MSK | AD9257_CHAN_F_MSK | AD9257_CHAN_E_MSK);
AD9257_Set(AD9257_DEV_IND_2_REG, AD9257_CHAN_H_MSK | AD9257_CHAN_G_MSK |
AD9257_CHAN_F_MSK | AD9257_CHAN_E_MSK);
AD9257_Set(AD9257_DEV_IND_1_REG,
AD9257_CHAN_D_MSK | AD9257_CHAN_C_MSK | AD9257_CHAN_B_MSK | AD9257_CHAN_A_MSK |
AD9257_CLK_CH_DCO_MSK | AD9257_CLK_CH_IFCO_MSK);
AD9257_Set(AD9257_DEV_IND_1_REG, AD9257_CHAN_D_MSK | AD9257_CHAN_C_MSK |
AD9257_CHAN_B_MSK | AD9257_CHAN_A_MSK |
AD9257_CLK_CH_DCO_MSK |
AD9257_CLK_CH_IFCO_MSK);
// vref
#ifdef GOTTHARDD

220
slsDetectorServers/slsDetectorServer/src/ALTERA_PLL.c Executable file → Normal file
View File

@@ -1,13 +1,13 @@
#include "ALTERA_PLL.h"
#include "clogger.h"
#include "blackfin.h"
#include "clogger.h"
#include <unistd.h> // usleep
/* Altera PLL DEFINES */
/** PLL Reconfiguration Registers */
//https://www.altera.com/documentation/mcn1424769382940.html
// https://www.altera.com/documentation/mcn1424769382940.html
#define ALTERA_PLL_MODE_REG (0x00)
#define ALTERA_PLL_MODE_WT_RQUST_VAL (0)
@@ -20,49 +20,97 @@
#define ALTERA_PLL_C_COUNTER_REG (0x05)
#define ALTERA_PLL_C_COUNTER_LW_CNT_OFST (0)
#define ALTERA_PLL_C_COUNTER_LW_CNT_MSK (0x000000FF << ALTERA_PLL_C_COUNTER_LW_CNT_OFST)
#define ALTERA_PLL_C_COUNTER_LW_CNT_MSK \
(0x000000FF << ALTERA_PLL_C_COUNTER_LW_CNT_OFST)
#define ALTERA_PLL_C_COUNTER_HGH_CNT_OFST (8)
#define ALTERA_PLL_C_COUNTER_HGH_CNT_MSK (0x000000FF << ALTERA_PLL_C_COUNTER_HGH_CNT_OFST)
#define ALTERA_PLL_C_COUNTER_HGH_CNT_MSK \
(0x000000FF << ALTERA_PLL_C_COUNTER_HGH_CNT_OFST)
/* total_div = lw_cnt + hgh_cnt */
#define ALTERA_PLL_C_COUNTER_BYPSS_ENBL_OFST (16)
#define ALTERA_PLL_C_COUNTER_BYPSS_ENBL_MSK (0x00000001 << ALTERA_PLL_C_COUNTER_BYPSS_ENBL_OFST)
/* if bypss_enbl = 0, fout = f(vco)/total_div; else fout = f(vco) (c counter is bypassed) */
#define ALTERA_PLL_C_COUNTER_BYPSS_ENBL_MSK \
(0x00000001 << ALTERA_PLL_C_COUNTER_BYPSS_ENBL_OFST)
/* if bypss_enbl = 0, fout = f(vco)/total_div; else fout = f(vco) (c counter is
* bypassed) */
#define ALTERA_PLL_C_COUNTER_ODD_DVSN_OFST (17)
#define ALTERA_PLL_C_COUNTER_ODD_DVSN_MSK (0x00000001 << ALTERA_PLL_C_COUNTER_ODD_DVSN_OFST)
/** if odd_dvsn = 0 (even), duty cycle = hgh_cnt/ total_div; else duty cycle = (hgh_cnt - 0.5) / total_div */
#define ALTERA_PLL_C_COUNTER_ODD_DVSN_MSK \
(0x00000001 << ALTERA_PLL_C_COUNTER_ODD_DVSN_OFST)
/** if odd_dvsn = 0 (even), duty cycle = hgh_cnt/ total_div; else duty cycle =
* (hgh_cnt - 0.5) / total_div */
#define ALTERA_PLL_C_COUNTER_SLCT_OFST (18)
#define ALTERA_PLL_C_COUNTER_SLCT_MSK (0x0000001F << ALTERA_PLL_C_COUNTER_SLCT_OFST)
#define ALTERA_PLL_C_COUNTER_SLCT_MSK \
(0x0000001F << ALTERA_PLL_C_COUNTER_SLCT_OFST)
#define ALTERA_PLL_PHASE_SHIFT_REG (0x06)
#define ALTERA_PLL_SHIFT_NUM_SHIFTS_OFST (0)
#define ALTERA_PLL_SHIFT_NUM_SHIFTS_MSK (0x0000FFFF << ALTERA_PLL_SHIFT_NUM_SHIFTS_OFST)
#define ALTERA_PLL_SHIFT_NUM_SHIFTS_MSK \
(0x0000FFFF << ALTERA_PLL_SHIFT_NUM_SHIFTS_OFST)
#define ALTERA_PLL_SHIFT_CNT_SELECT_OFST (16)
#define ALTERA_PLL_SHIFT_CNT_SELECT_MSK (0x0000001F << ALTERA_PLL_SHIFT_CNT_SELECT_OFST)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C0_VAL ((0x0 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C1_VAL ((0x1 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C2_VAL ((0x2 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C3_VAL ((0x3 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C4_VAL ((0x4 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C5_VAL ((0x5 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C6_VAL ((0x6 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C7_VAL ((0x7 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C8_VAL ((0x8 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C9_VAL ((0x9 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C10_VAL ((0x10 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C11_VAL ((0x11 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C12_VAL ((0x12 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C13_VAL ((0x13 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C14_VAL ((0x14 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C15_VAL ((0x15 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C16_VAL ((0x16 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C17_VAL ((0x17 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SELECT_MSK \
(0x0000001F << ALTERA_PLL_SHIFT_CNT_SELECT_OFST)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C0_VAL \
((0x0 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & \
ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C1_VAL \
((0x1 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & \
ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C2_VAL \
((0x2 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & \
ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C3_VAL \
((0x3 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & \
ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C4_VAL \
((0x4 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & \
ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C5_VAL \
((0x5 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & \
ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C6_VAL \
((0x6 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & \
ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C7_VAL \
((0x7 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & \
ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C8_VAL \
((0x8 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & \
ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C9_VAL \
((0x9 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & \
ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C10_VAL \
((0x10 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & \
ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C11_VAL \
((0x11 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & \
ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C12_VAL \
((0x12 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & \
ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C13_VAL \
((0x13 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & \
ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C14_VAL \
((0x14 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & \
ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C15_VAL \
((0x15 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & \
ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C16_VAL \
((0x16 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & \
ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C17_VAL \
((0x17 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & \
ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_UP_DOWN_OFST (21)
#define ALTERA_PLL_SHIFT_UP_DOWN_MSK (0x00000001 << ALTERA_PLL_SHIFT_UP_DOWN_OFST)
#define ALTERA_PLL_SHIFT_UP_DOWN_NEG_VAL ((0x0 << ALTERA_PLL_SHIFT_UP_DOWN_OFST) & ALTERA_PLL_SHIFT_UP_DOWN_MSK)
#define ALTERA_PLL_SHIFT_UP_DOWN_POS_VAL ((0x1 << ALTERA_PLL_SHIFT_UP_DOWN_OFST) & ALTERA_PLL_SHIFT_UP_DOWN_MSK)
#define ALTERA_PLL_SHIFT_UP_DOWN_MSK \
(0x00000001 << ALTERA_PLL_SHIFT_UP_DOWN_OFST)
#define ALTERA_PLL_SHIFT_UP_DOWN_NEG_VAL \
((0x0 << ALTERA_PLL_SHIFT_UP_DOWN_OFST) & ALTERA_PLL_SHIFT_UP_DOWN_MSK)
#define ALTERA_PLL_SHIFT_UP_DOWN_POS_VAL \
((0x1 << ALTERA_PLL_SHIFT_UP_DOWN_OFST) & ALTERA_PLL_SHIFT_UP_DOWN_MSK)
#define ALTERA_PLL_K_COUNTER_REG (0x07)
#define ALTERA_PLL_BANDWIDTH_REG (0x08)
@@ -70,10 +118,8 @@
#define ALTERA_PLL_VCO_DIV_REG (0x1c)
#define ALTERA_PLL_MIF_REG (0x1f)
#define ALTERA_PLL_WAIT_TIME_US (10 * 1000)
// defines from the fpga
uint32_t ALTERA_PLL_Cntrl_Reg = 0x0;
uint32_t ALTERA_PLL_Param_Reg = 0x0;
@@ -89,7 +135,9 @@ uint32_t ALTERA_PLL_Cntrl_AddrMask = 0x0;
int ALTERA_PLL_Cntrl_AddrOfst = 0;
#ifdef JUNGFRAUD
void ALTERA_PLL_SetDefines(uint32_t creg, uint32_t preg, uint32_t rprmsk, uint32_t wpmsk, uint32_t prmsk, uint32_t amsk, int aofst, uint32_t wd2msk, int clk2Index) {
void ALTERA_PLL_SetDefines(uint32_t creg, uint32_t preg, uint32_t rprmsk,
uint32_t wpmsk, uint32_t prmsk, uint32_t amsk,
int aofst, uint32_t wd2msk, int clk2Index) {
ALTERA_PLL_Cntrl_Reg = creg;
ALTERA_PLL_Param_Reg = preg;
ALTERA_PLL_Cntrl_RcnfgPrmtrRstMask = rprmsk;
@@ -101,7 +149,9 @@ void ALTERA_PLL_SetDefines(uint32_t creg, uint32_t preg, uint32_t rprmsk, uint32
ALTERA_PLL_Cntrl_DBIT_ClkIndex = clk2Index;
}
#else
void ALTERA_PLL_SetDefines(uint32_t creg, uint32_t preg, uint32_t rprmsk, uint32_t wpmsk, uint32_t prmsk, uint32_t amsk, int aofst) {
void ALTERA_PLL_SetDefines(uint32_t creg, uint32_t preg, uint32_t rprmsk,
uint32_t wpmsk, uint32_t prmsk, uint32_t amsk,
int aofst) {
ALTERA_PLL_Cntrl_Reg = creg;
ALTERA_PLL_Param_Reg = preg;
ALTERA_PLL_Cntrl_RcnfgPrmtrRstMask = rprmsk;
@@ -112,31 +162,41 @@ void ALTERA_PLL_SetDefines(uint32_t creg, uint32_t preg, uint32_t rprmsk, uint32
}
#endif
void ALTERA_PLL_ResetPLL () {
void ALTERA_PLL_ResetPLL() {
LOG(logINFO, ("Resetting only PLL\n"));
LOG(logDEBUG2, ("pllrstmsk:0x%x\n", ALTERA_PLL_Cntrl_PLLRstMask));
bus_w(ALTERA_PLL_Cntrl_Reg, bus_r(ALTERA_PLL_Cntrl_Reg) | ALTERA_PLL_Cntrl_PLLRstMask);
LOG(logDEBUG2, ("Set PLL Reset mSk: ALTERA_PLL_Cntrl_Reg:0x%x\n", bus_r(ALTERA_PLL_Cntrl_Reg)));
bus_w(ALTERA_PLL_Cntrl_Reg,
bus_r(ALTERA_PLL_Cntrl_Reg) | ALTERA_PLL_Cntrl_PLLRstMask);
LOG(logDEBUG2, ("Set PLL Reset mSk: ALTERA_PLL_Cntrl_Reg:0x%x\n",
bus_r(ALTERA_PLL_Cntrl_Reg)));
usleep(ALTERA_PLL_WAIT_TIME_US);
bus_w(ALTERA_PLL_Cntrl_Reg, bus_r(ALTERA_PLL_Cntrl_Reg) & ~ALTERA_PLL_Cntrl_PLLRstMask);
LOG(logDEBUG2, ("UnSet PLL Reset mSk: ALTERA_PLL_Cntrl_Reg:0x%x\n", bus_r(ALTERA_PLL_Cntrl_Reg)));
bus_w(ALTERA_PLL_Cntrl_Reg,
bus_r(ALTERA_PLL_Cntrl_Reg) & ~ALTERA_PLL_Cntrl_PLLRstMask);
LOG(logDEBUG2, ("UnSet PLL Reset mSk: ALTERA_PLL_Cntrl_Reg:0x%x\n",
bus_r(ALTERA_PLL_Cntrl_Reg)));
}
void ALTERA_PLL_ResetPLLAndReconfiguration () {
void ALTERA_PLL_ResetPLLAndReconfiguration() {
LOG(logINFO, ("Resetting PLL and Reconfiguration\n"));
bus_w(ALTERA_PLL_Cntrl_Reg, bus_r(ALTERA_PLL_Cntrl_Reg) | ALTERA_PLL_Cntrl_RcnfgPrmtrRstMask | ALTERA_PLL_Cntrl_PLLRstMask);
bus_w(ALTERA_PLL_Cntrl_Reg, bus_r(ALTERA_PLL_Cntrl_Reg) |
ALTERA_PLL_Cntrl_RcnfgPrmtrRstMask |
ALTERA_PLL_Cntrl_PLLRstMask);
usleep(ALTERA_PLL_WAIT_TIME_US);
bus_w(ALTERA_PLL_Cntrl_Reg, bus_r(ALTERA_PLL_Cntrl_Reg) & ~ALTERA_PLL_Cntrl_RcnfgPrmtrRstMask & ~ALTERA_PLL_Cntrl_PLLRstMask);
bus_w(ALTERA_PLL_Cntrl_Reg, bus_r(ALTERA_PLL_Cntrl_Reg) &
~ALTERA_PLL_Cntrl_RcnfgPrmtrRstMask &
~ALTERA_PLL_Cntrl_PLLRstMask);
}
void ALTERA_PLL_SetPllReconfigReg(uint32_t reg, uint32_t val, int useSecondWRMask) {
LOG(logDEBUG1, ("Setting PLL Reconfig Reg, reg:0x%x, val:0x%x, useSecondWRMask:%d)\n", reg, val, useSecondWRMask));
void ALTERA_PLL_SetPllReconfigReg(uint32_t reg, uint32_t val,
int useSecondWRMask) {
LOG(logDEBUG1,
("Setting PLL Reconfig Reg, reg:0x%x, val:0x%x, useSecondWRMask:%d)\n",
reg, val, useSecondWRMask));
uint32_t wrmask = ALTERA_PLL_Cntrl_WrPrmtrMask;
#ifdef JUNGFRAUD
@@ -145,36 +205,47 @@ void ALTERA_PLL_SetPllReconfigReg(uint32_t reg, uint32_t val, int useSecondWRMas
}
#endif
LOG(logDEBUG2, ("pllparamreg:0x%x pllcontrolreg:0x%x addrofst:%d addrmsk:0x%x wrmask:0x%x\n",
ALTERA_PLL_Param_Reg, ALTERA_PLL_Cntrl_Reg, ALTERA_PLL_Cntrl_AddrOfst, ALTERA_PLL_Cntrl_AddrMask, wrmask));
LOG(logDEBUG2,
("pllparamreg:0x%x pllcontrolreg:0x%x addrofst:%d addrmsk:0x%x "
"wrmask:0x%x\n",
ALTERA_PLL_Param_Reg, ALTERA_PLL_Cntrl_Reg, ALTERA_PLL_Cntrl_AddrOfst,
ALTERA_PLL_Cntrl_AddrMask, wrmask));
// set parameter
bus_w(ALTERA_PLL_Param_Reg, val);
LOG(logDEBUG2, ("Set Parameter: ALTERA_PLL_Param_Reg:0x%x\n", bus_r(ALTERA_PLL_Param_Reg)));
LOG(logDEBUG2, ("Set Parameter: ALTERA_PLL_Param_Reg:0x%x\n",
bus_r(ALTERA_PLL_Param_Reg)));
usleep(ALTERA_PLL_WAIT_TIME_US);
// set address
bus_w(ALTERA_PLL_Cntrl_Reg, (reg << ALTERA_PLL_Cntrl_AddrOfst) & ALTERA_PLL_Cntrl_AddrMask);
LOG(logDEBUG2, ("Set Address: ALTERA_PLL_Cntrl_Reg:0x%x\n", bus_r(ALTERA_PLL_Cntrl_Reg)));
bus_w(ALTERA_PLL_Cntrl_Reg,
(reg << ALTERA_PLL_Cntrl_AddrOfst) & ALTERA_PLL_Cntrl_AddrMask);
LOG(logDEBUG2, ("Set Address: ALTERA_PLL_Cntrl_Reg:0x%x\n",
bus_r(ALTERA_PLL_Cntrl_Reg)));
usleep(ALTERA_PLL_WAIT_TIME_US);
//write parameter
// write parameter
bus_w(ALTERA_PLL_Cntrl_Reg, bus_r(ALTERA_PLL_Cntrl_Reg) | wrmask);
LOG(logDEBUG2, ("Set WR bit: ALTERA_PLL_Cntrl_Reg:0x%x\n", bus_r(ALTERA_PLL_Cntrl_Reg)));
LOG(logDEBUG2, ("Set WR bit: ALTERA_PLL_Cntrl_Reg:0x%x\n",
bus_r(ALTERA_PLL_Cntrl_Reg)));
usleep(ALTERA_PLL_WAIT_TIME_US);
bus_w(ALTERA_PLL_Cntrl_Reg, bus_r(ALTERA_PLL_Cntrl_Reg) & ~wrmask);
LOG(logDEBUG2, ("Unset WR bit: ALTERA_PLL_Cntrl_Reg:0x%x\n", bus_r(ALTERA_PLL_Cntrl_Reg)));
LOG(logDEBUG2, ("Unset WR bit: ALTERA_PLL_Cntrl_Reg:0x%x\n",
bus_r(ALTERA_PLL_Cntrl_Reg)));
usleep(ALTERA_PLL_WAIT_TIME_US);
}
void ALTERA_PLL_SetPhaseShift(int32_t phase, int clkIndex, int pos) {
LOG(logINFO, ("\tWriting PLL Phase Shift\n"));
uint32_t value = (((phase << ALTERA_PLL_SHIFT_NUM_SHIFTS_OFST) & ALTERA_PLL_SHIFT_NUM_SHIFTS_MSK) |
((clkIndex << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & ALTERA_PLL_SHIFT_CNT_SELECT_MSK) |
(pos ? ALTERA_PLL_SHIFT_UP_DOWN_POS_VAL : ALTERA_PLL_SHIFT_UP_DOWN_NEG_VAL));
uint32_t value = (((phase << ALTERA_PLL_SHIFT_NUM_SHIFTS_OFST) &
ALTERA_PLL_SHIFT_NUM_SHIFTS_MSK) |
((clkIndex << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) &
ALTERA_PLL_SHIFT_CNT_SELECT_MSK) |
(pos ? ALTERA_PLL_SHIFT_UP_DOWN_POS_VAL
: ALTERA_PLL_SHIFT_UP_DOWN_NEG_VAL));
LOG(logDEBUG1, ("C%d phase word:0x%08x\n", clkIndex, value));
@@ -186,16 +257,19 @@ void ALTERA_PLL_SetPhaseShift(int32_t phase, int clkIndex, int pos) {
#endif
// write phase shift
ALTERA_PLL_SetPllReconfigReg(ALTERA_PLL_PHASE_SHIFT_REG, value, useSecondWR);
ALTERA_PLL_SetPllReconfigReg(ALTERA_PLL_PHASE_SHIFT_REG, value,
useSecondWR);
}
void ALTERA_PLL_SetModePolling() {
LOG(logINFO, ("\tSetting Polling Mode\n"));
ALTERA_PLL_SetPllReconfigReg(ALTERA_PLL_MODE_REG, ALTERA_PLL_MODE_PLLNG_MD_VAL, 0);
ALTERA_PLL_SetPllReconfigReg(ALTERA_PLL_MODE_REG,
ALTERA_PLL_MODE_PLLNG_MD_VAL, 0);
}
int ALTERA_PLL_SetOuputFrequency (int clkIndex, int pllVCOFreqMhz, int value) {
LOG(logDEBUG1, ("C%d: Setting output frequency to %d (pllvcofreq: %dMhz)\n", clkIndex, value, pllVCOFreqMhz));
int ALTERA_PLL_SetOuputFrequency(int clkIndex, int pllVCOFreqMhz, int value) {
LOG(logDEBUG1, ("C%d: Setting output frequency to %d (pllvcofreq: %dMhz)\n",
clkIndex, value, pllVCOFreqMhz));
// calculate output frequency
float total_div = (float)pllVCOFreqMhz / (float)value;
@@ -210,20 +284,26 @@ int ALTERA_PLL_SetOuputFrequency (int clkIndex, int pllVCOFreqMhz, int value) {
++high_count;
odd_division = 1;
}
LOG(logINFO, ("\tC%d: Low:%d, High:%d, Odd:%d\n", clkIndex, low_count, high_count, odd_division));
LOG(logINFO, ("\tC%d: Low:%d, High:%d, Odd:%d\n", clkIndex, low_count,
high_count, odd_division));
// command to set output frequency
uint32_t val = (((low_count << ALTERA_PLL_C_COUNTER_LW_CNT_OFST) & ALTERA_PLL_C_COUNTER_LW_CNT_MSK) |
((high_count << ALTERA_PLL_C_COUNTER_HGH_CNT_OFST) & ALTERA_PLL_C_COUNTER_HGH_CNT_MSK) |
((odd_division << ALTERA_PLL_C_COUNTER_ODD_DVSN_OFST) & ALTERA_PLL_C_COUNTER_ODD_DVSN_MSK) |
((clkIndex << ALTERA_PLL_C_COUNTER_SLCT_OFST) & ALTERA_PLL_C_COUNTER_SLCT_MSK));
uint32_t val = (((low_count << ALTERA_PLL_C_COUNTER_LW_CNT_OFST) &
ALTERA_PLL_C_COUNTER_LW_CNT_MSK) |
((high_count << ALTERA_PLL_C_COUNTER_HGH_CNT_OFST) &
ALTERA_PLL_C_COUNTER_HGH_CNT_MSK) |
((odd_division << ALTERA_PLL_C_COUNTER_ODD_DVSN_OFST) &
ALTERA_PLL_C_COUNTER_ODD_DVSN_MSK) |
((clkIndex << ALTERA_PLL_C_COUNTER_SLCT_OFST) &
ALTERA_PLL_C_COUNTER_SLCT_MSK));
LOG(logDEBUG1, ("C%d word:0x%08x\n", clkIndex, val));
// write frequency (post-scale output counter C)
ALTERA_PLL_SetPllReconfigReg(ALTERA_PLL_C_COUNTER_REG, val, 0);
// reset required to keep the phase (must reconfigure adcs again after this as adc clock is stopped temporarily when resetting pll)
ALTERA_PLL_ResetPLL ();
// reset required to keep the phase (must reconfigure adcs again after this
// as adc clock is stopped temporarily when resetting pll)
ALTERA_PLL_ResetPLL();
/*double temp = ((double)pllVCOFreqMhz / (double)(low_count + high_count));
if ((temp - (int)temp) > 0.0001) {
@@ -233,5 +313,3 @@ int ALTERA_PLL_SetOuputFrequency (int clkIndex, int pllVCOFreqMhz, int value) {
*/
return value;
}

90
slsDetectorServers/slsDetectorServer/src/ALTERA_PLL_CYCLONE10.c Executable file → Normal file
View File

@@ -10,40 +10,49 @@
/** PLL Reconfiguration Registers */
// https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an728.pdf
// c counter (C0-C8 (+1 to base address))
#define ALTERA_PLL_C10_C_COUNTER_BASE_REG (0x0C0)
#define ALTERA_PLL_C10_C_COUNTER_MAX_DIVIDER_VAL (512)
#define ALTERA_PLL_C10_C_COUNTER_LW_CNT_OFST (0)
#define ALTERA_PLL_C10_C_COUNTER_LW_CNT_MSK (0x000000FF << ALTERA_PLL_C10_C_COUNTER_LW_CNT_OFST)
#define ALTERA_PLL_C10_C_COUNTER_LW_CNT_MSK \
(0x000000FF << ALTERA_PLL_C10_C_COUNTER_LW_CNT_OFST)
#define ALTERA_PLL_C10_C_COUNTER_HGH_CNT_OFST (8)
#define ALTERA_PLL_C10_C_COUNTER_HGH_CNT_MSK (0x000000FF << ALTERA_PLL_C10_C_COUNTER_HGH_CNT_OFST)
#define ALTERA_PLL_C10_C_COUNTER_HGH_CNT_MSK \
(0x000000FF << ALTERA_PLL_C10_C_COUNTER_HGH_CNT_OFST)
/* total_div = lw_cnt + hgh_cnt */
#define ALTERA_PLL_C10_C_COUNTER_BYPSS_ENBL_OFST (16)
#define ALTERA_PLL_C10_C_COUNTER_BYPSS_ENBL_MSK (0x00000001 << ALTERA_PLL_C10_C_COUNTER_BYPSS_ENBL_OFST)
/* if bypss_enbl = 0, fout = f(vco)/total_div; else fout = f(vco) (c counter is bypassed) */
#define ALTERA_PLL_C10_C_COUNTER_BYPSS_ENBL_MSK \
(0x00000001 << ALTERA_PLL_C10_C_COUNTER_BYPSS_ENBL_OFST)
/* if bypss_enbl = 0, fout = f(vco)/total_div; else fout = f(vco) (c counter is
* bypassed) */
#define ALTERA_PLL_C10_C_COUNTER_ODD_DVSN_OFST (17)
#define ALTERA_PLL_C10_C_COUNTER_ODD_DVSN_MSK (0x00000001 << ALTERA_PLL_C10_C_COUNTER_ODD_DVSN_OFST)
/** if odd_dvsn = 0 (even), duty cycle = hgh_cnt/ total_div; else duty cycle = (hgh_cnt - 0.5) / total_div */
#define ALTERA_PLL_C10_C_COUNTER_ODD_DVSN_MSK \
(0x00000001 << ALTERA_PLL_C10_C_COUNTER_ODD_DVSN_OFST)
/** if odd_dvsn = 0 (even), duty cycle = hgh_cnt/ total_div; else duty cycle =
* (hgh_cnt - 0.5) / total_div */
// dynamic phase shift (C0-C8 (+1 to base address), 0xF for all counters)
#define ALTERA_PLL_C10_PHASE_SHIFT_BASE_REG (0x100)
#define ALTERA_PLL_C10_MAX_SHIFTS_PER_OPERATION (7)
#define ALTERA_PLL_C10_SHIFT_NUM_SHIFTS_OFST (0)
#define ALTERA_PLL_C10_SHIFT_NUM_SHIFTS_MSK (0x00000007 << ALTERA_PLL_C10_SHIFT_NUM_SHIFTS_OFST)
#define ALTERA_PLL_C10_SHIFT_NUM_SHIFTS_MSK \
(0x00000007 << ALTERA_PLL_C10_SHIFT_NUM_SHIFTS_OFST)
#define ALTERA_PLL_C10_SHIFT_UP_DOWN_OFST (3)
#define ALTERA_PLL_C10_SHIFT_UP_DOWN_MSK (0x00000001 << ALTERA_PLL_C10_SHIFT_UP_DOWN_OFST)
#define ALTERA_PLL_C10_SHIFT_UP_DOWN_NEG_VAL ((0x0 << ALTERA_PLL_C10_SHIFT_UP_DOWN_OFST) & ALTERA_PLL_C10_SHIFT_UP_DOWN_MSK)
#define ALTERA_PLL_C10_SHIFT_UP_DOWN_POS_VAL ((0x1 << ALTERA_PLL_C10_SHIFT_UP_DOWN_OFST) & ALTERA_PLL_C10_SHIFT_UP_DOWN_MSK)
#define ALTERA_PLL_C10_SHIFT_UP_DOWN_MSK \
(0x00000001 << ALTERA_PLL_C10_SHIFT_UP_DOWN_OFST)
#define ALTERA_PLL_C10_SHIFT_UP_DOWN_NEG_VAL \
((0x0 << ALTERA_PLL_C10_SHIFT_UP_DOWN_OFST) & \
ALTERA_PLL_C10_SHIFT_UP_DOWN_MSK)
#define ALTERA_PLL_C10_SHIFT_UP_DOWN_POS_VAL \
((0x1 << ALTERA_PLL_C10_SHIFT_UP_DOWN_OFST) & \
ALTERA_PLL_C10_SHIFT_UP_DOWN_MSK)
#define ALTERA_PLL_C10_PHASE_SHIFT_STEP_OF_VCO (8)
#define ALTERA_PLL_C10_WAIT_TIME_US (1 * 1000) // 1 ms
int ALTERA_PLL_C10_Reg_offset = 0x0;
const int ALTERA_PLL_C10_NUM = 2;
uint32_t ALTERA_PLL_C10_BaseAddress[2] = {0x0, 0x0};
@@ -51,7 +60,10 @@ uint32_t ALTERA_PLL_C10_Reset_Reg[2] = {0x0, 0x0};
uint32_t ALTERA_PLL_C10_Reset_Msk[2] = {0x0, 0x0};
int ALTERA_PLL_C10_VCO_FREQ[2] = {0, 0};
void ALTERA_PLL_C10_SetDefines(int regofst, uint32_t baseaddr0, uint32_t baseaddr1, uint32_t resetreg0, uint32_t resetreg1, uint32_t resetmsk0, uint32_t resetmsk1, int vcofreq0, int vcofreq1) {
void ALTERA_PLL_C10_SetDefines(int regofst, uint32_t baseaddr0,
uint32_t baseaddr1, uint32_t resetreg0,
uint32_t resetreg1, uint32_t resetmsk0,
uint32_t resetmsk1, int vcofreq0, int vcofreq1) {
ALTERA_PLL_C10_Reg_offset = regofst;
ALTERA_PLL_C10_BaseAddress[0] = baseaddr0;
ALTERA_PLL_C10_BaseAddress[1] = baseaddr1;
@@ -79,12 +91,13 @@ void ALTERA_PLL_C10_Reconfigure(int pllIndex) {
LOG(logINFO, ("\tReconfiguring PLL %d\n", pllIndex));
// write anything to base address to start reconfiguring
LOG(logDEBUG1, ("\tWriting 1 to base address 0x%x to start reconfiguring\n", ALTERA_PLL_C10_BaseAddress[pllIndex]));
LOG(logDEBUG1, ("\tWriting 1 to base address 0x%x to start reconfiguring\n",
ALTERA_PLL_C10_BaseAddress[pllIndex]));
bus_w_csp1(ALTERA_PLL_C10_BaseAddress[pllIndex], 0x1);
usleep(ALTERA_PLL_C10_WAIT_TIME_US);
}
void ALTERA_PLL_C10_ResetPLL (int pllIndex) {
void ALTERA_PLL_C10_ResetPLL(int pllIndex) {
uint32_t resetreg = ALTERA_PLL_C10_Reset_Reg[pllIndex];
uint32_t resetmsk = ALTERA_PLL_C10_Reset_Msk[pllIndex];
LOG(logINFO, ("Resetting PLL %d\n", pllIndex));
@@ -93,19 +106,26 @@ void ALTERA_PLL_C10_ResetPLL (int pllIndex) {
usleep(ALTERA_PLL_C10_WAIT_TIME_US);
}
void ALTERA_PLL_C10_SetPhaseShift(int pllIndex, int clkIndex, int phase,
int pos) {
LOG(logINFO, ("\tC%d: Writing PLL %d Phase Shift [phase:%d, pos dir:%d]\n",
clkIndex, pllIndex, phase, pos));
void ALTERA_PLL_C10_SetPhaseShift(int pllIndex, int clkIndex, int phase, int pos) {
LOG(logINFO, ("\tC%d: Writing PLL %d Phase Shift [phase:%d, pos dir:%d]\n", clkIndex, pllIndex, phase, pos));
uint32_t addr = ALTERA_PLL_C10_BaseAddress[pllIndex] + (ALTERA_PLL_C10_PHASE_SHIFT_BASE_REG + (int)clkIndex) * ALTERA_PLL_C10_Reg_offset;
uint32_t addr = ALTERA_PLL_C10_BaseAddress[pllIndex] +
(ALTERA_PLL_C10_PHASE_SHIFT_BASE_REG + (int)clkIndex) *
ALTERA_PLL_C10_Reg_offset;
int maxshifts = ALTERA_PLL_C10_MAX_SHIFTS_PER_OPERATION;
// only 7 shifts at a time
while (phase > 0) {
int phaseToDo = (phase > maxshifts) ? maxshifts : phase;
uint32_t value = (((phaseToDo << ALTERA_PLL_C10_SHIFT_NUM_SHIFTS_OFST) & ALTERA_PLL_C10_SHIFT_NUM_SHIFTS_MSK) |
(pos ? ALTERA_PLL_C10_SHIFT_UP_DOWN_POS_VAL : ALTERA_PLL_C10_SHIFT_UP_DOWN_NEG_VAL));
LOG(logDEBUG1, ("\t[addr:0x%x, phaseTodo:%d phaseleft:%d phase word:0x%08x]\n", addr, phaseToDo, phase, value));
uint32_t value = (((phaseToDo << ALTERA_PLL_C10_SHIFT_NUM_SHIFTS_OFST) &
ALTERA_PLL_C10_SHIFT_NUM_SHIFTS_MSK) |
(pos ? ALTERA_PLL_C10_SHIFT_UP_DOWN_POS_VAL
: ALTERA_PLL_C10_SHIFT_UP_DOWN_NEG_VAL));
LOG(logDEBUG1,
("\t[addr:0x%x, phaseTodo:%d phaseleft:%d phase word:0x%08x]\n",
addr, phaseToDo, phase, value));
bus_w_csp1(addr, value);
ALTERA_PLL_C10_Reconfigure(pllIndex);
@@ -113,8 +133,10 @@ void ALTERA_PLL_C10_SetPhaseShift(int pllIndex, int clkIndex, int phase, int pos
}
}
void ALTERA_PLL_C10_SetOuputClockDivider (int pllIndex, int clkIndex, int value) {
LOG(logDEBUG1, ("\tC%d: Setting output clock divider for pll%d to %d\n", clkIndex, pllIndex, value));
void ALTERA_PLL_C10_SetOuputClockDivider(int pllIndex, int clkIndex,
int value) {
LOG(logDEBUG1, ("\tC%d: Setting output clock divider for pll%d to %d\n",
clkIndex, pllIndex, value));
// assume 50% duty cycle
uint32_t low_count = value / 2;
@@ -126,13 +148,19 @@ void ALTERA_PLL_C10_SetOuputClockDivider (int pllIndex, int clkIndex, int value)
++high_count;
odd_division = 1;
}
LOG(logINFO, ("\tC%d: Low:%d, High:%d, Odd:%d\n", clkIndex, low_count, high_count, odd_division));
LOG(logINFO, ("\tC%d: Low:%d, High:%d, Odd:%d\n", clkIndex, low_count,
high_count, odd_division));
// command to set output frequency
uint32_t addr = ALTERA_PLL_C10_BaseAddress[pllIndex] + (ALTERA_PLL_C10_C_COUNTER_BASE_REG + (int)clkIndex) * ALTERA_PLL_C10_Reg_offset;
uint32_t val = (((low_count << ALTERA_PLL_C10_C_COUNTER_LW_CNT_OFST) & ALTERA_PLL_C10_C_COUNTER_LW_CNT_MSK) |
((high_count << ALTERA_PLL_C10_C_COUNTER_HGH_CNT_OFST) & ALTERA_PLL_C10_C_COUNTER_HGH_CNT_MSK) |
((odd_division << ALTERA_PLL_C10_C_COUNTER_ODD_DVSN_OFST) & ALTERA_PLL_C10_C_COUNTER_ODD_DVSN_MSK));
uint32_t addr = ALTERA_PLL_C10_BaseAddress[pllIndex] +
(ALTERA_PLL_C10_C_COUNTER_BASE_REG + (int)clkIndex) *
ALTERA_PLL_C10_Reg_offset;
uint32_t val = (((low_count << ALTERA_PLL_C10_C_COUNTER_LW_CNT_OFST) &
ALTERA_PLL_C10_C_COUNTER_LW_CNT_MSK) |
((high_count << ALTERA_PLL_C10_C_COUNTER_HGH_CNT_OFST) &
ALTERA_PLL_C10_C_COUNTER_HGH_CNT_MSK) |
((odd_division << ALTERA_PLL_C10_C_COUNTER_ODD_DVSN_OFST) &
ALTERA_PLL_C10_C_COUNTER_ODD_DVSN_MSK));
LOG(logDEBUG1, ("\t[addr:0x%x, word:0x%08x]\n", addr, val));
// write frequency
@@ -141,5 +169,5 @@ void ALTERA_PLL_C10_SetOuputClockDivider (int pllIndex, int clkIndex, int value)
ALTERA_PLL_C10_Reconfigure(pllIndex);
// reset required to keep the phase relationships
ALTERA_PLL_C10_ResetPLL (pllIndex);
ALTERA_PLL_C10_ResetPLL(pllIndex);
}

26
slsDetectorServers/slsDetectorServer/src/ASIC_Driver.c Executable file → Normal file
View File

@@ -3,36 +3,36 @@
#include "common.h"
#include "sls_detector_defs.h"
#include <getopt.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <getopt.h>
#include <string.h>
#include <unistd.h>
#include <fcntl.h>
#include <sys/ioctl.h>
#include <linux/types.h>
#include <linux/spi/spidev.h>
#include <linux/types.h>
#include <string.h>
#include <sys/ioctl.h>
#include <unistd.h>
// defines from the fpga
char ASIC_Driver_DriverFileName[MAX_STR_LENGTH];
void ASIC_Driver_SetDefines(char* driverfname) {
void ASIC_Driver_SetDefines(char *driverfname) {
LOG(logINFOBLUE, ("Configuring ASIC Driver to %s\n", driverfname));
memset(ASIC_Driver_DriverFileName, 0, MAX_STR_LENGTH);
strcpy(ASIC_Driver_DriverFileName, driverfname);
}
int ASIC_Driver_Set (int index, int length, char* buffer) {
int ASIC_Driver_Set(int index, int length, char *buffer) {
char temp[20];
memset(temp, 0, sizeof(temp));
sprintf(temp, "%d", index + 1);
char fname[MAX_STR_LENGTH];
strcpy(fname, ASIC_Driver_DriverFileName);
strcat(fname, temp);
LOG(logDEBUG2, ("\t[chip index: %d, length: %d, fname: %s]\n", index, length, fname));
LOG(logDEBUG2,
("\t[chip index: %d, length: %d, fname: %s]\n", index, length, fname));
{
LOG(logDEBUG2, ("\t[values: \n"));
int i;
@@ -43,15 +43,17 @@ int ASIC_Driver_Set (int index, int length, char* buffer) {
}
#ifndef VIRTUAL
int fd=open(fname, O_RDWR);
int fd = open(fname, O_RDWR);
if (fd == -1) {
LOG(logERROR, ("Could not open file %s for writing to control ASIC (%d)\n", fname, index));
LOG(logERROR,
("Could not open file %s for writing to control ASIC (%d)\n", fname,
index));
return FAIL;
}
struct spi_ioc_transfer transfer;
memset(&transfer, 0, sizeof(transfer));
transfer.tx_buf = (unsigned long) buffer;
transfer.tx_buf = (unsigned long)buffer;
transfer.len = length;
transfer.cs_change = 0;

30
slsDetectorServers/slsDetectorServer/src/DAC6571.c Executable file → Normal file
View File

@@ -9,48 +9,44 @@
#define DAC6571_MIN_DAC_VAL (0x0)
#define DAC6571_MAX_DAC_VAL (0x3FF)
// defines from the hardware
int DAC6571_HardMaxVoltage = 0;
char DAC6571_DriverFileName[MAX_STR_LENGTH];
void DAC6571_SetDefines(int hardMaxV, char* driverfname) {
LOG(logINFOBLUE, ("Configuring High Voltage to %s (hard max: %dV)\n", driverfname, hardMaxV));
void DAC6571_SetDefines(int hardMaxV, char *driverfname) {
LOG(logINFOBLUE, ("Configuring High Voltage to %s (hard max: %dV)\n",
driverfname, hardMaxV));
DAC6571_HardMaxVoltage = hardMaxV;
memset(DAC6571_DriverFileName, 0, MAX_STR_LENGTH);
strcpy(DAC6571_DriverFileName, driverfname);
}
int DAC6571_Set (int val) {
int DAC6571_Set(int val) {
LOG(logDEBUG1, ("Setting high voltage to %d\n", val));
if (val < 0)
return FAIL;
int dacvalue = 0;
// convert value
ConvertToDifferentRange(0, DAC6571_HardMaxVoltage,
DAC6571_MIN_DAC_VAL, DAC6571_MAX_DAC_VAL,
val, &dacvalue);
ConvertToDifferentRange(0, DAC6571_HardMaxVoltage, DAC6571_MIN_DAC_VAL,
DAC6571_MAX_DAC_VAL, val, &dacvalue);
LOG(logINFO, ("\t%dV (dacval %d)\n", val, dacvalue));
#ifndef VIRTUAL
//open file
FILE* fd=fopen(DAC6571_DriverFileName,"w");
if (fd==NULL) {
LOG(logERROR, ("Could not open file %s for writing to set high voltage\n", DAC6571_DriverFileName));
// open file
FILE *fd = fopen(DAC6571_DriverFileName, "w");
if (fd == NULL) {
LOG(logERROR,
("Could not open file %s for writing to set high voltage\n",
DAC6571_DriverFileName));
return FAIL;
}
//convert to string, add 0 and write to file
// convert to string, add 0 and write to file
fprintf(fd, "%d\n", dacvalue);
fclose(fd);
#endif
return OK;
}

173
slsDetectorServers/slsDetectorServer/src/I2C.c Executable file → Normal file
View File

@@ -23,7 +23,6 @@
* I2C_RX_DATA_FIFO_REG
*/
#define I2C_DATA_RATE_KBPS (200)
/** Control Register */
@@ -31,28 +30,46 @@
#define I2C_CTRL_ENBLE_CORE_MSK (0x00000001 << I2C_CTRL_ENBLE_CORE_OFST)
#define I2C_CTRL_BUS_SPEED_OFST (1)
#define I2C_CTRL_BUS_SPEED_MSK (0x00000001 << I2C_CTRL_BUS_SPEED_OFST)
#define I2C_CTRL_BUS_SPEED_STNDRD_100_VAL ((0x0 << I2C_CTRL_BUS_SPEED_OFST) & I2C_CTRL_BUS_SPEED_MSK) // standard mode (up to 100 kbps)
#define I2C_CTRL_BUS_SPEED_FAST_400_VAL ((0x1 << I2C_CTRL_BUS_SPEED_OFST) & I2C_CTRL_BUS_SPEED_MSK) // fast mode (up to 400 kbps)
/** if actual level of transfer command fifo <= thd level, TX_READY interrupt asserted */
#define I2C_CTRL_BUS_SPEED_STNDRD_100_VAL \
((0x0 << I2C_CTRL_BUS_SPEED_OFST) & \
I2C_CTRL_BUS_SPEED_MSK) // standard mode (up to 100 kbps)
#define I2C_CTRL_BUS_SPEED_FAST_400_VAL \
((0x1 << I2C_CTRL_BUS_SPEED_OFST) & \
I2C_CTRL_BUS_SPEED_MSK) // fast mode (up to 400 kbps)
/** if actual level of transfer command fifo <= thd level, TX_READY interrupt
* asserted */
#define I2C_CTRL_TFR_CMD_FIFO_THD_OFST (2)
#define I2C_CTRL_TFR_CMD_FIFO_THD_MSK (0x00000003 << I2C_CTRL_TFR_CMD_FIFO_THD_OFST)
#define I2C_CTRL_TFR_CMD_EMPTY_VAL ((0x0 << I2C_CTRL_TFR_CMD_FIFO_THD_OFST) & I2C_CTRL_TFR_CMD_FIFO_THD_MSK)
#define I2C_CTRL_TFR_CMD_ONE_FOURTH_VAL ((0x1 << I2C_CTRL_TFR_CMD_FIFO_THD_OFST) & I2C_CTRL_TFR_CMD_FIFO_THD_MSK)
#define I2C_CTRL_TFR_CMD_ONE_HALF_VAL ((0x2 << I2C_CTRL_TFR_CMD_FIFO_THD_OFST) & I2C_CTRL_TFR_CMD_FIFO_THD_MSK)
#define I2C_CTRL_TFR_CMD_NOT_FULL_VAL ((0x3 << I2C_CTRL_TFR_CMD_FIFO_THD_OFST) & I2C_CTRL_TFR_CMD_FIFO_THD_MSK)
/** if actual level of receive data fifo <= thd level, RX_READY interrupt asserted */
#define I2C_CTRL_TFR_CMD_FIFO_THD_MSK \
(0x00000003 << I2C_CTRL_TFR_CMD_FIFO_THD_OFST)
#define I2C_CTRL_TFR_CMD_EMPTY_VAL \
((0x0 << I2C_CTRL_TFR_CMD_FIFO_THD_OFST) & I2C_CTRL_TFR_CMD_FIFO_THD_MSK)
#define I2C_CTRL_TFR_CMD_ONE_FOURTH_VAL \
((0x1 << I2C_CTRL_TFR_CMD_FIFO_THD_OFST) & I2C_CTRL_TFR_CMD_FIFO_THD_MSK)
#define I2C_CTRL_TFR_CMD_ONE_HALF_VAL \
((0x2 << I2C_CTRL_TFR_CMD_FIFO_THD_OFST) & I2C_CTRL_TFR_CMD_FIFO_THD_MSK)
#define I2C_CTRL_TFR_CMD_NOT_FULL_VAL \
((0x3 << I2C_CTRL_TFR_CMD_FIFO_THD_OFST) & I2C_CTRL_TFR_CMD_FIFO_THD_MSK)
/** if actual level of receive data fifo <= thd level, RX_READY interrupt
* asserted */
#define I2C_CTRL_RX_DATA_FIFO_THD_OFST (4)
#define I2C_CTRL_RX_DATA_FIFO_THD_MSK (0x00000003 << I2C_CTRL_RX_DATA_FIFO_THD_OFST)
#define I2C_CTRL_RX_DATA_1_VALID_ENTRY_VAL ((0x0 << I2C_CTRL_RX_DATA_FIFO_THD_OFST) & I2C_CTRL_RX_DATA_FIFO_THD_MSK)
#define I2C_CTRL_RX_DATA_ONE_FOURTH_VAL ((0x1 << I2C_CTRL_RX_DATA_FIFO_THD_OFST) & I2C_CTRL_RX_DATA_FIFO_THD_MSK)
#define I2C_CTRL_RX_DATA_ONE_HALF_VAL ((0x2 << I2C_CTRL_RX_DATA_FIFO_THD_OFST) & I2C_CTRL_RX_DATA_FIFO_THD_MSK)
#define I2C_CTRL_RX_DATA_FULL_VAL ((0x3 << I2C_CTRL_RX_DATA_FIFO_THD_OFST) & I2C_CTRL_RX_DATA_FIFO_THD_MSK)
#define I2C_CTRL_RX_DATA_FIFO_THD_MSK \
(0x00000003 << I2C_CTRL_RX_DATA_FIFO_THD_OFST)
#define I2C_CTRL_RX_DATA_1_VALID_ENTRY_VAL \
((0x0 << I2C_CTRL_RX_DATA_FIFO_THD_OFST) & I2C_CTRL_RX_DATA_FIFO_THD_MSK)
#define I2C_CTRL_RX_DATA_ONE_FOURTH_VAL \
((0x1 << I2C_CTRL_RX_DATA_FIFO_THD_OFST) & I2C_CTRL_RX_DATA_FIFO_THD_MSK)
#define I2C_CTRL_RX_DATA_ONE_HALF_VAL \
((0x2 << I2C_CTRL_RX_DATA_FIFO_THD_OFST) & I2C_CTRL_RX_DATA_FIFO_THD_MSK)
#define I2C_CTRL_RX_DATA_FULL_VAL \
((0x3 << I2C_CTRL_RX_DATA_FIFO_THD_OFST) & I2C_CTRL_RX_DATA_FIFO_THD_MSK)
/** Transfer Command Fifo register */
#define I2C_TFR_CMD_RW_OFST (0)
#define I2C_TFR_CMD_RW_MSK (0x00000001 << I2C_TFR_CMD_RW_OFST)
#define I2C_TFR_CMD_RW_WRITE_VAL ((0x0 << I2C_TFR_CMD_RW_OFST) & I2C_TFR_CMD_RW_MSK)
#define I2C_TFR_CMD_RW_READ_VAL ((0x1 << I2C_TFR_CMD_RW_OFST) & I2C_TFR_CMD_RW_MSK)
#define I2C_TFR_CMD_RW_WRITE_VAL \
((0x0 << I2C_TFR_CMD_RW_OFST) & I2C_TFR_CMD_RW_MSK)
#define I2C_TFR_CMD_RW_READ_VAL \
((0x1 << I2C_TFR_CMD_RW_OFST) & I2C_TFR_CMD_RW_MSK)
#define I2C_TFR_CMD_ADDR_OFST (1)
#define I2C_TFR_CMD_ADDR_MSK (0x0000007F << I2C_TFR_CMD_ADDR_OFST)
/** when writing, rw and addr converts to data to be written mask */
@@ -73,19 +90,23 @@
/** SCL Low Count register */
#define I2C_SCL_LOW_COUNT_PERIOD_OFST (0)
#define I2C_SCL_LOW_COUNT_PERIOD_MSK (0x0000FFFF << I2C_SCL_LOW_COUNT_PERIOD_OFST)
#define I2C_SCL_LOW_COUNT_PERIOD_MSK \
(0x0000FFFF << I2C_SCL_LOW_COUNT_PERIOD_OFST)
/** SCL High Count register */
#define I2C_SCL_HIGH_COUNT_PERIOD_OFST (0)
#define I2C_SCL_HIGH_COUNT_PERIOD_MSK (0x0000FFFF << I2C_SCL_HIGH_COUNT_PERIOD_OFST)
#define I2C_SCL_HIGH_COUNT_PERIOD_MSK \
(0x0000FFFF << I2C_SCL_HIGH_COUNT_PERIOD_OFST)
/** SDA Hold Count register */
#define I2C_SDA_HOLD_COUNT_PERIOD_OFST (0)
#define I2C_SDA_HOLD_COUNT_PERIOD_MSK (0x0000FFFF << I2C_SDA_HOLD_COUNT_PERIOD_OFST)
#define I2C_SDA_HOLD_COUNT_PERIOD_MSK \
(0x0000FFFF << I2C_SDA_HOLD_COUNT_PERIOD_OFST)
/** Receive Data Fifo Level register */
//#define I2C_RX_DATA_FIFO_LVL_OFST (0)
//#define I2C_RX_DATA_FIFO_LVL_MSK (0x000000FF << I2C_RX_DATA_FIFO_LVL_OFST)
//#define I2C_RX_DATA_FIFO_LVL_MSK (0x000000FF <<
//I2C_RX_DATA_FIFO_LVL_OFST)
// defines in the fpga
uint32_t I2C_Control_Reg = 0x0;
@@ -97,14 +118,14 @@ uint32_t I2C_Scl_High_Count_Reg = 0x0;
uint32_t I2C_Sda_Hold_Reg = 0x0;
uint32_t I2C_Transfer_Command_Fifo_Reg = 0x0;
void I2C_ConfigureI2CCore(uint32_t creg, uint32_t sreg,
uint32_t rreg, uint32_t rlvlreg,
uint32_t slreg, uint32_t shreg, uint32_t sdreg, uint32_t treg) {
void I2C_ConfigureI2CCore(uint32_t creg, uint32_t sreg, uint32_t rreg,
uint32_t rlvlreg, uint32_t slreg, uint32_t shreg,
uint32_t sdreg, uint32_t treg) {
LOG(logINFO, ("\tConfiguring I2C Core for %d kbps:\n", I2C_DATA_RATE_KBPS));
LOG(logDEBUG1,("controlreg,:0x%x, statusreg,:0x%x, "
LOG(logDEBUG1, ("controlreg,:0x%x, statusreg,:0x%x, "
"rxrdatafiforeg: 0x%x, rxdatafifocountreg,:0x%x, "
"scllow,:0x%x, sclhighreg,:0x%x, sdaholdreg,:0x%x, transfercmdreg,:0x%x\n",
"scllow,:0x%x, sclhighreg,:0x%x, sdaholdreg,:0x%x, "
"transfercmdreg,:0x%x\n",
creg, sreg, rreg, rlvlreg, slreg, shreg, sdreg, treg));
I2C_Control_Reg = creg;
@@ -117,57 +138,77 @@ void I2C_ConfigureI2CCore(uint32_t creg, uint32_t sreg,
I2C_Transfer_Command_Fifo_Reg = treg;
// calculate scl low and high period count
uint32_t sclPeriodNs = ((1000.00 * 1000.00 * 1000.00) / ((double)I2C_DATA_RATE_KBPS * 1000.00));
uint32_t sclPeriodNs = ((1000.00 * 1000.00 * 1000.00) /
((double)I2C_DATA_RATE_KBPS * 1000.00));
// scl low period same as high period
uint32_t sclLowPeriodNs = sclPeriodNs / 2;
// convert to us, then to clock (defined in blackfin.h)
uint32_t sclLowPeriodCount = (sclLowPeriodNs / 1000.00) * I2C_CLOCK_MHZ;
// calculate sda hold data count
uint32_t sdaDataHoldTimeNs = (sclLowPeriodNs / 2); // scl low period same as high period
uint32_t sdaDataHoldTimeNs =
(sclLowPeriodNs / 2); // scl low period same as high period
// convert to us, then to clock (defined in blackfin.h)
uint32_t sdaDataHoldCount = ((sdaDataHoldTimeNs / 1000.00) * I2C_CLOCK_MHZ);
LOG(logINFO, ("\tSetting SCL Low Period: %d ns (%d clocks)\n", sclLowPeriodNs, sclLowPeriodCount));
bus_w(I2C_Scl_Low_Count_Reg, bus_r(I2C_Scl_Low_Count_Reg) |
((sclLowPeriodCount << I2C_SCL_LOW_COUNT_PERIOD_OFST) & I2C_SCL_LOW_COUNT_PERIOD_MSK));
LOG(logINFO, ("\tSetting SCL Low Period: %d ns (%d clocks)\n",
sclLowPeriodNs, sclLowPeriodCount));
bus_w(I2C_Scl_Low_Count_Reg,
bus_r(I2C_Scl_Low_Count_Reg) |
((sclLowPeriodCount << I2C_SCL_LOW_COUNT_PERIOD_OFST) &
I2C_SCL_LOW_COUNT_PERIOD_MSK));
LOG(logDEBUG1, ("SCL Low reg:0x%x\n", bus_r(I2C_Scl_Low_Count_Reg)));
LOG(logINFO, ("\tSetting SCL High Period: %d ns (%d clocks)\n", sclLowPeriodNs, sclLowPeriodCount));
bus_w(I2C_Scl_High_Count_Reg, bus_r(I2C_Scl_High_Count_Reg) |
((sclLowPeriodCount << I2C_SCL_HIGH_COUNT_PERIOD_OFST) & I2C_SCL_HIGH_COUNT_PERIOD_MSK));
LOG(logINFO, ("\tSetting SCL High Period: %d ns (%d clocks)\n",
sclLowPeriodNs, sclLowPeriodCount));
bus_w(I2C_Scl_High_Count_Reg,
bus_r(I2C_Scl_High_Count_Reg) |
((sclLowPeriodCount << I2C_SCL_HIGH_COUNT_PERIOD_OFST) &
I2C_SCL_HIGH_COUNT_PERIOD_MSK));
LOG(logDEBUG1, ("SCL High reg:0x%x\n", bus_r(I2C_Scl_High_Count_Reg)));
LOG(logINFO, ("\tSetting SDA Hold Time: %d ns (%d clocks)\n", sdaDataHoldTimeNs, sdaDataHoldCount));
bus_w(I2C_Sda_Hold_Reg, bus_r(I2C_Sda_Hold_Reg) |
((sdaDataHoldCount << I2C_SDA_HOLD_COUNT_PERIOD_OFST) & I2C_SDA_HOLD_COUNT_PERIOD_MSK));
LOG(logINFO, ("\tSetting SDA Hold Time: %d ns (%d clocks)\n",
sdaDataHoldTimeNs, sdaDataHoldCount));
bus_w(I2C_Sda_Hold_Reg,
bus_r(I2C_Sda_Hold_Reg) |
((sdaDataHoldCount << I2C_SDA_HOLD_COUNT_PERIOD_OFST) &
I2C_SDA_HOLD_COUNT_PERIOD_MSK));
LOG(logDEBUG1, ("SDA Hold reg:0x%x\n", bus_r(I2C_Sda_Hold_Reg)));
LOG(logINFO, ("\tEnabling core and bus speed to fast (up to 400 kbps)\n"));
bus_w(I2C_Control_Reg, bus_r(I2C_Control_Reg) |
I2C_CTRL_ENBLE_CORE_MSK | I2C_CTRL_BUS_SPEED_FAST_400_VAL);// fixme: (works?)
bus_w(I2C_Control_Reg,
bus_r(I2C_Control_Reg) | I2C_CTRL_ENBLE_CORE_MSK |
I2C_CTRL_BUS_SPEED_FAST_400_VAL); // fixme: (works?)
LOG(logDEBUG1, ("Control reg:0x%x\n", bus_r(I2C_Control_Reg)));
//The INA226 supports the transmission protocol for fast mode (1 kHz to 400 kHz) and high-speed mode (1 kHz to 2.94 MHz).
// The INA226 supports the transmission protocol for fast mode (1 kHz to 400
// kHz) and high-speed mode (1 kHz to 2.94 MHz).
}
uint32_t I2C_Read(uint32_t devId, uint32_t addr) {
LOG(logDEBUG2, (" ================================================\n"));
LOG(logDEBUG2, (" Reading from I2C device 0x%x and reg 0x%x\n", devId, addr));
LOG(logDEBUG2,
(" Reading from I2C device 0x%x and reg 0x%x\n", devId, addr));
// device Id mask
uint32_t devIdMask = ((devId << I2C_TFR_CMD_ADDR_OFST) & I2C_TFR_CMD_ADDR_MSK);
uint32_t devIdMask =
((devId << I2C_TFR_CMD_ADDR_OFST) & I2C_TFR_CMD_ADDR_MSK);
LOG(logDEBUG2, (" devId:0x%x\n", devIdMask));
// write I2C ID
bus_w(I2C_Transfer_Command_Fifo_Reg, (devIdMask & ~(I2C_TFR_CMD_RW_MSK)));
LOG(logDEBUG2, (" write devID and R/-W:0x%x\n", (devIdMask & ~(I2C_TFR_CMD_RW_MSK))));
LOG(logDEBUG2,
(" write devID and R/-W:0x%x\n", (devIdMask & ~(I2C_TFR_CMD_RW_MSK))));
// write register addr
bus_w(I2C_Transfer_Command_Fifo_Reg, addr);
LOG(logDEBUG2, (" write addr:0x%x\n", addr));
// repeated start with read (repeated start needed here because it was in write operation mode earlier, for the device ID)
bus_w(I2C_Transfer_Command_Fifo_Reg, (devIdMask | I2C_TFR_CMD_RPTD_STRT_MSK | I2C_TFR_CMD_RW_READ_VAL));
LOG(logDEBUG2, (" repeated start:0x%x\n", (devIdMask | I2C_TFR_CMD_RPTD_STRT_MSK | I2C_TFR_CMD_RW_READ_VAL)));
// repeated start with read (repeated start needed here because it was in
// write operation mode earlier, for the device ID)
bus_w(I2C_Transfer_Command_Fifo_Reg,
(devIdMask | I2C_TFR_CMD_RPTD_STRT_MSK | I2C_TFR_CMD_RW_READ_VAL));
LOG(logDEBUG2,
(" repeated start:0x%x\n",
(devIdMask | I2C_TFR_CMD_RPTD_STRT_MSK | I2C_TFR_CMD_RW_READ_VAL)));
// continue reading
bus_w(I2C_Transfer_Command_Fifo_Reg, 0x0);
@@ -180,10 +221,11 @@ uint32_t I2C_Read(uint32_t devId, uint32_t addr) {
// read value
uint32_t retval = 0;
//In case one wants to do something more general (INA226 receives only 2 bytes)
// In case one wants to do something more general (INA226 receives only 2
// bytes)
// wait till status is idle
int status = 1;
while(status) {
while (status) {
status = bus_r(I2C_Status_Reg) & I2C_STATUS_BUSY_MSK;
LOG(logDEBUG2, (" status:%d\n", status));
usleep(0);
@@ -196,7 +238,8 @@ uint32_t I2C_Read(uint32_t devId, uint32_t addr) {
// level bytes to read, read 1 byte at a time
for (iloop = level - 1; iloop >= 0; --iloop) {
u_int16_t byte = bus_r(I2C_Rx_Data_Fifo_Reg) & I2C_RX_DATA_FIFO_RXDATA_MSK;
u_int16_t byte =
bus_r(I2C_Rx_Data_Fifo_Reg) & I2C_RX_DATA_FIFO_RXDATA_MSK;
LOG(logDEBUG2, (" byte nr %d:0x%x\n", iloop, byte));
// push by 1 byte at a time
retval |= (byte << (8 * iloop));
@@ -208,33 +251,43 @@ uint32_t I2C_Read(uint32_t devId, uint32_t addr) {
void I2C_Write(uint32_t devId, uint32_t addr, uint16_t data) {
LOG(logDEBUG2, (" ================================================\n"));
LOG(logDEBUG2, (" Writing to I2C (Device:0x%x, reg:0x%x, data:%d)\n", devId, addr, data));
LOG(logDEBUG2, (" Writing to I2C (Device:0x%x, reg:0x%x, data:%d)\n", devId,
addr, data));
// device Id mask
uint32_t devIdMask = ((devId << I2C_TFR_CMD_ADDR_OFST) & I2C_TFR_CMD_ADDR_MSK);
uint32_t devIdMask =
((devId << I2C_TFR_CMD_ADDR_OFST) & I2C_TFR_CMD_ADDR_MSK);
LOG(logDEBUG2, (" devId:0x%x\n", devId));
// write I2C ID
bus_w(I2C_Transfer_Command_Fifo_Reg, (devIdMask & ~(I2C_TFR_CMD_RW_MSK)));
LOG(logDEBUG2, (" write devID and R/-W:0x%x\n", (devIdMask & ~(I2C_TFR_CMD_RW_MSK))));
LOG(logDEBUG2,
(" write devID and R/-W:0x%x\n", (devIdMask & ~(I2C_TFR_CMD_RW_MSK))));
// write register addr
bus_w(I2C_Transfer_Command_Fifo_Reg, addr);
LOG(logDEBUG2, (" write addr:0x%x\n", addr));
// do not do the repeated start as it is already in write operation mode (else it wont work)
// do not do the repeated start as it is already in write operation mode
// (else it wont work)
uint8_t msb = (uint8_t)((data & 0xFF00) >> 8);
uint8_t lsb = (uint8_t)(data & 0x00FF);
LOG(logDEBUG2, (" msb:0x%02x, lsb:0x%02x\n", msb, lsb));
// writing data MSB
bus_w(I2C_Transfer_Command_Fifo_Reg, ((msb << I2C_TFR_CMD_DATA_FR_WR_OFST) & I2C_TFR_CMD_DATA_FR_WR_MSK));
LOG(logDEBUG2, (" write msb:0x%02x\n", ((msb << I2C_TFR_CMD_DATA_FR_WR_OFST) & I2C_TFR_CMD_DATA_FR_WR_MSK)));
bus_w(I2C_Transfer_Command_Fifo_Reg,
((msb << I2C_TFR_CMD_DATA_FR_WR_OFST) & I2C_TFR_CMD_DATA_FR_WR_MSK));
LOG(logDEBUG2,
(" write msb:0x%02x\n",
((msb << I2C_TFR_CMD_DATA_FR_WR_OFST) & I2C_TFR_CMD_DATA_FR_WR_MSK)));
// writing data LSB and stop writing bit
bus_w(I2C_Transfer_Command_Fifo_Reg, ((lsb << I2C_TFR_CMD_DATA_FR_WR_OFST) & I2C_TFR_CMD_DATA_FR_WR_MSK) | I2C_TFR_CMD_STOP_MSK);
LOG(logDEBUG2, (" write lsb and stop writing:0x%x\n", ((lsb << I2C_TFR_CMD_DATA_FR_WR_OFST) & I2C_TFR_CMD_DATA_FR_WR_MSK) | I2C_TFR_CMD_STOP_MSK));
bus_w(I2C_Transfer_Command_Fifo_Reg,
((lsb << I2C_TFR_CMD_DATA_FR_WR_OFST) & I2C_TFR_CMD_DATA_FR_WR_MSK) |
I2C_TFR_CMD_STOP_MSK);
LOG(logDEBUG2,
(" write lsb and stop writing:0x%x\n",
((lsb << I2C_TFR_CMD_DATA_FR_WR_OFST) & I2C_TFR_CMD_DATA_FR_WR_MSK) |
I2C_TFR_CMD_STOP_MSK));
LOG(logDEBUG2, (" ================================================\n"));
}

79
slsDetectorServers/slsDetectorServer/src/INA226.c Executable file → Normal file
View File

@@ -16,43 +16,46 @@
/** INA226 defines */
/** Register set */
#define INA226_CONFIGURATION_REG (0x00) //R/W
#define INA226_SHUNT_VOLTAGE_REG (0x01) //R
#define INA226_BUS_VOLTAGE_REG (0x02) //R
#define INA226_POWER_REG (0x03) //R
#define INA226_CURRENT_REG (0x04) //R
#define INA226_CALIBRATION_REG (0x05) //R/W
#define INA226_MASK_ENABLE_REG (0x06) //R/W
#define INA226_ALERT_LIMIT_REG (0x07) //R/W
#define INA226_MANUFACTURER_ID_REG (0xFE) //R
#define INA226_DIE_ID_REG (0xFF) //R
#define INA226_CONFIGURATION_REG (0x00) // R/W
#define INA226_SHUNT_VOLTAGE_REG (0x01) // R
#define INA226_BUS_VOLTAGE_REG (0x02) // R
#define INA226_POWER_REG (0x03) // R
#define INA226_CURRENT_REG (0x04) // R
#define INA226_CALIBRATION_REG (0x05) // R/W
#define INA226_MASK_ENABLE_REG (0x06) // R/W
#define INA226_ALERT_LIMIT_REG (0x07) // R/W
#define INA226_MANUFACTURER_ID_REG (0xFE) // R
#define INA226_DIE_ID_REG (0xFF) // R
/** bus voltage register */
#define INA226_BUS_VOLTAGE_VMIN_UV (1250) // 1.25mV
#define INA226_BUS_VOLTAGE_MX_STPS (0x7FFF + 1)
#define INA226_BUS_VOLTAGE_VMAX_UV (INA226_BUS_VOLTAGE_VMIN_UV * INA226_BUS_VOLTAGE_MX_STPS) // 40960000uV, 40.96V
#define INA226_BUS_VOLTAGE_VMAX_UV \
(INA226_BUS_VOLTAGE_VMIN_UV * \
INA226_BUS_VOLTAGE_MX_STPS) // 40960000uV, 40.96V
/** shunt voltage register */
#define INA226_SHUNT_VOLTAGE_VMIN_NV (2500) // 2.5uV
#define INA226_SHUNT_VOLTAGE_MX_STPS (0x7FFF + 1)
#define INA226_SHUNT_VOLTAGE_VMAX_NV (INA226_SHUNT_VOLTAGE_VMIN_NV * INA226_SHUNT_VOLTAGE_MX_STPS) // 81920000nV, 81.92mV
#define INA226_SHUNT_VOLTAGE_VMAX_NV \
(INA226_SHUNT_VOLTAGE_VMIN_NV * \
INA226_SHUNT_VOLTAGE_MX_STPS) // 81920000nV, 81.92mV
#define INA226_SHUNT_NEGATIVE_MSK (1 << 15)
#define INA226_SHUNT_ABS_VALUE_MSK (0x7FFF)
/** current precision for calibration register */
#define INA226_CURRENT_IMIN_UA (100) //100uA can be changed
#define INA226_CURRENT_IMIN_UA (100) // 100uA can be changed
/** calibration register */
#define INA226_CALIBRATION_MSK (0x7FFF)
/** get calibration register value to be set */
#define INA226_getCalibrationValue(rOhm) (0.00512 /(INA226_CURRENT_IMIN_UA * 1e-6 * rOhm))
#define INA226_getCalibrationValue(rOhm) \
(0.00512 / (INA226_CURRENT_IMIN_UA * 1e-6 * rOhm))
/** get current unit */
#define INA226_getConvertedCurrentUnits(shuntV, calibReg) ((double)shuntV * (double)calibReg / (double)2048)
#define INA226_getConvertedCurrentUnits(shuntV, calibReg) \
((double)shuntV * (double)calibReg / (double)2048)
// defines from the fpga
double INA226_Shunt_Resistor_Ohm = 0.0;
@@ -61,8 +64,8 @@ int INA226_Calibration_Register_Value = 0;
#define INA226_CALIBRATION_CURRENT_TOLERANCE (1.2268)
void INA226_ConfigureI2CCore(double rOhm, uint32_t creg, uint32_t sreg,
uint32_t rreg, uint32_t rlvlreg,
uint32_t slreg, uint32_t shreg, uint32_t sdreg, uint32_t treg) {
uint32_t rreg, uint32_t rlvlreg, uint32_t slreg,
uint32_t shreg, uint32_t sdreg, uint32_t treg) {
LOG(logINFOBLUE, ("Configuring INA226\n"));
LOG(logDEBUG1, ("Shunt ohm resistor: %f\n", rOhm));
INA226_Shunt_Resistor_Ohm = rOhm;
@@ -71,13 +74,19 @@ void INA226_ConfigureI2CCore(double rOhm, uint32_t creg, uint32_t sreg,
}
void INA226_CalibrateCurrentRegister(uint32_t deviceId) {
LOG(logINFO, ("Calibrating Current Register for Device ID: 0x%x\n", deviceId));
LOG(logINFO,
("Calibrating Current Register for Device ID: 0x%x\n", deviceId));
// get calibration value based on shunt resistor
uint16_t calVal = ((uint16_t)INA226_getCalibrationValue(INA226_Shunt_Resistor_Ohm)) & INA226_CALIBRATION_MSK;
LOG(logINFO, ("\tCalculated calibration reg value: 0x%0x (%d)\n", calVal, calVal));
uint16_t calVal =
((uint16_t)INA226_getCalibrationValue(INA226_Shunt_Resistor_Ohm)) &
INA226_CALIBRATION_MSK;
LOG(logINFO,
("\tCalculated calibration reg value: 0x%0x (%d)\n", calVal, calVal));
calVal = ((double)calVal / INA226_CALIBRATION_CURRENT_TOLERANCE) + 0.5;
LOG(logINFO, ("\tRealculated (for tolerance) calibration reg value: 0x%0x (%d)\n", calVal, calVal));
LOG(logINFO,
("\tRealculated (for tolerance) calibration reg value: 0x%0x (%d)\n",
calVal, calVal));
INA226_Calibration_Register_Value = calVal;
// calibrate current register
@@ -86,7 +95,9 @@ void INA226_CalibrateCurrentRegister(uint32_t deviceId) {
// read back calibration register
int retval = I2C_Read(deviceId, INA226_CALIBRATION_REG);
if (retval != calVal) {
LOG(logERROR, ("Cannot set calibration register for I2C. Set 0x%x, read 0x%x\n", calVal, retval));
LOG(logERROR,
("Cannot set calibration register for I2C. Set 0x%x, read 0x%x\n",
calVal, retval));
}
}
@@ -98,14 +109,15 @@ int INA226_ReadVoltage(uint32_t deviceId) {
// value in uV
int voltageuV = 0;
ConvertToDifferentRange(0, INA226_BUS_VOLTAGE_MX_STPS,
INA226_BUS_VOLTAGE_VMIN_UV, INA226_BUS_VOLTAGE_VMAX_UV,
regval, &voltageuV);
INA226_BUS_VOLTAGE_VMIN_UV,
INA226_BUS_VOLTAGE_VMAX_UV, regval, &voltageuV);
LOG(logDEBUG1, (" voltage: 0x%d uV\n", voltageuV));
// value in mV
int voltagemV = voltageuV / 1000;
LOG(logDEBUG1, (" voltage: %d mV\n", voltagemV));
LOG(logINFO, ("Voltage via I2C (Device: 0x%x): %d mV\n", deviceId, voltagemV));
LOG(logINFO,
("Voltage via I2C (Device: 0x%x): %d mV\n", deviceId, voltagemV));
return voltagemV;
}
@@ -125,10 +137,10 @@ int INA226_ReadCurrent(uint32_t deviceId) {
LOG(logDEBUG1, (" shunt voltage reg: %d\n", shuntVoltageRegVal));
}
// value for current
int retval = INA226_getConvertedCurrentUnits(shuntVoltageRegVal, INA226_Calibration_Register_Value);
int retval = INA226_getConvertedCurrentUnits(
shuntVoltageRegVal, INA226_Calibration_Register_Value);
LOG(logDEBUG1, (" current unit value: %d\n", retval));
// reading directly the current reg
LOG(logDEBUG1, (" Reading current reg\n"));
int cuurentRegVal = I2C_Read(deviceId, INA226_CURRENT_REG);
@@ -141,7 +153,9 @@ int INA226_ReadCurrent(uint32_t deviceId) {
}
// should be the same
LOG(logDEBUG1, (" ===============current reg: %d, current unit cal:%d=================================\n", cuurentRegVal, retval));
LOG(logDEBUG1, (" ===============current reg: %d, current unit "
"cal:%d=================================\n",
cuurentRegVal, retval));
// current in uA
int currentuA = cuurentRegVal * INA226_CURRENT_IMIN_UA;
LOG(logDEBUG1, (" current: %d uA\n", currentuA));
@@ -150,7 +164,8 @@ int INA226_ReadCurrent(uint32_t deviceId) {
int currentmA = (currentuA / 1000.00) + 0.5;
LOG(logDEBUG1, (" current: %d mA\n", currentmA));
LOG(logINFO, ("Current via I2C (Device: 0x%x): %d mA\n", deviceId, currentmA));
LOG(logINFO,
("Current via I2C (Device: 0x%x): %d mA\n", deviceId, currentmA));
return currentmA;
}

127
slsDetectorServers/slsDetectorServer/src/LTC2620.c Executable file → Normal file
View File

@@ -1,8 +1,8 @@
#include "LTC2620.h"
#include "commonServerFunctions.h" // blackfin.h, ansi.h
#include "common.h"
#include "blackfin.h"
#include "clogger.h"
#include "common.h"
#include "commonServerFunctions.h" // blackfin.h, ansi.h
#include "sls_detector_defs.h"
#include <string.h>
@@ -16,15 +16,26 @@
#define LTC2620_DAC_CMD_OFST (20)
#define LTC2620_DAC_CMD_MSK (0x0000000F << LTC2620_DAC_CMD_OFST)
#define LTC2620_DAC_CMD_WR_IN_VAL ((0x0 << LTC2620_DAC_CMD_OFST) & LTC2620_DAC_CMD_MSK) // write to input register
#define LTC2620_DAC_CMD_UPDTE_DAC_VAL ((0x1 << LTC2620_DAC_CMD_OFST) & LTC2620_DAC_CMD_MSK) // update dac (power up)
#define LTC2620_DAC_CMD_WR_IN_UPDTE_DAC_VAL ((0x2 << LTC2620_DAC_CMD_OFST) & LTC2620_DAC_CMD_MSK) // write to input register and update dac (power up)
#define LTC2620_DAC_CMD_WR_UPDTE_DAC_VAL ((0x3 << LTC2620_DAC_CMD_OFST) & LTC2620_DAC_CMD_MSK) // write to and update dac (power up)
#define LTC2620_DAC_CMD_PWR_DWN_VAL ((0x4 << LTC2620_DAC_CMD_OFST) & LTC2620_DAC_CMD_MSK)
#define LTC2620_DAC_CMD_NO_OPRTN_VAL ((0xF << LTC2620_DAC_CMD_OFST) & LTC2620_DAC_CMD_MSK)
#define LTC2620_DAC_CMD_WR_IN_VAL \
((0x0 << LTC2620_DAC_CMD_OFST) & \
LTC2620_DAC_CMD_MSK) // write to input register
#define LTC2620_DAC_CMD_UPDTE_DAC_VAL \
((0x1 << LTC2620_DAC_CMD_OFST) & \
LTC2620_DAC_CMD_MSK) // update dac (power up)
#define LTC2620_DAC_CMD_WR_IN_UPDTE_DAC_VAL \
((0x2 << LTC2620_DAC_CMD_OFST) & \
LTC2620_DAC_CMD_MSK) // write to input register and update dac (power up)
#define LTC2620_DAC_CMD_WR_UPDTE_DAC_VAL \
((0x3 << LTC2620_DAC_CMD_OFST) & \
LTC2620_DAC_CMD_MSK) // write to and update dac (power up)
#define LTC2620_DAC_CMD_PWR_DWN_VAL \
((0x4 << LTC2620_DAC_CMD_OFST) & LTC2620_DAC_CMD_MSK)
#define LTC2620_DAC_CMD_NO_OPRTN_VAL \
((0xF << LTC2620_DAC_CMD_OFST) & LTC2620_DAC_CMD_MSK)
#define LTC2620_NUMBITS (24)
#define LTC2620_DAISY_CHAIN_NUMBITS (32) // due to shift register FIXME: was 33 earlier
#define LTC2620_DAISY_CHAIN_NUMBITS \
(32) // due to shift register FIXME: was 33 earlier
#define LTC2620_NUMCHANNELS (8)
#define LTC2620_PWR_DOWN_VAL (-100)
#define LTC2620_MIN_VAL (0)
@@ -45,7 +56,9 @@ int LTC2620_Ndac = 0;
int LTC2620_MinVoltage = 0;
int LTC2620_MaxVoltage = 0;
void LTC2620_SetDefines(uint32_t reg, uint32_t cmsk, uint32_t clkmsk, uint32_t dmsk, int dofst, int nd, int minMV, int maxMV) {
void LTC2620_SetDefines(uint32_t reg, uint32_t cmsk, uint32_t clkmsk,
uint32_t dmsk, int dofst, int nd, int minMV,
int maxMV) {
LTC2620_Reg = reg;
LTC2620_CsMask = cmsk;
LTC2620_ClkMask = clkmsk;
@@ -57,53 +70,44 @@ void LTC2620_SetDefines(uint32_t reg, uint32_t cmsk, uint32_t clkmsk, uint32_t d
}
void LTC2620_Disable() {
bus_w(LTC2620_Reg, (bus_r(LTC2620_Reg)
| LTC2620_CsMask
| LTC2620_ClkMask)
& ~(LTC2620_DigMask));
bus_w(LTC2620_Reg, (bus_r(LTC2620_Reg) | LTC2620_CsMask | LTC2620_ClkMask) &
~(LTC2620_DigMask));
}
int LTC2620_GetPowerDownValue() {
return LTC2620_PWR_DOWN_VAL;
}
int LTC2620_GetPowerDownValue() { return LTC2620_PWR_DOWN_VAL; }
int LTC2620_GetMinInput() {
return LTC2620_MIN_VAL;
}
int LTC2620_GetMinInput() { return LTC2620_MIN_VAL; }
int LTC2620_GetMaxInput() {
return LTC2620_MAX_VAL;
}
int LTC2620_GetMaxInput() { return LTC2620_MAX_VAL; }
int LTC2620_GetMaxNumSteps() {
return LTC2620_MAX_STEPS;
}
int LTC2620_GetMaxNumSteps() { return LTC2620_MAX_STEPS; }
int LTC2620_VoltageToDac(int voltage, int* dacval) {
int LTC2620_VoltageToDac(int voltage, int *dacval) {
return ConvertToDifferentRange(LTC2620_MinVoltage, LTC2620_MaxVoltage,
LTC2620_MIN_VAL, LTC2620_MAX_VAL,
voltage, dacval);
LTC2620_MIN_VAL, LTC2620_MAX_VAL, voltage,
dacval);
}
int LTC2620_DacToVoltage(int dacval, int* voltage) {
return ConvertToDifferentRange( LTC2620_MIN_VAL, LTC2620_MAX_VAL,
int LTC2620_DacToVoltage(int dacval, int *voltage) {
return ConvertToDifferentRange(LTC2620_MIN_VAL, LTC2620_MAX_VAL,
LTC2620_MinVoltage, LTC2620_MaxVoltage,
dacval, voltage);
}
void LTC2620_SetSingle(int cmd, int data, int dacaddr) {
LOG(logDEBUG2, ("(Single) dac addr:%d, dac value:%d, cmd:%d\n", dacaddr, data, cmd));
LOG(logDEBUG2,
("(Single) dac addr:%d, dac value:%d, cmd:%d\n", dacaddr, data, cmd));
uint32_t codata = (((data << LTC2620_DAC_DATA_OFST) & LTC2620_DAC_DATA_MSK) |
((dacaddr << LTC2620_DAC_ADDR_OFST) & LTC2620_DAC_ADDR_MSK) |
cmd);
uint32_t codata =
(((data << LTC2620_DAC_DATA_OFST) & LTC2620_DAC_DATA_MSK) |
((dacaddr << LTC2620_DAC_ADDR_OFST) & LTC2620_DAC_ADDR_MSK) | cmd);
LOG(logDEBUG2, ("codata: 0x%x\n", codata));
serializeToSPI (LTC2620_Reg, codata, LTC2620_CsMask, LTC2620_NUMBITS,
serializeToSPI(LTC2620_Reg, codata, LTC2620_CsMask, LTC2620_NUMBITS,
LTC2620_ClkMask, LTC2620_DigMask, LTC2620_DigOffset, 0);
}
void LTC2620_SendDaisyData(uint32_t* valw, uint32_t val) {
void LTC2620_SendDaisyData(uint32_t *valw, uint32_t val) {
sendDataToSPI(valw, LTC2620_Reg, val, LTC2620_DAISY_CHAIN_NUMBITS,
LTC2620_ClkMask, LTC2620_DigMask, LTC2620_DigOffset);
}
@@ -114,18 +118,20 @@ void LTC2620_SetDaisy(int cmd, int data, int dacaddr, int chipIndex) {
uint32_t valw = 0;
int ichip = 0;
LOG(logDEBUG2, ("(Daisy) desired chip index:%d, nchip:%d, dac ch:%d, val:%d, cmd:0x%x \n",
LOG(logDEBUG2, ("(Daisy) desired chip index:%d, nchip:%d, dac ch:%d, "
"val:%d, cmd:0x%x \n",
chipIndex, nchip, dacaddr, data, cmd));
// data to be bit banged
uint32_t codata = (((data << LTC2620_DAC_DATA_OFST) & LTC2620_DAC_DATA_MSK) |
((dacaddr << LTC2620_DAC_ADDR_OFST) & LTC2620_DAC_ADDR_MSK) |
cmd);
uint32_t codata =
(((data << LTC2620_DAC_DATA_OFST) & LTC2620_DAC_DATA_MSK) |
((dacaddr << LTC2620_DAC_ADDR_OFST) & LTC2620_DAC_ADDR_MSK) | cmd);
LOG(logDEBUG2, ("codata: 0x%x\n", codata));
// select all chips (ctb daisy chain; others 1 chip)
LOG(logDEBUG2, ("Selecting LTC2620\n"));
SPIChipSelect (&valw, LTC2620_Reg, LTC2620_CsMask, LTC2620_ClkMask, LTC2620_DigMask, 0);
SPIChipSelect(&valw, LTC2620_Reg, LTC2620_CsMask, LTC2620_ClkMask,
LTC2620_DigMask, 0);
// send same data to all
if (chipIndex < 0) {
@@ -138,7 +144,8 @@ void LTC2620_SetDaisy(int cmd, int data, int dacaddr, int chipIndex) {
// send to one chip, nothing to others
else {
// send nothing to subsequent ichips (daisy chain) (if any chips after desired chip)
// send nothing to subsequent ichips (daisy chain) (if any chips after
// desired chip)
for (ichip = chipIndex + 1; ichip < nchip; ++ichip) {
LOG(logDEBUG2, ("Send nothing to ichip %d\n", ichip));
LTC2620_SendDaisyData(&valw, LTC2620_DAC_CMD_NO_OPRTN_VAL);
@@ -148,7 +155,8 @@ void LTC2620_SetDaisy(int cmd, int data, int dacaddr, int chipIndex) {
LOG(logDEBUG2, ("Send data (0x%x) to ichip %d\n", codata, chipIndex));
LTC2620_SendDaisyData(&valw, codata);
// send nothing to preceding ichips (daisy chain) (if any chips in front of desired chip)
// send nothing to preceding ichips (daisy chain) (if any chips in front
// of desired chip)
for (ichip = 0; ichip < chipIndex; ++ichip) {
LOG(logDEBUG2, ("Send nothing to ichip %d\n", ichip));
LTC2620_SendDaisyData(&valw, LTC2620_DAC_CMD_NO_OPRTN_VAL);
@@ -157,11 +165,13 @@ void LTC2620_SetDaisy(int cmd, int data, int dacaddr, int chipIndex) {
// deselect all chips (ctb daisy chain; others 1 chip)
LOG(logDEBUG2, ("Deselecting LTC2620\n"));
SPIChipDeselect(&valw, LTC2620_Reg, LTC2620_CsMask, LTC2620_ClkMask, LTC2620_DigMask, 0);
SPIChipDeselect(&valw, LTC2620_Reg, LTC2620_CsMask, LTC2620_ClkMask,
LTC2620_DigMask, 0);
}
void LTC2620_Set(int cmd, int data, int dacaddr, int chipIndex) {
LOG(logDEBUG1, ("cmd:0x%x, data:%d, dacaddr:%d, chipIndex:%d\n", cmd, data, dacaddr, chipIndex));
LOG(logDEBUG1, ("cmd:0x%x, data:%d, dacaddr:%d, chipIndex:%d\n", cmd, data,
dacaddr, chipIndex));
LOG(logDEBUG2, (" ================================================\n"));
// ctb
if (LTC2620_Ndac > LTC2620_NUMCHANNELS)
@@ -172,7 +182,7 @@ void LTC2620_Set(int cmd, int data, int dacaddr, int chipIndex) {
LOG(logDEBUG2, (" ================================================\n"));
}
void LTC2620_Configure(){
void LTC2620_Configure() {
LOG(logINFOBLUE, ("Configuring LTC2620\n"));
// dac channel - all channels
@@ -182,13 +192,14 @@ void LTC2620_Configure(){
int data = 0x6;
// command
int cmd = LTC2620_DAC_CMD_WR_IN_VAL; //FIXME: should be command update and not write(does not power up)
int cmd = LTC2620_DAC_CMD_WR_IN_VAL; // FIXME: should be command update and
// not write(does not power up)
// also why do we need to power up (for jctb, we power down next)
LTC2620_Set(cmd, data, addr, -1);
}
void LTC2620_SetDAC (int dacnum, int data) {
void LTC2620_SetDAC(int dacnum, int data) {
LOG(logDEBUG1, ("Setting dac %d to %d\n", dacnum, data));
// LTC2620 index
int ichip = dacnum / LTC2620_NUMCHANNELS;
@@ -204,17 +215,18 @@ void LTC2620_SetDAC (int dacnum, int data) {
cmd = LTC2620_DAC_CMD_PWR_DWN_VAL;
LOG(logDEBUG1, ("POWER DOWN\n"));
} else {
LOG(logDEBUG1,("Write to Input Register and Update\n"));
LOG(logDEBUG1, ("Write to Input Register and Update\n"));
}
LTC2620_Set(cmd, data, addr, ichip);
}
int LTC2620_SetDACValue (int dacnum, int val, int mV, int* dacval) {
int LTC2620_SetDACValue(int dacnum, int val, int mV, int *dacval) {
LOG(logDEBUG1, ("dacnum:%d, val:%d, ismV:%d\n", dacnum, val, mV));
// validate index
if (dacnum < 0 || dacnum >= LTC2620_Ndac) {
LOG(logERROR, ("Dac index %d is out of bounds (0 to %d)\n", dacnum, LTC2620_Ndac - 1));
LOG(logERROR, ("Dac index %d is out of bounds (0 to %d)\n", dacnum,
LTC2620_Ndac - 1));
return FAIL;
}
@@ -234,19 +246,22 @@ int LTC2620_SetDACValue (int dacnum, int val, int mV, int* dacval) {
ret = LTC2620_VoltageToDac(val, dacval);
} else if (val >= 0 && dacnum <= ndacsonly) {
// do not convert power down dac val
//(if not ndacsonly (pwr/vchip): dont need to print mV value as it will be wrong (wrong limits))
//(if not ndacsonly (pwr/vchip): dont need to print mV value as it will
//be wrong (wrong limits))
ret = LTC2620_DacToVoltage(val, &dacmV);
}
// conversion out of bounds
if (ret == FAIL) {
LOG(logERROR, ("Setting Dac %d %s is out of bounds\n", dacnum, (mV ? "mV" : "dac units")));
LOG(logERROR, ("Setting Dac %d %s is out of bounds\n", dacnum,
(mV ? "mV" : "dac units")));
return FAIL;
}
// set
if ( (*dacval >= 0) || (*dacval == LTC2620_PWR_DOWN_VAL)) {
LOG(logINFO, ("Setting DAC %d: %d dac (%d mV)\n",dacnum, *dacval, dacmV));
if ((*dacval >= 0) || (*dacval == LTC2620_PWR_DOWN_VAL)) {
LOG(logINFO,
("Setting DAC %d: %d dac (%d mV)\n", dacnum, *dacval, dacmV));
LTC2620_SetDAC(dacnum, *dacval);
}
return OK;

55
slsDetectorServers/slsDetectorServer/src/LTC2620_Driver.c Executable file → Normal file
View File

@@ -10,40 +10,40 @@
#define LTC2620_D_MAX_DAC_VAL (4095) // 12 bits
#define LTC2620_D_MAX_STEPS (LTC2620_D_MAX_DAC_VAL + 1)
// defines from the fpga
int LTC2620_D_HardMaxVoltage = 0;
char LTC2620_D_DriverFileName[MAX_STR_LENGTH];
int LTC2620_D_NumDacs = 0;
void LTC2620_D_SetDefines(int hardMaxV, char* driverfname, int numdacs) {
LOG(logINFOBLUE, ("Configuring DACs (LTC2620) to %s (numdacs:%d, hard max: %dmV)\n", driverfname, numdacs, hardMaxV));
void LTC2620_D_SetDefines(int hardMaxV, char *driverfname, int numdacs) {
LOG(logINFOBLUE,
("Configuring DACs (LTC2620) to %s (numdacs:%d, hard max: %dmV)\n",
driverfname, numdacs, hardMaxV));
LTC2620_D_HardMaxVoltage = hardMaxV;
memset(LTC2620_D_DriverFileName, 0, MAX_STR_LENGTH);
strcpy(LTC2620_D_DriverFileName, driverfname);
LTC2620_D_NumDacs = numdacs;
}
int LTC2620_D_GetMaxNumSteps() {
return LTC2620_D_MAX_STEPS;
int LTC2620_D_GetMaxNumSteps() { return LTC2620_D_MAX_STEPS; }
int LTC2620_D_VoltageToDac(int voltage, int *dacval) {
return ConvertToDifferentRange(0, LTC2620_D_HardMaxVoltage, 0,
LTC2620_D_MAX_DAC_VAL, voltage, dacval);
}
int LTC2620_D_VoltageToDac(int voltage, int* dacval) {
return ConvertToDifferentRange(0, LTC2620_D_HardMaxVoltage, 0, LTC2620_D_MAX_DAC_VAL,
voltage, dacval);
int LTC2620_D_DacToVoltage(int dacval, int *voltage) {
return ConvertToDifferentRange(0, LTC2620_D_MAX_DAC_VAL, 0,
LTC2620_D_HardMaxVoltage, dacval, voltage);
}
int LTC2620_D_DacToVoltage(int dacval, int* voltage) {
return ConvertToDifferentRange( 0, LTC2620_D_MAX_DAC_VAL, 0, LTC2620_D_HardMaxVoltage,
dacval, voltage);
}
int LTC2620_D_SetDACValue (int dacnum, int val, int mV, char* dacname, int* dacval) {
int LTC2620_D_SetDACValue(int dacnum, int val, int mV, char *dacname,
int *dacval) {
LOG(logDEBUG1, ("dacnum:%d, val:%d, ismV:%d\n", dacnum, val, mV));
// validate index
if (dacnum < 0 || dacnum >= LTC2620_D_NumDacs) {
LOG(logERROR, ("Dac index %d is out of bounds (0 to %d)\n", dacnum, LTC2620_D_NumDacs - 1));
LOG(logERROR, ("Dac index %d is out of bounds (0 to %d)\n", dacnum,
LTC2620_D_NumDacs - 1));
return FAIL;
}
@@ -64,14 +64,15 @@ int LTC2620_D_SetDACValue (int dacnum, int val, int mV, char* dacname, int* dacv
// conversion out of bounds
if (ret == FAIL) {
LOG(logERROR, ("Setting Dac %d %s is out of bounds\n", dacnum, (mV ? "mV" : "dac units")));
LOG(logERROR, ("Setting Dac %d %s is out of bounds\n", dacnum,
(mV ? "mV" : "dac units")));
return FAIL;
}
// set
if ( (*dacval >= 0) || (*dacval == LTC2620_D_PWR_DOWN_VAL)) {
LOG(logINFO, ("Setting DAC %2d [%-12s] : %d dac (%d mV)\n",dacnum, dacname, *dacval, dacmV));
if ((*dacval >= 0) || (*dacval == LTC2620_D_PWR_DOWN_VAL)) {
LOG(logINFO, ("Setting DAC %2d [%-12s] : %d dac (%d mV)\n", dacnum,
dacname, *dacval, dacmV));
#ifndef VIRTUAL
char fname[MAX_STR_LENGTH];
@@ -80,19 +81,19 @@ int LTC2620_D_SetDACValue (int dacnum, int val, int mV, char* dacname, int* dacv
memset(temp, 0, sizeof(temp));
sprintf(temp, "%d", dacnum);
strcat(fname, temp);
LOG(logDEBUG1, ("fname %s\n",fname));
LOG(logDEBUG1, ("fname %s\n", fname));
//open file
FILE* fd=fopen(fname,"w");
if (fd==NULL) {
LOG(logERROR, ("Could not open file %s for writing to set dac %d\n", fname, dacnum));
// open file
FILE *fd = fopen(fname, "w");
if (fd == NULL) {
LOG(logERROR, ("Could not open file %s for writing to set dac %d\n",
fname, dacnum));
return FAIL;
}
//convert to string, add 0 and write to file
// convert to string, add 0 and write to file
fprintf(fd, "%d\n", *dacval);
fclose(fd);
#endif
}
return OK;
}

22
slsDetectorServers/slsDetectorServer/src/MAX1932.c Executable file → Normal file
View File

@@ -1,8 +1,8 @@
#include "MAX1932.h"
#include "commonServerFunctions.h" // blackfin.h, ansi.h
#include "blackfin.h"
#include "clogger.h"
#include "common.h"
#include "commonServerFunctions.h" // blackfin.h, ansi.h
#include "sls_detector_defs.h"
/* MAX1932 HV DEFINES */
@@ -24,8 +24,8 @@ int MAX1932_DigOffset = 0x0;
int MAX1932_MinVoltage = 0;
int MAX1932_MaxVoltage = 0;
void MAX1932_SetDefines(uint32_t reg, uint32_t cmsk, uint32_t clkmsk, uint32_t dmsk, int dofst,
int minMV, int maxMV) {
void MAX1932_SetDefines(uint32_t reg, uint32_t cmsk, uint32_t clkmsk,
uint32_t dmsk, int dofst, int minMV, int maxMV) {
LOG(logINFOBLUE, ("Configuring High Voltage\n"));
MAX1932_Reg = reg;
MAX1932_CsMask = cmsk;
@@ -37,13 +37,11 @@ void MAX1932_SetDefines(uint32_t reg, uint32_t cmsk, uint32_t clkmsk, uint32_t d
}
void MAX1932_Disable() {
bus_w(MAX1932_Reg, (bus_r(MAX1932_Reg)
| MAX1932_CsMask
| MAX1932_ClkMask)
& ~(MAX1932_DigMask));
bus_w(MAX1932_Reg, (bus_r(MAX1932_Reg) | MAX1932_CsMask | MAX1932_ClkMask) &
~(MAX1932_DigMask));
}
int MAX1932_Set (int* val) {
int MAX1932_Set(int *val) {
LOG(logDEBUG1, ("Setting high voltage to %d\n", *val));
if (*val < 0)
return FAIL;
@@ -64,8 +62,8 @@ int MAX1932_Set (int* val) {
else {
// no failure in conversion as limits handled (range from 0x1 to 0xFF)
ConvertToDifferentRange(MAX1932_MinVoltage, MAX1932_MaxVoltage,
MAX1932_MIN_DAC_VAL, MAX1932_MAX_DAC_VAL,
*val, &dacvalue);
MAX1932_MIN_DAC_VAL, MAX1932_MAX_DAC_VAL, *val,
&dacvalue);
dacvalue &= MAX1932_HV_DATA_MSK;
}
@@ -74,7 +72,3 @@ int MAX1932_Set (int* val) {
MAX1932_ClkMask, MAX1932_DigMask, MAX1932_DigOffset, 0);
return OK;
}

65
slsDetectorServers/slsDetectorServer/src/UDPPacketHeaderGenerator.c Executable file → Normal file
View File

@@ -2,16 +2,16 @@
#include "clogger.h"
#include "sls_detector_defs.h"
#include <stdio.h>
#include <stdlib.h>
#include <sys/types.h>
#include <sys/socket.h>
#include <arpa/inet.h>
#include <netinet/in.h>
#include <string.h>
#include <unistd.h>
#include <errno.h>
#include <netdb.h>
#include <netinet/in.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <sys/socket.h>
#include <sys/types.h>
#include <unistd.h>
#define UDP_PACKET_HEADER_VERSION (0x1)
@@ -19,26 +19,21 @@ extern const enum detectorType myDetectorType;
extern int analogDataBytes;
extern int digitalDataBytes;
extern char* analogData;
extern char* digitalData;
extern char *analogData;
extern char *digitalData;
int analogOffset = 0;
int digitalOffset = 0;
uint32_t udpPacketNumber = 0;
uint64_t udpFrameNumber = 0;
uint32_t getUDPPacketNumber() { return udpPacketNumber; }
uint32_t getUDPPacketNumber() {
return udpPacketNumber;
}
uint64_t getUDPFrameNumber() { return udpFrameNumber; }
uint64_t getUDPFrameNumber() {
return udpFrameNumber;
}
void createUDPPacketHeader(char* buffer, uint16_t id) {
void createUDPPacketHeader(char *buffer, uint16_t id) {
memset(buffer, 0, sizeof(sls_detector_header));
sls_detector_header* header = (sls_detector_header*)(buffer);
sls_detector_header *header = (sls_detector_header *)(buffer);
header->modId = id;
// row and column remains 0 (only used by ctb now)
@@ -53,8 +48,10 @@ void createUDPPacketHeader(char* buffer, uint16_t id) {
udpFrameNumber = 0;
}
int fillUDPPacket(char* buffer) {
LOG(logDEBUG2, ("Analog (databytes:%d, offset:%d)\n Digital (databytes:%d offset:%d)\n",
int fillUDPPacket(char *buffer) {
LOG(logDEBUG2,
("Analog (databytes:%d, offset:%d)\n Digital (databytes:%d "
"offset:%d)\n",
analogDataBytes, analogOffset, digitalDataBytes, digitalOffset));
// reached end of data for one frame
if (analogOffset >= analogDataBytes && digitalOffset >= digitalDataBytes) {
@@ -64,7 +61,7 @@ int fillUDPPacket(char* buffer) {
return 0;
}
sls_detector_header* header = (sls_detector_header*)(buffer);
sls_detector_header *header = (sls_detector_header *)(buffer);
// update frame number, starts at 1 (reset packet number)
if (analogOffset == 0 && digitalOffset == 0) {
@@ -76,7 +73,8 @@ int fillUDPPacket(char* buffer) {
// increment and copy udp packet number (starts at 0)
++udpPacketNumber;
header->packetNumber = udpPacketNumber;
LOG(logDEBUG2, ("Creating packet number %d (fnum:%lld)\n", udpPacketNumber, (long long int) udpFrameNumber));
LOG(logDEBUG2, ("Creating packet number %d (fnum:%lld)\n", udpPacketNumber,
(long long int)udpFrameNumber));
int freeBytes = UDP_PACKET_DATA_BYTES;
@@ -84,10 +82,12 @@ int fillUDPPacket(char* buffer) {
int analogBytes = 0;
if (analogOffset < analogDataBytes) {
// bytes to copy
analogBytes = ((analogOffset + freeBytes) <= analogDataBytes) ?
freeBytes : (analogDataBytes - analogOffset);
analogBytes = ((analogOffset + freeBytes) <= analogDataBytes)
? freeBytes
: (analogDataBytes - analogOffset);
// copy
memcpy(buffer + sizeof(sls_detector_header), analogData + analogOffset, analogBytes);
memcpy(buffer + sizeof(sls_detector_header), analogData + analogOffset,
analogBytes);
// increment offset
analogOffset += analogBytes;
// decrement free bytes
@@ -98,10 +98,12 @@ int fillUDPPacket(char* buffer) {
int digitalBytes = 0;
if (freeBytes && digitalOffset < digitalDataBytes) {
// bytes to copy
digitalBytes = ((digitalOffset + freeBytes) <= digitalDataBytes) ?
freeBytes : (digitalDataBytes - digitalOffset);
digitalBytes = ((digitalOffset + freeBytes) <= digitalDataBytes)
? freeBytes
: (digitalDataBytes - digitalOffset);
// copy
memcpy(buffer + sizeof(sls_detector_header) + analogBytes, digitalData + digitalOffset, digitalBytes);
memcpy(buffer + sizeof(sls_detector_header) + analogBytes,
digitalData + digitalOffset, digitalBytes);
// increment offset
digitalOffset += digitalBytes;
// decrement free bytes
@@ -110,8 +112,11 @@ int fillUDPPacket(char* buffer) {
// pad data
if (freeBytes) {
memset(buffer + sizeof(sls_detector_header) + analogBytes + digitalBytes, 0, freeBytes);
LOG(logDEBUG1, ("Padding %d bytes for fnum:%lld pnum:%d\n", freeBytes, (long long int)udpFrameNumber, udpPacketNumber));
memset(buffer + sizeof(sls_detector_header) + analogBytes +
digitalBytes,
0, freeBytes);
LOG(logDEBUG1, ("Padding %d bytes for fnum:%lld pnum:%d\n", freeBytes,
(long long int)udpFrameNumber, udpPacketNumber));
}
return UDP_PACKET_DATA_BYTES + sizeof(sls_detector_header);

69
slsDetectorServers/slsDetectorServer/src/blackfin.c Executable file → Normal file
View File

@@ -1,74 +1,73 @@
#include "blackfin.h"
#include "RegisterDefs.h"
#include "sls_detector_defs.h"
#include "ansi.h"
#include "clogger.h"
#include "sls_detector_defs.h"
#include <fcntl.h> // open
#include <sys/mman.h> // mmap
/* global variables */
u_int32_t* csp0base = 0;
u_int32_t *csp0base = 0;
#define CSP0 0x20200000
#define MEM_SIZE 0x100000
void bus_w16(u_int32_t offset, u_int16_t data) {
volatile u_int16_t *ptr1;
ptr1=(u_int16_t*)(csp0base + offset / 2);
*ptr1=data;
ptr1 = (u_int16_t *)(csp0base + offset / 2);
*ptr1 = data;
}
u_int16_t bus_r16(u_int32_t offset){
u_int16_t bus_r16(u_int32_t offset) {
volatile u_int16_t *ptr1;
ptr1=(u_int16_t*)(csp0base + offset / 2);
ptr1 = (u_int16_t *)(csp0base + offset / 2);
return *ptr1;
}
void bus_w(u_int32_t offset, u_int32_t data) {
volatile u_int32_t *ptr1;
ptr1=(u_int32_t*)(csp0base + offset / 2);
*ptr1=data;
ptr1 = (u_int32_t *)(csp0base + offset / 2);
*ptr1 = data;
}
u_int32_t bus_r(u_int32_t offset) {
volatile u_int32_t *ptr1;
ptr1=(u_int32_t*)(csp0base + offset / 2);
ptr1 = (u_int32_t *)(csp0base + offset / 2);
return *ptr1;
}
int64_t get64BitReg(int aLSB, int aMSB){
int64_t get64BitReg(int aLSB, int aMSB) {
int64_t v64;
u_int32_t vLSB,vMSB;
vLSB=bus_r(aLSB);
vMSB=bus_r(aMSB);
v64=vMSB;
v64=(v64<<32) | vLSB;
LOG(logDEBUG5, (" reg64(%x,%x) %x %x %llx\n", aLSB, aMSB, vLSB, vMSB, (long long unsigned int)v64));
u_int32_t vLSB, vMSB;
vLSB = bus_r(aLSB);
vMSB = bus_r(aMSB);
v64 = vMSB;
v64 = (v64 << 32) | vLSB;
LOG(logDEBUG5, (" reg64(%x,%x) %x %x %llx\n", aLSB, aMSB, vLSB, vMSB,
(long long unsigned int)v64));
return v64;
}
int64_t set64BitReg(int64_t value, int aLSB, int aMSB){
int64_t set64BitReg(int64_t value, int aLSB, int aMSB) {
int64_t v64;
u_int32_t vLSB,vMSB;
if (value!=-1) {
vLSB=value&(0xffffffff);
bus_w(aLSB,vLSB);
v64=value>> 32;
vMSB=v64&(0xffffffff);
bus_w(aMSB,vMSB);
u_int32_t vLSB, vMSB;
if (value != -1) {
vLSB = value & (0xffffffff);
bus_w(aLSB, vLSB);
v64 = value >> 32;
vMSB = v64 & (0xffffffff);
bus_w(aMSB, vMSB);
}
return get64BitReg(aLSB, aMSB);
}
uint64_t getU64BitReg(int aLSB, int aMSB){
uint64_t getU64BitReg(int aLSB, int aMSB) {
uint64_t retval = bus_r(aMSB);
retval = (retval << 32) | bus_r(aLSB);
return retval;
}
void setU64BitReg(uint64_t value, int aLSB, int aMSB){
void setU64BitReg(uint64_t value, int aLSB, int aMSB) {
bus_w(aLSB, value & (0xffffffff));
bus_w(aMSB, (value >> 32) & (0xffffffff));
}
@@ -110,21 +109,19 @@ int mapCSP0(void) {
return FAIL;
}
LOG(logDEBUG1, ("/dev/mem opened\n"));
csp0base = mmap(0, MEM_SIZE, PROT_READ|PROT_WRITE, MAP_FILE|MAP_SHARED, fd, CSP0);
csp0base = mmap(0, MEM_SIZE, PROT_READ | PROT_WRITE,
MAP_FILE | MAP_SHARED, fd, CSP0);
if (csp0base == MAP_FAILED) {
LOG(logERROR, ("Can't map memmory area\n"));
return FAIL;
}
#endif
LOG(logINFO, ("csp0base mapped from %p to %p\n",
csp0base, (csp0base + MEM_SIZE)));
LOG(logINFO, ("csp0base mapped from %p to %p\n", csp0base,
(csp0base + MEM_SIZE)));
LOG(logINFO, ("Status Register: %08x\n", bus_r(STATUS_REG)));
}else
} else
LOG(logINFO, ("Memory already mapped before\n"));
return OK;
}
uint32_t* Blackfin_getBaseAddress() {
return csp0base;
}
uint32_t *Blackfin_getBaseAddress() { return csp0base; }

17
slsDetectorServers/slsDetectorServer/src/common.c Executable file → Normal file
View File

@@ -2,13 +2,14 @@
#include "clogger.h"
#include "sls_detector_defs.h"
int ConvertToDifferentRange(int inputMin, int inputMax, int outputMin, int outputMax,
int inputValue, int* outputValue) {
int ConvertToDifferentRange(int inputMin, int inputMax, int outputMin,
int outputMax, int inputValue, int *outputValue) {
LOG(logDEBUG1, (" Input Value: %d (Input:(%d - %d), Output:(%d - %d))\n",
inputValue, inputMin, inputMax, outputMin, outputMax));
// validate within bounds
// eg. MAX1932 range is v(60 - 200) to dac(255 - 1), here inputMin > inputMax (when dac to voltage)
// eg. MAX1932 range is v(60 - 200) to dac(255 - 1), here inputMin >
// inputMax (when dac to voltage)
int smaller = inputMin;
int bigger = inputMax;
if (smaller > bigger) {
@@ -16,13 +17,16 @@ int ConvertToDifferentRange(int inputMin, int inputMax, int outputMin, int outpu
bigger = inputMin;
}
if ((inputValue < smaller) || (inputValue > bigger)) {
LOG(logERROR, ("Input Value is outside bounds (%d to %d): %d\n", smaller, bigger, inputValue));
LOG(logERROR, ("Input Value is outside bounds (%d to %d): %d\n",
smaller, bigger, inputValue));
*outputValue = -1;
return FAIL;
}
double value = ((double)(inputValue - inputMin) * (double)(outputMax - outputMin))
/ (double)(inputMax - inputMin) + outputMin;
double value =
((double)(inputValue - inputMin) * (double)(outputMax - outputMin)) /
(double)(inputMax - inputMin) +
outputMin;
// double to integer conversion (if decimal places, round to integer)
if ((value - (int)value) > 0.0001) {
@@ -33,4 +37,3 @@ int ConvertToDifferentRange(int inputMin, int inputMax, int outputMin, int outpu
LOG(logDEBUG1, (" Converted Output Value: %d\n", *outputValue));
return OK;
}

98
slsDetectorServers/slsDetectorServer/src/commonServerFunctions.c Executable file → Normal file
View File

@@ -4,53 +4,61 @@
#include <unistd.h> // usleep
void SPIChipSelect (uint32_t* valw, uint32_t addr, uint32_t csmask, uint32_t clkmask, uint32_t digoutmask, int convBit) {
LOG(logDEBUG2, ("SPI chip select. valw:0x%08x addr:0x%x csmask:0x%x, clkmask:0x%x digmask:0x%x convbit:%d\n",
void SPIChipSelect(uint32_t *valw, uint32_t addr, uint32_t csmask,
uint32_t clkmask, uint32_t digoutmask, int convBit) {
LOG(logDEBUG2, ("SPI chip select. valw:0x%08x addr:0x%x csmask:0x%x, "
"clkmask:0x%x digmask:0x%x convbit:%d\n",
*valw, addr, csmask, clkmask, digoutmask, convBit));
// start point
if (convBit) {
// needed for the slow adcs for apprx 20 ns before and after rising of convbit (usleep val is vague assumption)
// needed for the slow adcs for apprx 20 ns before and after rising of
// convbit (usleep val is vague assumption)
usleep(20);
// clkmask has to be down for conversion to have correct value (for conv bit = 1)
(*valw) = (((bus_r(addr) | csmask) &(~clkmask)) &(~digoutmask));
// clkmask has to be down for conversion to have correct value (for conv
// bit = 1)
(*valw) = (((bus_r(addr) | csmask) & (~clkmask)) & (~digoutmask));
} else {
(*valw) = ((bus_r(addr) | csmask | clkmask) &(~digoutmask));
(*valw) = ((bus_r(addr) | csmask | clkmask) & (~digoutmask));
}
bus_w (addr, (*valw));
bus_w(addr, (*valw));
LOG(logDEBUG2, ("startpoint. valw:0x%08x\n", *valw));
// needed for the slow adcs for apprx 10 ns before and after rising of convbit (usleep val is vague assumption)
// needed for the slow adcs for apprx 10 ns before and after rising of
// convbit (usleep val is vague assumption)
if (convBit)
usleep(10);
// chip sel bar down
(*valw) &= ~csmask;
bus_w (addr, (*valw));
bus_w(addr, (*valw));
LOG(logDEBUG2, ("chip sel bar down. valw:0x%08x\n", *valw));
}
void SPIChipDeselect (uint32_t* valw, uint32_t addr, uint32_t csmask, uint32_t clkmask, uint32_t digoutmask, int convBit) {
LOG(logDEBUG2, ("SPI chip deselect. valw:0x%08x addr:0x%x csmask:0x%x, clkmask:0x%x digmask:0x%x convbit:%d\n",
void SPIChipDeselect(uint32_t *valw, uint32_t addr, uint32_t csmask,
uint32_t clkmask, uint32_t digoutmask, int convBit) {
LOG(logDEBUG2, ("SPI chip deselect. valw:0x%08x addr:0x%x csmask:0x%x, "
"clkmask:0x%x digmask:0x%x convbit:%d\n",
*valw, addr, csmask, clkmask, digoutmask, convBit));
// needed for the slow adcs for apprx 20 ns before and after rising of convbit (usleep val is vague assumption)
// needed for the slow adcs for apprx 20 ns before and after rising of
// convbit (usleep val is vague assumption)
if (convBit)
usleep(20);
// chip sel bar up
(*valw) |= csmask;
bus_w (addr, (*valw));
bus_w(addr, (*valw));
LOG(logDEBUG2, ("chip sel bar up. valw:0x%08x\n", *valw));
// needed for the slow adcs for apprx 10 ns before and after rising of convbit (usleep val is vague assumption)
// needed for the slow adcs for apprx 10 ns before and after rising of
// convbit (usleep val is vague assumption)
if (convBit)
usleep(10);
//clk down
// clk down
(*valw) &= ~clkmask;
bus_w (addr, (*valw));
bus_w(addr, (*valw));
LOG(logDEBUG2, ("clk down. valw:0x%08x\n", *valw));
// stop point = start point of course
@@ -61,12 +69,18 @@ void SPIChipDeselect (uint32_t* valw, uint32_t addr, uint32_t csmask, uint32_t
} else {
(*valw) |= csmask;
}
bus_w (addr, (*valw)); //FIXME: for ctb slow adcs, might need to set it to low again
bus_w(
addr,
(*valw)); // FIXME: for ctb slow adcs, might need to set it to low again
LOG(logDEBUG2, ("stop point. valw:0x%08x\n", *valw));
}
void sendDataToSPI (uint32_t* valw, uint32_t addr, uint32_t val, int numbitstosend, uint32_t clkmask, uint32_t digoutmask, int digofset) {
LOG(logDEBUG2, ("SPI send data. valw:0x%08x addr:0x%x val:0x%x, numbitstosend:%d, clkmask:0x%x digmask:0x%x digofst:%d\n",
void sendDataToSPI(uint32_t *valw, uint32_t addr, uint32_t val,
int numbitstosend, uint32_t clkmask, uint32_t digoutmask,
int digofset) {
LOG(logDEBUG2,
("SPI send data. valw:0x%08x addr:0x%x val:0x%x, numbitstosend:%d, "
"clkmask:0x%x digmask:0x%x digofst:%d\n",
*valw, addr, val, numbitstosend, clkmask, digoutmask, digofset));
int i = 0;
@@ -74,24 +88,27 @@ void sendDataToSPI (uint32_t* valw, uint32_t addr, uint32_t val, int numbitstose
// clk down
(*valw) &= ~clkmask;
bus_w (addr, (*valw));
bus_w(addr, (*valw));
LOG(logDEBUG2, ("clk down. valw:0x%08x\n", *valw));
// write data (i)
(*valw) = (((*valw) & ~digoutmask) + // unset bit
(((val >> (numbitstosend - 1 - i)) & 0x1) << digofset)); // each bit from val starting from msb
bus_w (addr, (*valw));
(((val >> (numbitstosend - 1 - i)) & 0x1)
<< digofset)); // each bit from val starting from msb
bus_w(addr, (*valw));
LOG(logDEBUG2, ("write data %d. valw:0x%08x\n", i, *valw));
// clk up
(*valw) |= clkmask ;
bus_w (addr, (*valw));
(*valw) |= clkmask;
bus_w(addr, (*valw));
LOG(logDEBUG2, ("clk up. valw:0x%08x\n", *valw));
}
}
uint32_t receiveDataFromSPI (uint32_t* valw, uint32_t addr, int numbitstoreceive, uint32_t clkmask, uint32_t readaddr) {
LOG(logDEBUG2, ("SPI send data. valw:0x%08x addr:0x%x numbitstoreceive:%d, clkmask:0x%x readaddr:0x%x \n",
uint32_t receiveDataFromSPI(uint32_t *valw, uint32_t addr, int numbitstoreceive,
uint32_t clkmask, uint32_t readaddr) {
LOG(logDEBUG2, ("SPI send data. valw:0x%08x addr:0x%x numbitstoreceive:%d, "
"clkmask:0x%x readaddr:0x%x \n",
*valw, addr, numbitstoreceive, clkmask, readaddr));
uint32_t retval = 0;
@@ -101,7 +118,7 @@ uint32_t receiveDataFromSPI (uint32_t* valw, uint32_t addr, int numbitstoreceive
// clk down
(*valw) &= ~clkmask;
bus_w (addr, (*valw));
bus_w(addr, (*valw));
LOG(logDEBUG2, ("clk down. valw:0x%08x\n", *valw));
// read data (i)
@@ -111,8 +128,8 @@ uint32_t receiveDataFromSPI (uint32_t* valw, uint32_t addr, int numbitstoreceive
usleep(20);
// clk up
(*valw) |= clkmask ;
bus_w (addr, (*valw));
(*valw) |= clkmask;
bus_w(addr, (*valw));
LOG(logDEBUG2, ("clk up. valw:0x%08x\n", *valw));
usleep(20);
@@ -121,7 +138,9 @@ uint32_t receiveDataFromSPI (uint32_t* valw, uint32_t addr, int numbitstoreceive
return retval;
}
void serializeToSPI(uint32_t addr, uint32_t val, uint32_t csmask, int numbitstosend, uint32_t clkmask, uint32_t digoutmask, int digofset, int convBit) {
void serializeToSPI(uint32_t addr, uint32_t val, uint32_t csmask,
int numbitstosend, uint32_t clkmask, uint32_t digoutmask,
int digofset, int convBit) {
if (numbitstosend == 16) {
LOG(logDEBUG2, ("Writing to SPI Register: 0x%04x\n", val));
} else {
@@ -129,23 +148,28 @@ void serializeToSPI(uint32_t addr, uint32_t val, uint32_t csmask, int numbitstos
}
uint32_t valw;
SPIChipSelect (&valw, addr, csmask, clkmask, digoutmask, convBit);
SPIChipSelect(&valw, addr, csmask, clkmask, digoutmask, convBit);
sendDataToSPI(&valw, addr, val, numbitstosend, clkmask, digoutmask, digofset);
sendDataToSPI(&valw, addr, val, numbitstosend, clkmask, digoutmask,
digofset);
SPIChipDeselect(&valw, addr, csmask, clkmask, digoutmask, convBit);
}
uint32_t serializeFromSPI(uint32_t addr, uint32_t csmask, int numbitstoreceive, uint32_t clkmask, uint32_t digoutmask, uint32_t readaddr, int convBit) {
uint32_t serializeFromSPI(uint32_t addr, uint32_t csmask, int numbitstoreceive,
uint32_t clkmask, uint32_t digoutmask,
uint32_t readaddr, int convBit) {
uint32_t valw;
SPIChipSelect (&valw, addr, csmask, clkmask, digoutmask, convBit);
SPIChipSelect(&valw, addr, csmask, clkmask, digoutmask, convBit);
uint32_t retval = receiveDataFromSPI(&valw, addr, numbitstoreceive, clkmask, readaddr);
uint32_t retval =
receiveDataFromSPI(&valw, addr, numbitstoreceive, clkmask, readaddr);
// not needed for conv bit (not a chip select)
//SPIChipDeselect(&valw, addr, csmask, clkmask, digoutmask, convBit); // moving this before bringin up earlier changes temp of slow adc
// SPIChipDeselect(&valw, addr, csmask, clkmask, digoutmask, convBit); //
// moving this before bringin up earlier changes temp of slow adc
if (numbitstoreceive == 16) {
LOG(logDEBUG2, ("Read From SPI Register: 0x%04x\n", retval));

274
slsDetectorServers/slsDetectorServer/src/communication_funcs.c Executable file → Normal file
View File

@@ -1,15 +1,13 @@
#include "communication_funcs.h"
#include "clogger.h"
#include <string.h>
#include <errno.h>
#include <arpa/inet.h>
#include <errno.h>
#include <string.h>
#include <sys/select.h>
#include <unistd.h>
#define SEND_REC_MAX_SIZE 4096
#define DEFAULT_PORTNO 1952
#define DEFAULT_BACKLOG 5
@@ -19,9 +17,8 @@
#define CPU_RSND_PCKT_LOOP (10)
#define CPU_RSND_WAIT_US (1)
// Global variables from errno.h
//extern int errno;
// extern int errno;
// Variables that will be exported
int lockStatus = 0;
@@ -41,10 +38,9 @@ fd_set readset, tempset;
// number of socket descrptor listening to
int isock = 0;
// value of socket descriptor,
//becomes max value of socket descriptor (listen) and file descriptor (accept)
// becomes max value of socket descriptor (listen) and file descriptor (accept)
int maxfd = 0;
int bindSocket(unsigned short int port_number) {
ret = FAIL;
int socketDescriptor = -1;
@@ -53,35 +49,39 @@ int bindSocket(unsigned short int port_number) {
// same port
if (myport == port_number) {
sprintf(mess, "Cannot create %s socket with port %d. Already in use before.\n",
(isControlServer ? "control":"stop"), port_number);
sprintf(
mess,
"Cannot create %s socket with port %d. Already in use before.\n",
(isControlServer ? "control" : "stop"), port_number);
LOG(logERROR, (mess));
}
// port ok
else {
// create socket
socketDescriptor = socket(AF_INET, SOCK_STREAM,0);
socketDescriptor = socket(AF_INET, SOCK_STREAM, 0);
// socket error
if (socketDescriptor < 0) {
sprintf(mess, "Cannot create %s socket with port %d\n",
(isControlServer ? "control":"stop"), port_number);
(isControlServer ? "control" : "stop"), port_number);
LOG(logERROR, (mess));
}
// socket success
else {
i = 1;
// set port reusable
setsockopt(socketDescriptor, SOL_SOCKET, SO_REUSEADDR, &i, sizeof(i));
setsockopt(socketDescriptor, SOL_SOCKET, SO_REUSEADDR, &i,
sizeof(i));
// Set some fields in the serverAddress structure
addressS.sin_family = AF_INET;
addressS.sin_addr.s_addr = htonl(INADDR_ANY);
addressS.sin_port = htons(port_number);
// bind socket error
if(bind(socketDescriptor,(struct sockaddr *) &addressS,sizeof(addressS)) < 0){
if (bind(socketDescriptor, (struct sockaddr *)&addressS,
sizeof(addressS)) < 0) {
sprintf(mess, "Cannot bind %s socket to port %d.\n",
(isControlServer ? "control":"stop"), port_number);
(isControlServer ? "control" : "stop"), port_number);
LOG(logERROR, (mess));
}
// bind socket ok
@@ -100,14 +100,17 @@ int bindSocket(unsigned short int port_number) {
// success
myport = port_number;
ret = OK;
LOG(logDEBUG1, ("%s socket bound: isock=%d, port=%d, fd=%d\n",
(isControlServer ? "Control":"Stop"), isock, port_number, socketDescriptor));
LOG(logDEBUG1,
("%s socket bound: isock=%d, port=%d, fd=%d\n",
(isControlServer ? "Control" : "Stop"), isock,
port_number, socketDescriptor));
}
// listen socket error
else {
sprintf(mess, "Cannot bind %s socket to port %d.\n",
(isControlServer ? "control":"stop"), port_number);
(isControlServer ? "control" : "stop"),
port_number);
LOG(logERROR, (mess));
}
}
@@ -117,8 +120,6 @@ int bindSocket(unsigned short int port_number) {
return socketDescriptor;
}
int acceptConnection(int socketDescriptor) {
int j;
struct sockaddr_in addressC;
@@ -142,36 +143,40 @@ int acceptConnection(int socketDescriptor) {
// timeout
if (result == 0) {
LOG(logDEBUG3, ("%s socket select() timed out!\n",
(isControlServer ? "control":"stop"), myport));
(isControlServer ? "control" : "stop"), myport));
}
// error (not signal caught)
else if (result < 0 && errno != EINTR) {
LOG(logERROR, ("%s socket select() error: %s\n",
(isControlServer ? "control":"stop"), myport, strerror(errno)));
LOG(logERROR,
("%s socket select() error: %s\n",
(isControlServer ? "control" : "stop"), myport, strerror(errno)));
}
// activity in descriptor set
else if (result > 0) {
LOG(logDEBUG3, ("%s select returned!\n", (isControlServer ? "control":"stop")));
LOG(logDEBUG3,
("%s select returned!\n", (isControlServer ? "control" : "stop")));
// loop through the file descriptor set
for (j = 0; j < maxfd + 1; ++j) {
// checks if file descriptor part of set
if (FD_ISSET(j, &tempset)) {
LOG(logDEBUG3, ("fd %d is set\n",j));
LOG(logDEBUG3, ("fd %d is set\n", j));
// clear the temporary set
FD_CLR(j, &tempset);
// accept connection (if error)
if ((file_des = accept(j,(struct sockaddr *) &addressC, &address_length)) < 0) {
LOG(logERROR, ("%s socket accept() error. Connection refused.\n",
if ((file_des = accept(j, (struct sockaddr *)&addressC,
&address_length)) < 0) {
LOG(logERROR,
("%s socket accept() error. Connection refused.\n",
"Error Number: %d, Message: %s\n",
(isControlServer ? "control":"stop"),
myport, errno, strerror(errno)));
switch(errno) {
(isControlServer ? "control" : "stop"), myport, errno,
strerror(errno)));
switch (errno) {
case EWOULDBLOCK:
LOG(logERROR, ("ewouldblock eagain"));
break;
@@ -222,15 +227,17 @@ int acceptConnection(int socketDescriptor) {
else {
char buf[INET_ADDRSTRLEN] = "";
memset(buf, 0, INET_ADDRSTRLEN);
inet_ntop(AF_INET, &(addressC.sin_addr), buf, INET_ADDRSTRLEN);
LOG(logDEBUG3, ("%s socket accepted connection, fd= %d\n",
(isControlServer ? "control":"stop"), file_des));
inet_ntop(AF_INET, &(addressC.sin_addr), buf,
INET_ADDRSTRLEN);
LOG(logDEBUG3,
("%s socket accepted connection, fd= %d\n",
(isControlServer ? "control" : "stop"), file_des));
getIpAddressFromString(buf, &dummyClientIP);
// add the file descriptor from accept
FD_SET(file_des, &readset);
maxfd = (maxfd < file_des)?file_des:maxfd;
maxfd = (maxfd < file_des) ? file_des : maxfd;
}
}
}
@@ -238,14 +245,8 @@ int acceptConnection(int socketDescriptor) {
return file_des;
}
void closeConnection(int file_des) {
if(file_des >= 0)
if (file_des >= 0)
close(file_des);
// remove file descriptor from set
FD_CLR(file_des, &readset);
@@ -255,34 +256,34 @@ void exitServer(int socketDescriptor) {
if (socketDescriptor >= 0) {
close(socketDescriptor);
}
LOG(logINFO, ("Closing %s server\n", (isControlServer ? "control":"stop")));
LOG(logINFO,
("Closing %s server\n", (isControlServer ? "control" : "stop")));
FD_CLR(socketDescriptor, &readset);
isock--;
fflush(stdout);
}
void swapData(void* val,int length,intType itype){
void swapData(void *val, int length, intType itype) {
int i;
int16_t* c = (int16_t*)val;
int32_t* a = (int32_t*)val;
int64_t* b = (int64_t*)val;
for(i = 0; length > 0; i++){
switch(itype){
int16_t *c = (int16_t *)val;
int32_t *a = (int32_t *)val;
int64_t *b = (int64_t *)val;
for (i = 0; length > 0; i++) {
switch (itype) {
case INT16:
c[i] = ((c[i] & 0x00FF) << 8) | ((c[i] & 0xFF00) >> 8);
length -= sizeof(int16_t);
break;
case INT32:
a[i] = ((a[i] << 8) & 0xFF00FF00) | ((a[i] >> 8) & 0xFF00FF );
a[i] = ((a[i] << 8) & 0xFF00FF00) | ((a[i] >> 8) & 0xFF00FF);
a[i] = (a[i] << 16) | ((a[i] >> 16) & 0xFFFF);
length -= sizeof(int32_t);
break;
case INT64:
b[i] = ((b[i] << 8) & 0xFF00FF00FF00FF00ULL ) | ((b[i] >> 8) & 0x00FF00FF00FF00FFULL );
b[i] = ((b[i] << 16) & 0xFFFF0000FFFF0000ULL ) | ((b[i] >> 16) & 0x0000FFFF0000FFFFULL );
b[i] = ((b[i] << 8) & 0xFF00FF00FF00FF00ULL) |
((b[i] >> 8) & 0x00FF00FF00FF00FFULL);
b[i] = ((b[i] << 16) & 0xFFFF0000FFFF0000ULL) |
((b[i] >> 16) & 0x0000FFFF0000FFFFULL);
b[i] = (b[i] << 32) | ((b[i] >> 32) & 0xFFFFFFFFULL);
length -= sizeof(int64_t);
break;
@@ -293,7 +294,7 @@ void swapData(void* val,int length,intType itype){
}
}
int sendData(int file_des, void* buf,int length, intType itype){
int sendData(int file_des, void *buf, int length, intType itype) {
#ifndef PCCOMPILE
#ifdef EIGERD
swapData(buf, length, itype);
@@ -302,49 +303,53 @@ int sendData(int file_des, void* buf,int length, intType itype){
return sendDataOnly(file_des, buf, length);
}
int receiveData(int file_des, void* buf,int length, intType itype){
int receiveData(int file_des, void *buf, int length, intType itype) {
int lret = receiveDataOnly(file_des, buf, length);
#ifndef PCCOMPILE
#ifdef EIGERD
if (lret >= 0) swapData(buf, length, itype);
if (lret >= 0)
swapData(buf, length, itype);
#endif
#endif
return lret;
}
int sendDataOnly(int file_des, void* buf,int length) {
int sendDataOnly(int file_des, void *buf, int length) {
if (!length)
return 0;
int bytesSent = 0;
int retry = 0; // retry index when buffer is blocked (write returns 0)
while (bytesSent < length) {
// setting a max packet size for blackfin driver (and network driver does not do a check if packets sent)
// setting a max packet size for blackfin driver (and network driver
// does not do a check if packets sent)
int bytesToSend = length - bytesSent;
if (bytesToSend > CPU_DRVR_SND_LMT)
bytesToSend = CPU_DRVR_SND_LMT;
// send
int rc = write(file_des, (char*)((char*)buf + bytesSent), bytesToSend);
int rc =
write(file_des, (char *)((char *)buf + bytesSent), bytesToSend);
// error
if (rc < 0) {
LOG(logERROR, ("Could not write to %s socket. Possible socket crash\n",
(isControlServer ? "control":"stop")));
LOG(logERROR,
("Could not write to %s socket. Possible socket crash\n",
(isControlServer ? "control" : "stop")));
return bytesSent;
}
// also error, wrote nothing, buffer blocked up, too fast sending for client
// also error, wrote nothing, buffer blocked up, too fast sending for
// client
if (rc == 0) {
LOG(logERROR, ("Could not write to %s socket. Buffer full. Retry: %d\n",
(isControlServer ? "control":"stop"), retry));
LOG(logERROR,
("Could not write to %s socket. Buffer full. Retry: %d\n",
(isControlServer ? "control" : "stop"), retry));
++retry;
// wrote nothing for many loops
if (retry >= CPU_RSND_PCKT_LOOP) {
LOG(logERROR, ("Could not write to %s socket. Buffer full! Too fast! No more.\n",
(isControlServer ? "control":"stop")));
LOG(logERROR, ("Could not write to %s socket. Buffer full! Too "
"fast! No more.\n",
(isControlServer ? "control" : "stop")));
return bytesSent;
}
usleep(CPU_RSND_WAIT_US);
@@ -353,8 +358,10 @@ int sendDataOnly(int file_des, void* buf,int length) {
else {
retry = 0;
if (rc != bytesToSend) {
LOG(logWARNING, ("Only partial write to %s socket. Expected to write %d bytes, wrote %d\n",
(isControlServer ? "control":"stop"), bytesToSend, rc));
LOG(logWARNING,
("Only partial write to %s socket. Expected to write %d "
"bytes, wrote %d\n",
(isControlServer ? "control" : "stop"), bytesToSend, rc));
}
}
bytesSent += rc;
@@ -363,22 +370,24 @@ int sendDataOnly(int file_des, void* buf,int length) {
return bytesSent;
}
int receiveDataOnly(int file_des, void* buf,int length) {
int receiveDataOnly(int file_des, void *buf, int length) {
int total_received = 0;
int nreceiving;
int nreceived;
if (file_des<0) return -1;
LOG(logDEBUG3, ("want to receive %d Bytes to %s server\n",
length, (isControlServer ? "control":"stop")));
if (file_des < 0)
return -1;
LOG(logDEBUG3, ("want to receive %d Bytes to %s server\n", length,
(isControlServer ? "control" : "stop")));
while(length > 0) {
nreceiving = (length>SEND_REC_MAX_SIZE) ? SEND_REC_MAX_SIZE:length; // (condition) ? if_true : if_false
nreceived = read(file_des,(char*)buf+total_received,nreceiving);
if(!nreceived){
if(!total_received) {
return -1; //to handle it
while (length > 0) {
nreceiving = (length > SEND_REC_MAX_SIZE)
? SEND_REC_MAX_SIZE
: length; // (condition) ? if_true : if_false
nreceived = read(file_des, (char *)buf + total_received, nreceiving);
if (!nreceived) {
if (!total_received) {
return -1; // to handle it
}
break;
}
@@ -386,24 +395,21 @@ int receiveDataOnly(int file_des, void* buf,int length) {
total_received += nreceived;
}
if (total_received>0)
if (total_received > 0)
thisClientIP = dummyClientIP;
if (lastClientIP != thisClientIP) {
differentClients = 1;
}
else
} else
differentClients = 0;
return total_received;
}
int sendModule(int file_des, sls_detector_module *myMod) {
int ts = 0, n = 0;
n = sendData(file_des,&(myMod->serialnumber),sizeof(myMod->serialnumber),INT32);
n = sendData(file_des, &(myMod->serialnumber), sizeof(myMod->serialnumber),
INT32);
if (!n) {
return -1;
}
@@ -428,8 +434,7 @@ int sendModule(int file_des, sls_detector_module *myMod) {
return -1;
}
ts += n;
n = sendData(file_des, &(myMod->iodelay), sizeof(myMod->iodelay),
INT32);
n = sendData(file_des, &(myMod->iodelay), sizeof(myMod->iodelay), INT32);
if (!n) {
return -1;
}
@@ -445,7 +450,7 @@ int sendModule(int file_des, sls_detector_module *myMod) {
}
ts += n;
// dacs
n = sendData(file_des,myMod->dacs, sizeof(int)*(myMod->ndac), INT32);
n = sendData(file_des, myMod->dacs, sizeof(int) * (myMod->ndac), INT32);
if (!n) {
return -1;
}
@@ -463,18 +468,17 @@ int sendModule(int file_des, sls_detector_module *myMod) {
return ts;
}
int receiveModule(int file_des, sls_detector_module* myMod) {
int receiveModule(int file_des, sls_detector_module *myMod) {
enum TLogLevel level = logDEBUG1;
LOG(level, ("Receiving Module\n"));
int ts = 0, n = 0;
int nDacs = myMod->ndac;
#ifdef EIGERD
int nChans = myMod->nchan; // can be zero for no trimbits
LOG(level, ("nChans: %d\n",nChans));
LOG(level, ("nChans: %d\n", nChans));
#endif
n = receiveData(file_des,&(myMod->serialnumber), sizeof(myMod->serialnumber), INT32);
n = receiveData(file_des, &(myMod->serialnumber),
sizeof(myMod->serialnumber), INT32);
if (!n) {
return -1;
}
@@ -486,36 +490,32 @@ int receiveModule(int file_des, sls_detector_module* myMod) {
return -1;
}
ts += n;
LOG(level,
("nchan received. %d bytes. nchan: %d\n", n, myMod->nchan));
LOG(level, ("nchan received. %d bytes. nchan: %d\n", n, myMod->nchan));
n = receiveData(file_des, &(myMod->nchip), sizeof(myMod->nchip), INT32);
if (!n) {
return -1;
}
ts += n;
LOG(level,
("nchip received. %d bytes. nchip: %d\n", n, myMod->nchip));
LOG(level, ("nchip received. %d bytes. nchip: %d\n", n, myMod->nchip));
n = receiveData(file_des, &(myMod->ndac), sizeof(myMod->ndac), INT32);
if (!n) {
return -1;
}
ts += n;
LOG(level,
("ndac received. %d bytes. ndac: %d\n", n, myMod->ndac));
LOG(level, ("ndac received. %d bytes. ndac: %d\n", n, myMod->ndac));
n = receiveData(file_des, &(myMod->reg), sizeof(myMod->reg), INT32);
if (!n) {
return -1;
}
ts += n;
LOG(level, ("reg received. %d bytes. reg: %d\n", n, myMod->reg));
n = receiveData(file_des, &(myMod->iodelay), sizeof(myMod->iodelay),
INT32);
n = receiveData(file_des, &(myMod->iodelay), sizeof(myMod->iodelay), INT32);
if (!n) {
return -1;
}
ts += n;
LOG(level, ("iodelay received. %d bytes. iodelay: %d\n", n,
myMod->iodelay));
LOG(level,
("iodelay received. %d bytes. iodelay: %d\n", n, myMod->iodelay));
n = receiveData(file_des, &(myMod->tau), sizeof(myMod->tau), INT32);
if (!n) {
return -1;
@@ -543,46 +543,46 @@ int receiveModule(int file_des, sls_detector_module* myMod) {
LOG(level, ("dacs received. %d bytes.\n", n));
// channels
#ifdef EIGERD
if (((myMod->nchan) != 0 ) && // no trimbits
if (((myMod->nchan) != 0) && // no trimbits
(nChans != (myMod->nchan))) { // with trimbits
LOG(logERROR, ("received wrong number of channels. "
"Expected %d, got %d\n", nChans, (myMod->nchan)));
"Expected %d, got %d\n",
nChans, (myMod->nchan)));
return 0;
}
n = receiveData(file_des, myMod->chanregs, sizeof(int) * (myMod->nchan), INT32);
n = receiveData(file_des, myMod->chanregs, sizeof(int) * (myMod->nchan),
INT32);
LOG(level, ("chanregs received. %d bytes.\n", n));
if (!n && myMod->nchan != 0){
if (!n && myMod->nchan != 0) {
return -1;
}
ts += n;
#endif
LOG(level, ("received module of size %d register %x\n",ts,myMod->reg));
LOG(level, ("received module of size %d register %x\n", ts, myMod->reg));
return ts;
}
void Server_LockedError() {
ret = FAIL;
char buf[INET_ADDRSTRLEN] = "";
getIpAddressinString(buf, dummyClientIP);
sprintf(mess,"Detector locked by %s\n", buf);
sprintf(mess, "Detector locked by %s\n", buf);
LOG(logWARNING, (mess));
}
int Server_VerifyLock() {
if (differentClients && lockStatus)
Server_LockedError();
return ret;
}
int Server_SendResult(int fileDes, intType itype, void* retval, int retvalSize) {
int Server_SendResult(int fileDes, intType itype, void *retval,
int retvalSize) {
// send success of operation
int ret1 = ret;
sendData(fileDes, &ret1,sizeof(ret1), INT32);
if(ret == FAIL) {
sendData(fileDes, &ret1, sizeof(ret1), INT32);
if (ret == FAIL) {
// send error message
if (strlen(mess))
sendData(fileDes, mess, MAX_STR_LENGTH, OTHER);
@@ -590,7 +590,7 @@ int Server_SendResult(int fileDes, intType itype, void* retval, int retvalSize)
else
LOG(logERROR, ("No error message provided for this failure in %s "
"server. Will mess up TCP.\n",
(isControlServer ? "control":"stop")));
(isControlServer ? "control" : "stop")));
}
// send return value
sendData(fileDes, retval, retvalSize, itype);
@@ -598,37 +598,33 @@ int Server_SendResult(int fileDes, intType itype, void* retval, int retvalSize)
return ret;
}
void getMacAddressinString(char* cmac, int size, uint64_t mac) {
void getMacAddressinString(char *cmac, int size, uint64_t mac) {
memset(cmac, 0, size);
sprintf(cmac,"%02x:%02x:%02x:%02x:%02x:%02x",
(unsigned int)((mac>>40)&0xFF),
(unsigned int)((mac>>32)&0xFF),
(unsigned int)((mac>>24)&0xFF),
(unsigned int)((mac>>16)&0xFF),
(unsigned int)((mac>>8)&0xFF),
(unsigned int)((mac>>0)&0xFF));
sprintf(
cmac, "%02x:%02x:%02x:%02x:%02x:%02x",
(unsigned int)((mac >> 40) & 0xFF), (unsigned int)((mac >> 32) & 0xFF),
(unsigned int)((mac >> 24) & 0xFF), (unsigned int)((mac >> 16) & 0xFF),
(unsigned int)((mac >> 8) & 0xFF), (unsigned int)((mac >> 0) & 0xFF));
}
void getIpAddressinString(char* cip, uint32_t ip) {
void getIpAddressinString(char *cip, uint32_t ip) {
memset(cip, 0, INET_ADDRSTRLEN);
#if defined(EIGERD) && !defined(VIRTUAL)
inet_ntop(AF_INET, &ip, cip, INET_ADDRSTRLEN);
#else
sprintf(cip, "%d.%d.%d.%d",
(ip>>24)&0xff,(ip>>16)&0xff,(ip>>8)&0xff,(ip)&0xff);
sprintf(cip, "%d.%d.%d.%d", (ip >> 24) & 0xff, (ip >> 16) & 0xff,
(ip >> 8) & 0xff, (ip)&0xff);
#endif
}
void getIpAddressFromString(char* cip, uint32_t* ip) {
char buf[INET_ADDRSTRLEN]="";
void getIpAddressFromString(char *cip, uint32_t *ip) {
char buf[INET_ADDRSTRLEN] = "";
memset(buf, 0, INET_ADDRSTRLEN);
char* byte = strtok (cip,".");
char *byte = strtok(cip, ".");
while (byte != NULL) {
sprintf(cip,"%02x",atoi(byte));
sprintf(cip, "%02x", atoi(byte));
strcat(buf, cip);
byte = strtok (NULL, ".");
byte = strtok(NULL, ".");
}
sscanf(buf, "%x", ip);
}

67
slsDetectorServers/slsDetectorServer/src/communication_funcs_UDP.c Executable file → Normal file
View File

@@ -2,32 +2,32 @@
#include "clogger.h"
#include "sls_detector_defs.h"
#include <stdio.h>
#include <stdlib.h>
#include <sys/types.h>
#include <sys/socket.h>
#include <arpa/inet.h>
#include <netinet/in.h>
#include <string.h>
#include <unistd.h>
#include <errno.h>
#include <netdb.h>
#include <netinet/in.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <sys/socket.h>
#include <sys/types.h>
#include <unistd.h>
int udpSockfd[2] = {-1, -1};
struct addrinfo* udpServerAddrInfo[2] = {0, 0};
struct addrinfo *udpServerAddrInfo[2] = {0, 0};
unsigned short int udpDestinationPort[2] = {0, 0};
char udpDestinationIp[2][INET_ADDRSTRLEN] = {"", ""};
//DEFAULT_TX_UDP_PORT;// src port
int getUdPSocketDescriptor(int index) {
return udpSockfd[index];
}
// DEFAULT_TX_UDP_PORT;// src port
int getUdPSocketDescriptor(int index) { return udpSockfd[index]; }
int setUDPDestinationDetails(int index, const char* ip, unsigned short int port) {
int setUDPDestinationDetails(int index, const char *ip,
unsigned short int port) {
udpDestinationPort[index] = port;
size_t len = strlen(ip);
memset(udpDestinationIp[index], 0, INET_ADDRSTRLEN);
strncpy(udpDestinationIp[index], ip, len > INET_ADDRSTRLEN ? INET_ADDRSTRLEN : len );
strncpy(udpDestinationIp[index], ip,
len > INET_ADDRSTRLEN ? INET_ADDRSTRLEN : len);
if (udpServerAddrInfo[index]) {
freeaddrinfo(udpServerAddrInfo[index]);
@@ -44,15 +44,19 @@ int setUDPDestinationDetails(int index, const char* ip, unsigned short int port)
char sport[100];
memset(sport, 0, 100);
sprintf(sport, "%d", udpDestinationPort[index]);
int err = getaddrinfo(udpDestinationIp[index], sport, &hints, &udpServerAddrInfo[index]);
int err = getaddrinfo(udpDestinationIp[index], sport, &hints,
&udpServerAddrInfo[index]);
if (err != 0) {
LOG(logERROR, ("Failed to resolve remote socket address %s at port %d. "
"(Error code:%d, %s)\n", udpDestinationIp[index], udpDestinationPort[index], err, gai_strerror(err)));
"(Error code:%d, %s)\n",
udpDestinationIp[index], udpDestinationPort[index], err,
gai_strerror(err)));
return FAIL;
}
if (udpServerAddrInfo[index] == NULL) {
LOG(logERROR, ("Failed to resolve remote socket address %s at port %d "
"(getaddrinfo returned NULL)\n", udpDestinationIp[index], udpDestinationPort[index]));
"(getaddrinfo returned NULL)\n",
udpDestinationIp[index], udpDestinationPort[index]));
udpServerAddrInfo[index] = 0;
return FAIL;
}
@@ -68,14 +72,17 @@ int createUDPSocket(int index) {
}
if (udpSockfd[index] != -1) {
LOG(logERROR, ("Strange that Udp socket was still open. Closing it to create a new one\n"));
LOG(logERROR, ("Strange that Udp socket was still open. Closing it to "
"create a new one\n"));
close(udpSockfd[index]);
udpSockfd[index] = -1;
}
// Creating socket file descriptor
udpSockfd[index] = socket(udpServerAddrInfo[index]->ai_family, udpServerAddrInfo[index]->ai_socktype, udpServerAddrInfo[index]->ai_protocol);
if (udpSockfd[index] == -1 ) {
udpSockfd[index] = socket(udpServerAddrInfo[index]->ai_family,
udpServerAddrInfo[index]->ai_socktype,
udpServerAddrInfo[index]->ai_protocol);
if (udpSockfd[index] == -1) {
LOG(logERROR, ("UDP socket at port %d failed. (Error code:%d, %s)\n",
udpDestinationPort[index], errno, gai_strerror(errno)));
return FAIL;
@@ -83,19 +90,23 @@ int createUDPSocket(int index) {
LOG(logINFO, ("Udp client socket created for server (port %d, ip:%s)\n",
udpDestinationPort[index], udpDestinationIp[index]));
// Using connect expects that the receiver (udp server) exists to listen to these packets
// connecting allows to use "send/write" instead of "sendto", avoiding checking for server address for each packet
// using write without a connect will end in segv
LOG(logINFO, ("Udp client socket connected\n",
udpDestinationPort[index], udpDestinationIp[index]));
// Using connect expects that the receiver (udp server) exists to listen to
// these packets connecting allows to use "send/write" instead of "sendto",
// avoiding checking for server address for each packet using write without
// a connect will end in segv
LOG(logINFO, ("Udp client socket connected\n", udpDestinationPort[index],
udpDestinationIp[index]));
return OK;
}
int sendUDPPacket(int index, const char* buf, int length) {
int n = sendto(udpSockfd[index], buf, length, 0, udpServerAddrInfo[index]->ai_addr, udpServerAddrInfo[index]->ai_addrlen);
int sendUDPPacket(int index, const char *buf, int length) {
int n = sendto(udpSockfd[index], buf, length, 0,
udpServerAddrInfo[index]->ai_addr,
udpServerAddrInfo[index]->ai_addrlen);
// udp sends atomically, no need to handle partial data
if (n == -1) {
LOG(logERROR, ("Could not send udp packet for socket %d. (Error code:%d, %s)\n",
LOG(logERROR,
("Could not send udp packet for socket %d. (Error code:%d, %s)\n",
index, n, errno, gai_strerror(errno)));
} else {
LOG(logDEBUG2, ("%d bytes sent\n", n));

15
slsDetectorServers/slsDetectorServer/src/communication_virtual.c Executable file → Normal file
View File

@@ -11,7 +11,7 @@
#define FD_STOP 1
#define FILE_NAME_LENGTH 1000
FILE* fd[2] = {NULL, NULL};
FILE *fd[2] = {NULL, NULL};
char fnameStatus[FILE_NAME_LENGTH];
char fnameStop[FILE_NAME_LENGTH];
int portNumber = 0;
@@ -21,7 +21,7 @@ int ComVirtual_createFiles(const int port) {
// control server writign status file
memset(fnameStatus, 0, FILE_NAME_LENGTH);
sprintf(fnameStatus, "%s%d", FILE_STATUS, port);
FILE* fd = NULL;
FILE *fd = NULL;
if (NULL == (fd = fopen(fnameStatus, "w"))) {
LOG(logERROR, ("Could not open the file %s for virtual communication\n",
fnameStatus));
@@ -80,8 +80,9 @@ int ComVirtual_getStop() {
return retval;
}
int ComVirtual_writeToFile(int value, const char* fname, const char* serverName) {
FILE* fd = NULL;
int ComVirtual_writeToFile(int value, const char *fname,
const char *serverName) {
FILE *fd = NULL;
if (NULL == (fd = fopen(fname, "w"))) {
LOG(logERROR, ("Vritual %s Server [%d] could not open "
"the file %s for writing\n",
@@ -98,8 +99,9 @@ int ComVirtual_writeToFile(int value, const char* fname, const char* serverName)
return 1;
}
int ComVirtual_readFromFile(int* value, const char* fname, const char* serverName) {
FILE* fd = NULL;
int ComVirtual_readFromFile(int *value, const char *fname,
const char *serverName) {
FILE *fd = NULL;
if (NULL == (fd = fopen(fname, "r"))) {
LOG(logERROR, ("Vritual %s Server [%d] could not open "
"the file %s for reading\n",
@@ -116,5 +118,4 @@ int ComVirtual_readFromFile(int* value, const char* fname, const char* serverNam
return 1;
}
#endif

89
slsDetectorServers/slsDetectorServer/src/nios.c Executable file → Normal file
View File

@@ -1,94 +1,93 @@
#include "nios.h"
#include "RegisterDefs.h"
#include "sls_detector_defs.h"
#include "ansi.h"
#include "clogger.h"
#include "sls_detector_defs.h"
#include <fcntl.h> // open
#include <sys/mman.h> // mmap
/* global variables */
u_int32_t* csp0base = 0;
u_int32_t *csp0base = 0;
#define CSP0 0x18060000
#define MEM_SIZE 0x100000 //TODO (1804 0000 - 1804 07FF = 800 * 4 = 2000), (1806 0000 = 10000* 4 = 40000)
#define MEM_SIZE \
0x100000 // TODO (1804 0000 - 1804 07FF = 800 * 4 = 2000), (1806 0000 =
// 10000* 4 = 40000)
u_int32_t* csp1base = 0;
u_int32_t *csp1base = 0;
#define CSP1 0x18040000
void bus_w_csp1(u_int32_t offset, u_int32_t data) {
volatile u_int32_t *ptr1;
ptr1=(u_int32_t*)(csp1base + offset/(sizeof(u_int32_t)));
*ptr1=data;
ptr1 = (u_int32_t *)(csp1base + offset / (sizeof(u_int32_t)));
*ptr1 = data;
}
u_int32_t bus_r_csp1(u_int32_t offset) {
volatile u_int32_t *ptr1;
ptr1=(u_int32_t*)(csp1base + offset/(sizeof(u_int32_t)));
ptr1 = (u_int32_t *)(csp1base + offset / (sizeof(u_int32_t)));
return *ptr1;
}
void bus_w(u_int32_t offset, u_int32_t data) {
volatile u_int32_t *ptr1;
ptr1=(u_int32_t*)(csp0base + offset/(sizeof(u_int32_t)));
*ptr1=data;
ptr1 = (u_int32_t *)(csp0base + offset / (sizeof(u_int32_t)));
*ptr1 = data;
}
u_int32_t bus_r(u_int32_t offset) {
volatile u_int32_t *ptr1;
ptr1=(u_int32_t*)(csp0base + offset/(sizeof(u_int32_t)));
ptr1 = (u_int32_t *)(csp0base + offset / (sizeof(u_int32_t)));
return *ptr1;
}
int64_t get64BitReg(int aLSB, int aMSB){
int64_t get64BitReg(int aLSB, int aMSB) {
int64_t v64;
u_int32_t vLSB,vMSB;
vLSB=bus_r(aLSB);
vMSB=bus_r(aMSB);
v64=vMSB;
v64=(v64<<32) | vLSB;
LOG(logDEBUG5, (" reg64(%x,%x) %x %x %llx\n", aLSB, aMSB, vLSB, vMSB, (long long unsigned int)v64));
u_int32_t vLSB, vMSB;
vLSB = bus_r(aLSB);
vMSB = bus_r(aMSB);
v64 = vMSB;
v64 = (v64 << 32) | vLSB;
LOG(logDEBUG5, (" reg64(%x,%x) %x %x %llx\n", aLSB, aMSB, vLSB, vMSB,
(long long unsigned int)v64));
return v64;
}
int64_t set64BitReg(int64_t value, int aLSB, int aMSB){
int64_t set64BitReg(int64_t value, int aLSB, int aMSB) {
int64_t v64;
u_int32_t vLSB,vMSB;
if (value!=-1) {
vLSB=value&(0xffffffff);
bus_w(aLSB,vLSB);
v64=value>> 32;
vMSB=v64&(0xffffffff);
bus_w(aMSB,vMSB);
u_int32_t vLSB, vMSB;
if (value != -1) {
vLSB = value & (0xffffffff);
bus_w(aLSB, vLSB);
v64 = value >> 32;
vMSB = v64 & (0xffffffff);
bus_w(aMSB, vMSB);
}
return get64BitReg(aLSB, aMSB);
}
uint64_t getU64BitReg(int aLSB, int aMSB){
uint64_t getU64BitReg(int aLSB, int aMSB) {
uint64_t retval = bus_r(aMSB);
retval = (retval << 32) | bus_r(aLSB);
return retval;
}
void setU64BitReg(uint64_t value, int aLSB, int aMSB){
void setU64BitReg(uint64_t value, int aLSB, int aMSB) {
bus_w(aLSB, value & (0xffffffff));
bus_w(aMSB, (value >> 32) & (0xffffffff));
}
u_int32_t readRegister(u_int32_t offset) {
return bus_r(offset);
}
u_int32_t readRegister(u_int32_t offset) { return bus_r(offset); }
u_int32_t writeRegister(u_int32_t offset, u_int32_t data) {
bus_w(offset, data);
return readRegister(offset);
}
int mapCSP0(void) {
u_int32_t csps[2] = {CSP0, CSP1};
u_int32_t** cspbases[2] = {&csp0base, &csp1base};
char names[2][10]={"csp0base","csp1base"};
u_int32_t **cspbases[2] = {&csp0base, &csp1base};
char names[2][10] = {"csp0base", "csp1base"};
int i = 0;
for (i = 0; i < 2; ++i) {
@@ -98,7 +97,8 @@ int mapCSP0(void) {
#ifdef VIRTUAL
*cspbases[i] = malloc(MEM_SIZE);
if (*cspbases[i] == NULL) {
LOG(logERROR, ("Could not allocate virtual memory for %s.\n", names[i]));
LOG(logERROR,
("Could not allocate virtual memory for %s.\n", names[i]));
return FAIL;
}
LOG(logINFO, ("memory allocated for %s\n", names[i]));
@@ -108,24 +108,23 @@ int mapCSP0(void) {
LOG(logERROR, ("Can't find /dev/mem for %s\n", names[i]));
return FAIL;
}
LOG(logDEBUG1, ("/dev/mem opened for %s, (CSP:0x%x)\n", names[i], csps[i]));
*cspbases[i] = (u_int32_t*)mmap(0, MEM_SIZE, PROT_READ|PROT_WRITE, MAP_FILE|MAP_SHARED, fd, csps[i]);
LOG(logDEBUG1,
("/dev/mem opened for %s, (CSP:0x%x)\n", names[i], csps[i]));
*cspbases[i] =
(u_int32_t *)mmap(0, MEM_SIZE, PROT_READ | PROT_WRITE,
MAP_FILE | MAP_SHARED, fd, csps[i]);
if (*cspbases[i] == MAP_FAILED) {
LOG(logERROR, ("Can't map memmory area for %s\n", names[i]));
return FAIL;
}
#endif
LOG(logINFO, ("%s mapped from %p to %p,(CSP:0x%x) \n",
names[i], *cspbases[i], *cspbases[i]+MEM_SIZE, csps[i]));
//LOG(logINFO, ("Status Register: %08x\n", bus_r(STATUS_REG)));
LOG(logINFO, ("%s mapped from %p to %p,(CSP:0x%x) \n", names[i],
*cspbases[i], *cspbases[i] + MEM_SIZE, csps[i]));
// LOG(logINFO, ("Status Register: %08x\n", bus_r(STATUS_REG)));
} else
LOG(logINFO, ("Memory %s already mapped before\n", names[i]));
}
return OK;
}
u_int32_t* Nios_getBaseAddress() {
return csp0base;
}
u_int32_t *Nios_getBaseAddress() { return csp0base; }

89
slsDetectorServers/slsDetectorServer/src/programFpgaBlackfin.c Executable file → Normal file
View File

@@ -3,9 +3,8 @@
#include "clogger.h"
#include "slsDetectorServer_defs.h"
#include <unistd.h> // usleep
#include <string.h>
#include <unistd.h> // usleep
/* global variables */
#define MTDSIZE 10
@@ -13,59 +12,61 @@
int gpioDefined = 0;
char mtdvalue[MTDSIZE] = {0};
void defineGPIOpins(){
void defineGPIOpins() {
if (!gpioDefined) {
//define the gpio pins
// define the gpio pins
system("echo 7 > /sys/class/gpio/export");
system("echo 9 > /sys/class/gpio/export");
//define their direction
// define their direction
system("echo in > /sys/class/gpio/gpio7/direction");
system("echo out > /sys/class/gpio/gpio9/direction");
LOG(logINFO, ("gpio pins defined\n"));
gpioDefined = 1;
}else LOG(logDEBUG1, ("gpio pins already defined earlier\n"));
} else
LOG(logDEBUG1, ("gpio pins already defined earlier\n"));
}
void FPGAdontTouchFlash(){
//tell FPGA to not touch flash
void FPGAdontTouchFlash() {
// tell FPGA to not touch flash
system("echo 0 > /sys/class/gpio/gpio9/value");
//usleep(100*1000);
// usleep(100*1000);
}
void FPGATouchFlash(){
//tell FPGA to touch flash to program itself
void FPGATouchFlash() {
// tell FPGA to touch flash to program itself
system("echo 1 > /sys/class/gpio/gpio9/value");
}
void resetFPGA(){
void resetFPGA() {
LOG(logINFOBLUE, ("Reseting FPGA\n"));
FPGAdontTouchFlash();
FPGATouchFlash();
usleep(CTRL_SRVR_INIT_TIME_US);
}
void eraseFlash(){
void eraseFlash() {
LOG(logDEBUG1, ("Erasing Flash\n"));
char command[255];
memset(command, 0, 255);
sprintf(command,"flash_eraseall %s",mtdvalue);
sprintf(command, "flash_eraseall %s", mtdvalue);
system(command);
LOG(logINFO, ("Flash erased\n"));
}
int startWritingFPGAprogram(FILE** filefp){
int startWritingFPGAprogram(FILE **filefp) {
LOG(logDEBUG1, ("Start Writing of FPGA program\n"));
//getting the drive
//root:/> cat /proc/mtd
//dev: size erasesize name
//mtd0: 00040000 00020000 "bootloader(nor)"
//mtd1: 00100000 00020000 "linux kernel(nor)"
//mtd2: 002c0000 00020000 "file system(nor)"
//mtd3: 01000000 00010000 "bitfile(spi)"
// getting the drive
// root:/> cat /proc/mtd
// dev: size erasesize name
// mtd0: 00040000 00020000 "bootloader(nor)"
// mtd1: 00100000 00020000 "linux kernel(nor)"
// mtd2: 002c0000 00020000 "file system(nor)"
// mtd3: 01000000 00010000 "bitfile(spi)"
char output[255];
memset(output, 0, 255);
FILE* fp = popen("awk \'$4== \"\\\"bitfile(spi)\\\"\" {print $1}\' /proc/mtd", "r");
FILE *fp = popen(
"awk \'$4== \"\\\"bitfile(spi)\\\"\" {print $1}\' /proc/mtd", "r");
if (fp == NULL) {
LOG(logERROR, ("popen returned NULL. Need that to get mtd drive.\n"));
return 1;
@@ -76,20 +77,20 @@ int startWritingFPGAprogram(FILE** filefp){
}
pclose(fp);
memset(mtdvalue, 0, MTDSIZE);
strcpy(mtdvalue,"/dev/");
char* pch = strtok(output,":");
if(pch == NULL){
strcpy(mtdvalue, "/dev/");
char *pch = strtok(output, ":");
if (pch == NULL) {
LOG(logERROR, ("Could not get mtd value\n"));
return 1;
}
strcat(mtdvalue,pch);
strcat(mtdvalue, pch);
LOG(logINFO, ("Flash drive found: %s\n", mtdvalue));
FPGAdontTouchFlash();
//writing the program to flash
// writing the program to flash
*filefp = fopen(mtdvalue, "w");
if(*filefp == NULL){
if (*filefp == NULL) {
LOG(logERROR, ("Unable to open %s in write mode\n", mtdvalue));
return 1;
}
@@ -98,42 +99,44 @@ int startWritingFPGAprogram(FILE** filefp){
return 0;
}
void stopWritingFPGAprogram(FILE* filefp){
void stopWritingFPGAprogram(FILE *filefp) {
LOG(logDEBUG1, ("Stopping of writing FPGA program\n"));
int wait = 0;
if(filefp!= NULL){
if (filefp != NULL) {
fclose(filefp);
wait = 1;
}
//touch and program
// touch and program
FPGATouchFlash();
if(wait){
if (wait) {
LOG(logDEBUG1, ("Waiting for FPGA to program from flash\n"));
//waiting for success or done
// waiting for success or done
char output[255];
int res=0;
while(res == 0){
FILE* sysFile = popen("cat /sys/class/gpio/gpio7/value", "r");
int res = 0;
while (res == 0) {
FILE *sysFile = popen("cat /sys/class/gpio/gpio7/value", "r");
fgets(output, sizeof(output), sysFile);
pclose(sysFile);
sscanf(output,"%d",&res);
sscanf(output, "%d", &res);
LOG(logDEBUG1, ("gpi07 returned %d\n", res));
}
}
LOG(logINFO, ("FPGA has picked up the program from flash\n"));
}
int writeFPGAProgram(char* fpgasrc, uint64_t fsize, FILE* filefp){
LOG(logDEBUG1, ("Writing of FPGA Program\n"
int writeFPGAProgram(char *fpgasrc, uint64_t fsize, FILE *filefp) {
LOG(logDEBUG1,
("Writing of FPGA Program\n"
"\taddress of fpgasrc:%p\n"
"\tfsize:%llu\n\tpointer:%p\n",
(void *)fpgasrc, (long long unsigned int)fsize, (void*)filefp));
(void *)fpgasrc, (long long unsigned int)fsize, (void *)filefp));
if(fwrite((void*)fpgasrc , sizeof(char) , fsize , filefp )!= fsize){
LOG(logERROR, ("Could not write FPGA source to flash (size:%llu)\n", (long long unsigned int)fsize));
if (fwrite((void *)fpgasrc, sizeof(char), fsize, filefp) != fsize) {
LOG(logERROR, ("Could not write FPGA source to flash (size:%llu)\n",
(long long unsigned int)fsize));
return 1;
}
LOG(logDEBUG1, ("program written to flash\n"));

50
slsDetectorServers/slsDetectorServer/src/programFpgaNios.c Executable file → Normal file
View File

@@ -3,9 +3,8 @@
#include "clogger.h"
#include "slsDetectorServer_defs.h"
#include <unistd.h> // usleep
#include <string.h>
#include <unistd.h> // usleep
/* global variables */
#define MTDSIZE 10
@@ -17,19 +16,21 @@ void NotifyServerStartSuccess() {
LOG(logINFOBLUE, ("Server started successfully\n"));
char command[255];
memset(command, 0, 255);
sprintf(command,"echo r > %s",MICROCONTROLLER_FILE);
sprintf(command, "echo r > %s", MICROCONTROLLER_FILE);
system(command);
}
void CreateNotificationForCriticalTasks() {
FILE* fd = fopen(NOTIFICATION_FILE, "r");
FILE *fd = fopen(NOTIFICATION_FILE, "r");
if (fd == NULL) {
fd = fopen(NOTIFICATION_FILE, "w");
if (fd == NULL) {
LOG(logERROR, ("Could not create notication file: %s\n", NOTIFICATION_FILE));
LOG(logERROR,
("Could not create notication file: %s\n", NOTIFICATION_FILE));
return;
}
LOG(logINFOBLUE, ("Created notification file: %s\n", NOTIFICATION_FILE));
LOG(logINFOBLUE,
("Created notification file: %s\n", NOTIFICATION_FILE));
}
fclose(fd);
NotifyCriticalTaskDone();
@@ -39,7 +40,7 @@ void NotifyCriticalTask() {
LOG(logINFO, ("\tNotifying Critical Task Ongoing\n"));
char command[255];
memset(command, 0, 255);
sprintf(command,"echo 1 > %s",NOTIFICATION_FILE);
sprintf(command, "echo 1 > %s", NOTIFICATION_FILE);
system(command);
}
@@ -47,7 +48,7 @@ void NotifyCriticalTaskDone() {
LOG(logINFO, ("\tNotifying Critical Task Done\n"));
char command[255];
memset(command, 0, 255);
sprintf(command,"echo 0 > %s",NOTIFICATION_FILE);
sprintf(command, "echo 0 > %s", NOTIFICATION_FILE);
system(command);
}
@@ -55,13 +56,13 @@ void rebootControllerAndFPGA() {
LOG(logDEBUG1, ("Reseting FPGA...\n"));
char command[255];
memset(command, 0, 255);
sprintf(command,"echo z > %s",MICROCONTROLLER_FILE);
sprintf(command, "echo z > %s", MICROCONTROLLER_FILE);
system(command);
}
int findFlash(char* mess) {
int findFlash(char *mess) {
LOG(logDEBUG1, ("Finding flash drive...\n"));
//getting the drive
// getting the drive
// # cat /proc/mtd
// dev: size erasesize name
// mtd0: 00580000 00010000 "qspi BootInfo + Factory Image"
@@ -72,7 +73,7 @@ int findFlash(char* mess) {
// mtd5: 04000000 00010000 "qspi Complete Flash"
char output[255];
memset(output, 0, 255);
FILE* fp = popen("awk \'$5== \"Application\" {print $1}\' /proc/mtd", "r");
FILE *fp = popen("awk \'$5== \"Application\" {print $1}\' /proc/mtd", "r");
if (fp == NULL) {
strcpy(mess, "popen returned NULL. Need that to get mtd drive.\n");
LOG(logERROR, (mess));
@@ -86,9 +87,9 @@ int findFlash(char* mess) {
pclose(fp);
memset(mtdvalue, 0, MTDSIZE);
strcpy(mtdvalue, "/dev/");
char* pch = strtok(output, ":");
if (pch == NULL){
strcpy (mess, "Could not get mtd value\n");
char *pch = strtok(output, ":");
if (pch == NULL) {
strcpy(mess, "Could not get mtd value\n");
LOG(logERROR, (mess));
return FAIL;
}
@@ -101,12 +102,12 @@ void eraseFlash() {
LOG(logDEBUG1, ("Erasing Flash...\n"));
char command[255];
memset(command, 0, 255);
sprintf(command,"flash_erase %s 0 0",mtdvalue);
sprintf(command, "flash_erase %s 0 0", mtdvalue);
system(command);
LOG(logINFO, ("\tFlash erased\n"));
}
int eraseAndWriteToFlash(char* mess, char* fpgasrc, uint64_t fsize) {
int eraseAndWriteToFlash(char *mess, char *fpgasrc, uint64_t fsize) {
if (findFlash(mess) == FAIL) {
return FAIL;
}
@@ -115,9 +116,9 @@ int eraseAndWriteToFlash(char* mess, char* fpgasrc, uint64_t fsize) {
// open file pointer to flash
FILE *filefp = fopen(mtdvalue, "w");
if(filefp == NULL){
if (filefp == NULL) {
NotifyCriticalTaskDone();
sprintf (mess, "Unable to open %s in write mode\n", mtdvalue);
sprintf(mess, "Unable to open %s in write mode\n", mtdvalue);
LOG(logERROR, (mess));
return FAIL;
}
@@ -135,15 +136,18 @@ int eraseAndWriteToFlash(char* mess, char* fpgasrc, uint64_t fsize) {
return OK;
}
int writeFPGAProgram(char* mess, char* fpgasrc, uint64_t fsize, FILE* filefp) {
int writeFPGAProgram(char *mess, char *fpgasrc, uint64_t fsize, FILE *filefp) {
LOG(logDEBUG1, ("Writing to flash...\n"
"\taddress of fpgasrc:%p\n"
"\tfsize:%lu\n\tpointer:%p\n",
(void *)fpgasrc, fsize, (void*)filefp));
(void *)fpgasrc, fsize, (void *)filefp));
uint64_t retval = fwrite((void*)fpgasrc , sizeof(char) , fsize , filefp);
uint64_t retval = fwrite((void *)fpgasrc, sizeof(char), fsize, filefp);
if (retval != fsize) {
sprintf (mess, "Could not write FPGA source to flash (size:%llu), write %llu\n", (long long unsigned int) fsize, (long long unsigned int)retval);
sprintf(
mess,
"Could not write FPGA source to flash (size:%llu), write %llu\n",
(long long unsigned int)fsize, (long long unsigned int)retval);
LOG(logERROR, (mess));
return FAIL;
}

181
slsDetectorServers/slsDetectorServer/src/readDefaultPattern.c Executable file → Normal file
View File

@@ -1,8 +1,8 @@
#include "readDefaultPattern.h"
#include "sls_detector_defs.h"
#include "slsDetectorServer_defs.h"
#include "ansi.h"
#include "clogger.h"
#include "slsDetectorServer_defs.h"
#include "sls_detector_defs.h"
#include <string.h>
@@ -14,16 +14,16 @@ extern uint64_t writePatternClkControl(uint64_t word);
extern uint64_t writePatternWord(int addr, uint64_t word);
extern int setPatternWaitAddress(int level, int addr);
extern uint64_t setPatternWaitTime(int level, uint64_t t);
extern void setPatternLoop(int level, int *startAddr, int *stopAddr, int *nLoop);
extern void setPatternLoop(int level, int *startAddr, int *stopAddr,
int *nLoop);
int loadDefaultPattern(char* fname) {
int loadDefaultPattern(char *fname) {
if (initError == FAIL) {
return initError;
}
FILE* fd = fopen(fname, "r");
if(fd == NULL) {
FILE *fd = fopen(fname, "r");
if (fd == NULL) {
sprintf(initErrorMessage, "Could not open pattern file [%s].\n", fname);
initError = FAIL;
LOG(logERROR, ("%s\n\n", initErrorMessage));
@@ -31,7 +31,6 @@ int loadDefaultPattern(char* fname) {
}
LOG(logINFOBLUE, ("Reading default pattern file %s\n", fname));
// Initialization
const size_t LZ = 256;
char line[LZ];
@@ -77,8 +76,8 @@ int loadDefaultPattern(char* fname) {
LOG(logDEBUG1, ("Removing leading spaces.\n"));
}
LOG(logDEBUG1, ("Command to process: (size:%d) %.*s\n",
strlen(line), strlen(line) -1, line));
LOG(logDEBUG1, ("Command to process: (size:%d) %.*s\n", strlen(line),
strlen(line) - 1, line));
memset(command, 0, LZ);
// patword
@@ -92,8 +91,10 @@ int loadDefaultPattern(char* fname) {
#else
if (sscanf(line, "%s 0x%x 0x%llx", command, &addr, &word) != 3) {
#endif
sprintf(initErrorMessage, "Could not scan patword arguments from default "
"pattern file. Line:[%s].\n", line);
sprintf(initErrorMessage,
"Could not scan patword arguments from default "
"pattern file. Line:[%s].\n",
line);
break;
}
@@ -112,8 +113,10 @@ int loadDefaultPattern(char* fname) {
#else
if (sscanf(line, "%s 0x%llx", command, &arg) != 2) {
#endif
sprintf(initErrorMessage, "Could not scan patioctrl arguments from default "
"pattern file. Line:[%s].\n", line);
sprintf(initErrorMessage,
"Could not scan patioctrl arguments from default "
"pattern file. Line:[%s].\n",
line);
break;
}
@@ -132,8 +135,10 @@ int loadDefaultPattern(char* fname) {
#else
if (sscanf(line, "%s 0x%llx", command, &arg) != 2) {
#endif
sprintf(initErrorMessage, "Could not scan patclkctrl arguments from default "
"pattern file. Line:[%s].\n", line);
sprintf(initErrorMessage,
"Could not scan patclkctrl arguments from default "
"pattern file. Line:[%s].\n",
line);
break;
}
@@ -148,13 +153,17 @@ int loadDefaultPattern(char* fname) {
uint32_t stopAddr = 0;
// cannot scan values
if (sscanf(line, "%s 0x%x 0x%x", command, &startAddr, &stopAddr) != 3) {
sprintf(initErrorMessage, "Could not scan patlimits arguments from default "
"pattern file. Line:[%s].\n", line);
if (sscanf(line, "%s 0x%x 0x%x", command, &startAddr, &stopAddr) !=
3) {
sprintf(initErrorMessage,
"Could not scan patlimits arguments from default "
"pattern file. Line:[%s].\n",
line);
break;
}
if (default_setPatternLoopLimits(line, startAddr, stopAddr) == FAIL) {
if (default_setPatternLoopLimits(line, startAddr, stopAddr) ==
FAIL) {
break;
}
}
@@ -177,13 +186,17 @@ int loadDefaultPattern(char* fname) {
uint32_t startAddr = 0;
uint32_t stopAddr = 0;
// cannot scan values
if (sscanf(line, "%s 0x%x 0x%x", command, &startAddr, &stopAddr) != 3) {
sprintf(initErrorMessage, "Could not scan patloop%d arguments from default "
"pattern file. Line:[%s].\n", level, line);
if (sscanf(line, "%s 0x%x 0x%x", command, &startAddr, &stopAddr) !=
3) {
sprintf(initErrorMessage,
"Could not scan patloop%d arguments from default "
"pattern file. Line:[%s].\n",
level, line);
break;
}
if (default_setPatternLoopAddresses(line, level, startAddr, stopAddr) == FAIL) {
if (default_setPatternLoopAddresses(line, level, startAddr,
stopAddr) == FAIL) {
break;
}
}
@@ -206,8 +219,10 @@ int loadDefaultPattern(char* fname) {
int numLoops = -1;
// cannot scan values
if (sscanf(line, "%s %d", command, &numLoops) != 2) {
sprintf(initErrorMessage, "Could not scan patnloop%d arguments from default "
"pattern file. Line:[%s].\n", level, line);
sprintf(initErrorMessage,
"Could not scan patnloop%d arguments from default "
"pattern file. Line:[%s].\n",
level, line);
break;
}
@@ -234,8 +249,10 @@ int loadDefaultPattern(char* fname) {
uint32_t addr = 0;
// cannot scan values
if (sscanf(line, "%s 0x%x", command, &addr) != 2) {
sprintf(initErrorMessage, "Could not scan patwait%d arguments from default "
"pattern file. Line:[%s].\n", level, line);
sprintf(initErrorMessage,
"Could not scan patwait%d arguments from default "
"pattern file. Line:[%s].\n",
level, line);
break;
}
@@ -267,8 +284,10 @@ int loadDefaultPattern(char* fname) {
#else
if (sscanf(line, "%s %lld", command, &waittime) != 2) {
#endif
sprintf(initErrorMessage, "Could not scan patwaittime%d arguments from default "
"pattern file. Line:[%s].\n", level, line);
sprintf(initErrorMessage,
"Could not scan patwaittime%d arguments from default "
"pattern file. Line:[%s].\n",
level, line);
break;
}
@@ -290,11 +309,11 @@ int loadDefaultPattern(char* fname) {
return initError;
}
int default_writePatternWord(char* line, uint32_t addr, uint64_t word) {
//validations
int default_writePatternWord(char *line, uint32_t addr, uint64_t word) {
// validations
if ((int32_t)addr < 0 || addr >= MAX_PATTERN_LENGTH) {
sprintf(initErrorMessage, "Cannot set pattern word from default "
sprintf(initErrorMessage,
"Cannot set pattern word from default "
"pattern file. Addr must be between 0 and 0x%x. Line:[%s]\n",
MAX_PATTERN_LENGTH, line);
return FAIL;
@@ -304,42 +323,51 @@ int default_writePatternWord(char* line, uint32_t addr, uint64_t word) {
return OK;
}
int default_writePatternIOControl(char* line, uint64_t arg) {
int default_writePatternIOControl(char *line, uint64_t arg) {
uint64_t retval = writePatternIOControl(arg);
if (retval != arg) {
#ifdef VIRTUAL
sprintf(initErrorMessage, "Could not set patioctrl from default pattern "
"file. Set 0x%lx, read 0x%lx. Line:[%s]\n", arg, retval, line);
sprintf(initErrorMessage,
"Could not set patioctrl from default pattern "
"file. Set 0x%lx, read 0x%lx. Line:[%s]\n",
arg, retval, line);
#else
sprintf(initErrorMessage, "Could not set patioctrl from default pattern "
"file. Set 0x%llx, read 0x%llx. Line:[%s]\n", arg, retval, line);
sprintf(initErrorMessage,
"Could not set patioctrl from default pattern "
"file. Set 0x%llx, read 0x%llx. Line:[%s]\n",
arg, retval, line);
#endif
return FAIL;
}
return OK;
}
int default_writePatternClkControl(char* line, uint64_t arg) {
int default_writePatternClkControl(char *line, uint64_t arg) {
uint64_t retval = writePatternClkControl(arg);
if (retval != arg) {
#ifdef VIRTUAL
sprintf(initErrorMessage, "Could not set patclkctrl from default pattern "
"file. Set 0x%lx, read 0x%lx. Line:[%s]\n", arg, retval, line);
sprintf(initErrorMessage,
"Could not set patclkctrl from default pattern "
"file. Set 0x%lx, read 0x%lx. Line:[%s]\n",
arg, retval, line);
#else
sprintf(initErrorMessage, "Could not set patclkctrl from default pattern "
"file. Set 0x%llx, read 0x%llx. Line:[%s]\n", arg, retval, line);
sprintf(initErrorMessage,
"Could not set patclkctrl from default pattern "
"file. Set 0x%llx, read 0x%llx. Line:[%s]\n",
arg, retval, line);
#endif
return FAIL;
}
return OK;
}
int default_setPatternLoopLimits(char* line, uint32_t startAddr, uint32_t stopAddr) {
//validations
int default_setPatternLoopLimits(char *line, uint32_t startAddr,
uint32_t stopAddr) {
// validations
if ((int32_t)startAddr < 0 || startAddr >= MAX_PATTERN_LENGTH ||
(int32_t)stopAddr < 0 || stopAddr >= MAX_PATTERN_LENGTH) {
sprintf(initErrorMessage, "Cannot set patlimits from default "
sprintf(initErrorMessage,
"Cannot set patlimits from default "
"pattern file. Addr must be between 0 and 0x%x. Line:[%s]\n",
MAX_PATTERN_LENGTH, line);
return FAIL;
@@ -350,7 +378,8 @@ int default_setPatternLoopLimits(char* line, uint32_t startAddr, uint32_t stopAd
// validate
if (r_startAddr != (int)startAddr || r_stopAddr != (int)stopAddr) {
sprintf(initErrorMessage, "Could not set patlimits from default pattern "
sprintf(initErrorMessage,
"Could not set patlimits from default pattern "
"file. Read start addr:0x%x, stop addr: 0x%x. Line:[%s]\n",
r_startAddr, r_stopAddr, line);
return FAIL;
@@ -358,17 +387,20 @@ int default_setPatternLoopLimits(char* line, uint32_t startAddr, uint32_t stopAd
return OK;
}
int default_setPatternLoopAddresses(char* line, int level, uint32_t startAddr, uint32_t stopAddr) {
//validations
int default_setPatternLoopAddresses(char *line, int level, uint32_t startAddr,
uint32_t stopAddr) {
// validations
if (level < 0 || level > 2) {
sprintf(initErrorMessage, "Cannot set patloop from default "
sprintf(initErrorMessage,
"Cannot set patloop from default "
"pattern file. Level must be between 0 and 2. Line:[%s]\n",
line);
return FAIL;
}
if ((int32_t)startAddr < 0 || startAddr >= MAX_PATTERN_LENGTH ||
(int32_t)stopAddr < 0 || stopAddr >= MAX_PATTERN_LENGTH) {
sprintf(initErrorMessage, "Cannot set patloop (level: %d) from default "
sprintf(initErrorMessage,
"Cannot set patloop (level: %d) from default "
"pattern file. Addr must be between 0 and 0x%x. Line:[%s]\n",
level, MAX_PATTERN_LENGTH, line);
return FAIL;
@@ -379,7 +411,9 @@ int default_setPatternLoopAddresses(char* line, int level, uint32_t startAddr, u
// validate
if (r_startAddr != (int)startAddr || r_stopAddr != (int)stopAddr) {
sprintf(initErrorMessage, "Could not set patloop (level: %d) from default "
sprintf(
initErrorMessage,
"Could not set patloop (level: %d) from default "
"pattern file. Read start addr:0x%x, stop addr: 0x%x. Line:[%s]\n",
level, r_startAddr, r_stopAddr, line);
return FAIL;
@@ -387,16 +421,18 @@ int default_setPatternLoopAddresses(char* line, int level, uint32_t startAddr, u
return OK;
}
int default_setPatternLoopCycles(char* line, int level, int numLoops) {
//validations
int default_setPatternLoopCycles(char *line, int level, int numLoops) {
// validations
if (level < 0 || level > 2) {
sprintf(initErrorMessage, "Cannot set patnloop from default "
sprintf(initErrorMessage,
"Cannot set patnloop from default "
"pattern file. Level must be between 0 and 2. Line:[%s]\n",
line);
return FAIL;
}
if (numLoops < 0) {
sprintf(initErrorMessage, "Cannot set patnloop from default "
sprintf(initErrorMessage,
"Cannot set patnloop from default "
"pattern file. Iterations must be between > 0. Line:[%s]\n",
line);
return FAIL;
@@ -408,7 +444,8 @@ int default_setPatternLoopCycles(char* line, int level, int numLoops) {
// validate
if (r_numLoops != numLoops) {
sprintf(initErrorMessage, "Could not set patnloop (level: %d) from default "
sprintf(initErrorMessage,
"Could not set patnloop (level: %d) from default "
"pattern file. Read %d loops. Line:[%s]\n",
level, r_numLoops, line);
return FAIL;
@@ -416,16 +453,18 @@ int default_setPatternLoopCycles(char* line, int level, int numLoops) {
return OK;
}
int default_setPatternWaitAddresses(char* line, int level, uint32_t addr) {
//validations
int default_setPatternWaitAddresses(char *line, int level, uint32_t addr) {
// validations
if (level < 0 || level > 2) {
sprintf(initErrorMessage, "Cannot set patwait address from default "
sprintf(initErrorMessage,
"Cannot set patwait address from default "
"pattern file. Level must be between 0 and 2. Line:[%s]\n",
line);
return FAIL;
}
if ((int32_t)addr < 0 || addr >= MAX_PATTERN_LENGTH) {
sprintf(initErrorMessage, "Cannot set patwait address (level: %d) from default "
sprintf(initErrorMessage,
"Cannot set patwait address (level: %d) from default "
"pattern file. Addr must be between 0 and 0x%x. Line:[%s]\n",
level, MAX_PATTERN_LENGTH, line);
return FAIL;
@@ -435,7 +474,8 @@ int default_setPatternWaitAddresses(char* line, int level, uint32_t addr) {
// validate
if (retval != addr) {
sprintf(initErrorMessage, "Could not set patwait address (level: %d) from default "
sprintf(initErrorMessage,
"Could not set patwait address (level: %d) from default "
"pattern file. Read addr: 0x%x. Line:[%s]\n",
level, retval, line);
return FAIL;
@@ -443,10 +483,11 @@ int default_setPatternWaitAddresses(char* line, int level, uint32_t addr) {
return OK;
}
int default_setPatternWaitTime(char* line, int level, uint64_t waittime) {
//validations
int default_setPatternWaitTime(char *line, int level, uint64_t waittime) {
// validations
if (level < 0 || level > 2) {
sprintf(initErrorMessage, "Cannot set patwaittime from default "
sprintf(initErrorMessage,
"Cannot set patwaittime from default "
"pattern file. Level must be between 0 and 2. Line:[%s]\n",
line);
return FAIL;
@@ -456,11 +497,13 @@ int default_setPatternWaitTime(char* line, int level, uint64_t waittime) {
// validate
if (retval != waittime) {
#ifdef VIRTUAL
sprintf(initErrorMessage, "Could not set patwaittime (level: %d) from default "
sprintf(initErrorMessage,
"Could not set patwaittime (level: %d) from default "
"pattern file. Read %ld wait time. Line:[%s]\n",
level, retval, line);
#else
sprintf(initErrorMessage, "Could not set patwaittime (level: %d) from default "
sprintf(initErrorMessage,
"Could not set patwaittime (level: %d) from default "
"pattern file. Read %lld wait time. Line:[%s]\n",
level, retval, line);
#endif

38
slsDetectorServers/slsDetectorServer/src/slsDetectorServer.c Executable file → Normal file
View File

@@ -1,11 +1,11 @@
/* A simple server in the internet domain using TCP
The port number is passed as an argument */
#include "sls_detector_defs.h"
#include "clogger.h"
#include "communication_funcs.h"
#include "slsDetectorServer_funcs.h"
#include "slsDetectorServer_defs.h"
#include "slsDetectorServer_funcs.h"
#include "sls_detector_defs.h"
#include "versionAPI.h"
#ifdef VIRTUAL
#include "communication_virtual.h"
@@ -24,15 +24,12 @@ extern int sockfd;
extern int debugflag;
extern int checkModuleFlag;
// Global variables from slsDetectorFunctionList
#ifdef GOTTHARDD
extern int phaseShift;
#endif
void error(char *msg){
perror(msg);
}
void error(char *msg) { perror(msg); }
int main(int argc, char *argv[]) {
@@ -66,37 +63,37 @@ int main(int argc, char *argv[]) {
{
int i;
for (i = 1; i < argc; ++i) {
if(!strcasecmp(argv[i],"-stopserver")) {
if (!strcasecmp(argv[i], "-stopserver")) {
LOG(logINFO, ("Detected stop server\n"));
isControlServer = 0;
}
else if(!strcasecmp(argv[i],"-devel")){
} else if (!strcasecmp(argv[i], "-devel")) {
LOG(logINFO, ("Detected developer mode\n"));
debugflag = 1;
}
else if(!strcasecmp(argv[i],"-nomodule")){
} else if (!strcasecmp(argv[i], "-nomodule")) {
LOG(logINFO, ("Detected No Module mode\n"));
checkModuleFlag = 0;
}
else if(!strcasecmp(argv[i],"-port")){
} else if (!strcasecmp(argv[i], "-port")) {
if ((i + 1) >= argc) {
LOG(logERROR, ("no port value given. Exiting.\n"));
return -1;
}
if (sscanf(argv[i + 1], "%d", &portno) == 0) {
LOG(logERROR, ("cannot decode port value %s. Exiting.\n", argv[i + 1]));
LOG(logERROR, ("cannot decode port value %s. Exiting.\n",
argv[i + 1]));
return -1;
}
LOG(logINFO, ("Detected port: %d\n", portno));
}
#ifdef GOTTHARDD
else if(!strcasecmp(argv[i],"-phaseshift")){
else if (!strcasecmp(argv[i], "-phaseshift")) {
if ((i + 1) >= argc) {
LOG(logERROR, ("no phase shift value given. Exiting.\n"));
return -1;
}
if (sscanf(argv[i + 1], "%d", &phaseShift) == 0) {
LOG(logERROR, ("cannot decode phase shift value %s. Exiting.\n", argv[i + 1]));
LOG(logERROR,
("cannot decode phase shift value %s. Exiting.\n",
argv[i + 1]));
return -1;
}
LOG(logINFO, ("Detected phase shift of %d\n", phaseShift));
@@ -115,7 +112,7 @@ int main(int argc, char *argv[]) {
int i;
for (i = 0; i < argc; ++i) {
if (!strcasecmp(argv[i], "-port")) {
i +=2;
i += 2;
continue;
}
if (i > 0) {
@@ -148,7 +145,6 @@ int main(int argc, char *argv[]) {
#endif
}
init_detector();
// bind socket
sockfd = bindSocket(portno);
@@ -165,7 +161,7 @@ int main(int argc, char *argv[]) {
// waits for connection
int retval = OK;
while(retval != GOODBYE && retval != REBOOT) {
while (retval != GOODBYE && retval != REBOOT) {
int fd = acceptConnection(sockfd);
if (fd > 0) {
retval = decode_function(fd);
@@ -176,7 +172,7 @@ int main(int argc, char *argv[]) {
exitServer(sockfd);
if (retval == REBOOT) {
LOG(logINFORED,("Rebooting!\n"));
LOG(logINFORED, ("Rebooting!\n"));
fflush(stdout);
#if defined(MYTHEN3D) || defined(GOTTHARD2D)
rebootNiosControllerAndFPGA();
@@ -184,6 +180,6 @@ int main(int argc, char *argv[]) {
system("reboot");
#endif
}
LOG(logINFO,("Goodbye!\n"));
LOG(logINFO, ("Goodbye!\n"));
return 0;
}

2533
slsDetectorServers/slsDetectorServer/src/slsDetectorServer_funcs.c Executable file → Normal file
View File

File diff suppressed because it is too large Load Diff