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moench and lookinginto max1932

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This commit is contained in:
maliakal_d 2018-12-19 17:16:41 +01:00
parent f161d68efc
commit a013734af8
29 changed files with 3059 additions and 7 deletions
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2
slsDetectorServers/ctbDetectorServer/slsDetectorFunctionList.c
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@ -478,7 +478,7 @@ void setupDetector() {
resetPeripheral();
cleanFifos();
// set defines
// set spi defines
AD7689_SetDefines(ADC_SPI_REG, ADC_SPI_SLOW_VAL_REG, ADC_SPI_SLOW_SRL_CNV_MSK, ADC_SPI_SLOW_SRL_CLK_MSK, ADC_SPI_SLOW_SRL_DT_MSK, ADC_SPI_SLOW_SRL_DT_OFST);
AD9257_SetDefines(ADC_SPI_REG, ADC_SPI_SRL_CS_OTPT_MSK, ADC_SPI_SRL_CLK_OTPT_MSK, ADC_SPI_SRL_DT_OTPT_MSK, ADC_SPI_SRL_DT_OTPT_OFST);
LTC2620_SetDefines(SPI_REG, SPI_DAC_SRL_CS_OTPT_MSK, SPI_DAC_SRL_CLK_OTPT_MSK, SPI_DAC_SRL_DGTL_OTPT_MSK, SPI_DAC_SRL_DGTL_OTPT_OFST, NDAC, MAX_DAC_VOLTAGE_VALUE);

2
slsDetectorServers/jungfrauDetectorServer/slsDetectorFunctionList.c
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@ -397,7 +397,7 @@ void setupDetector() {
resetPeripheral();
cleanFifos();
// set defines
// set spi defines
AD9257_SetDefines(ADC_SPI_REG, ADC_SPI_SRL_CS_OTPT_MSK, ADC_SPI_SRL_CLK_OTPT_MSK, ADC_SPI_SRL_DT_OTPT_MSK, ADC_SPI_SRL_DT_OTPT_OFST);
LTC2620_SetDefines(SPI_REG, SPI_DAC_SRL_CS_OTPT_MSK, SPI_DAC_SRL_CLK_OTPT_MSK, SPI_DAC_SRL_DGTL_OTPT_MSK, SPI_DAC_SRL_DGTL_OTPT_OFST, NDAC, MAX_DAC_VOLTAGE_VALUE);
MAX1932_SetDefines(SPI_REG, SPI_HV_SRL_CS_OTPT_MSK, SPI_HV_SRL_CLK_OTPT_MSK, SPI_HV_SRL_DGTL_OTPT_MSK, SPI_HV_SRL_DGTL_OTPT_OFST);

1
slsDetectorServers/moenchDetectorServer/AD9257.h Symbolic link
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@ -0,0 +1 @@
../slsDetectorServer/AD9257.h

1
slsDetectorServers/moenchDetectorServer/LTC2620.h Symbolic link
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@ -0,0 +1 @@
../slsDetectorServer/LTC2620.h

1
slsDetectorServers/moenchDetectorServer/MAX1932.h Symbolic link
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@ -0,0 +1 @@
../slsDetectorServer/MAX1932.h

31
slsDetectorServers/moenchDetectorServer/Makefile Executable file
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@ -0,0 +1,31 @@
CROSS = bfin-uclinux-
CC = $(CROSS)gcc
CFLAGS += -Wall -DMOENCHD -DSTOP_SERVER # -DVERBOSEI #-DVERBOSE
LDLIBS += -lm -lstdc++
PROGS = moenchDetectorServer
DESTDIR ?= bin
INSTMODE = 0777
SRC_CLNT = communication_funcs.c slsDetectorServer.c slsDetectorServer_funcs.c slsDetectorFunctionList.c
OBJS = $(SRC_CLNT:.c=.o)
all: clean versioning $(PROGS)
boot: $(OBJS)
versioning:
@echo `tput setaf 6; ./updateGitVersion.sh; tput sgr0;`
$(PROGS): $(OBJS)
# echo $(OBJS)
mkdir -p $(DESTDIR)
$(CC) -o $@ $^ $(CFLAGS) $(LDLIBS)
mv $(PROGS) $(DESTDIR)
rm *.gdb
clean:
rm -rf $(DESTDIR)/$(PROGS) *.o *.gdb

27
slsDetectorServers/moenchDetectorServer/Makefile.virtual Normal file
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@ -0,0 +1,27 @@
CC = gcc
CFLAGS += -Wall -DMOENCHD -DVIRTUAL -DSTOP_SERVER #-DVERBOSEI #-DVERBOSE
LDLIBS += -lm -lstdc++ -pthread
PROGS = moenchDetectorServer_virtual
DESTDIR ?= bin
INSTMODE = 0777
SRC_CLNT = communication_funcs.c slsDetectorServer.c slsDetectorServer_funcs.c slsDetectorFunctionList.c
OBJS = $(SRC_CLNT:.c=.o)
all: clean versioning $(PROGS)
boot: $(OBJS)
versioning:
@echo `tput setaf 6; ./updateGitVersion.sh; tput sgr0;`
$(PROGS): $(OBJS)
# echo $(OBJS)
mkdir -p $(DESTDIR)
$(CC) -o $@ $^ $(CFLAGS) $(LDLIBS)
mv $(PROGS) $(DESTDIR)
clean:
rm -rf $(DESTDIR)/$(PROGS) *.o

531
slsDetectorServers/moenchDetectorServer/RegisterDefs.h Normal file
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@ -0,0 +1,531 @@
#pragma once
/* Definitions for FPGA */
#define MEM_MAP_SHIFT 11
/* FPGA Version RO register */
#define FPGA_VERSION_REG (0x00 << MEM_MAP_SHIFT)
#define FPGA_VERSION_BRD_RVSN_OFST (0)
#define FPGA_VERSION_BRD_RVSN_MSK (0x00FFFFFF << FPGA_VERSION_BRD_RVSN_OFST)
#define FPGA_VERSION_DTCTR_TYP_OFST (24)
#define FPGA_VERSION_DTCTR_TYP_MSK (0x000000FF << FPGA_VERSION_DTCTR_TYP_OFST)
#define FPGA_VERSION_DTCTR_TYP_MOENCH_VAL ((0x2 << FPGA_VERSION_DTCTR_TYP_OFST) & FPGA_VERSION_DTCTR_TYP_MSK)
/* Fix pattern RO register */
#define FIX_PATT_REG (0x01 << MEM_MAP_SHIFT)
#define FIX_PATT_VAL (0xACDC2014)
/* Status RO register */
#define STATUS_REG (0x02 << MEM_MAP_SHIFT)
#define STATUS_RN_BSY_OFST (0)
#define STATUS_RN_BSY_MSK (0x00000001 << STATUS_RN_BSY_OFST)
#define STATUS_RDT_BSY_OFST (1)
#define STATUS_RDT_BSY_MSK (0x00000001 << STATUS_RDT_BSY_OFST)
//#define STATUS_FF_TST_BSY_OFST (2)
//#define STATUS_FF_TST_BSY_MSK (0x00000001 << STATUS_FF_TST_BSY_OFST)
#define STATUS_WTNG_FR_TRGGR_OFST (3)
#define STATUS_WTNG_FR_TRGGR_MSK (0x00000001 << STATUS_WTNG_FR_TRGGR_OFST)
#define STATUS_DLY_BFR_OFST (4)
#define STATUS_DLY_BFR_MSK (0x00000001 << STATUS_DLY_BFR_OFST)
#define STATUS_DLY_AFTR_OFST (5)
#define STATUS_DLY_AFTR_MSK (0x00000001 << STATUS_DLY_AFTR_OFST)
#define STATUS_EXPSNG_OFST (6)
#define STATUS_EXPSNG_MSK (0x00000001 << STATUS_EXPSNG_OFST)
#define STATUS_CNT_ENBL_OFST (7)
#define STATUS_CNT_ENBL_MSK (0x00000001 << STATUS_CNT_ENBL_OFST)
#define STATUS_SM_FF_FLL_OFST (11)
#define STATUS_SM_FF_FLL_MSK (0x00000001 << STATUS_SM_FF_FLL_OFST)
#define STATUS_STPPD_OFST (15)
#define STATUS_STPPD_MSK (0x00000001 << STATUS_STPPD_OFST)
#define STATUS_ALL_FF_EMPTY_OFST (16)
#define STATUS_ALL_FF_EMPTY_MSK (0x00000001 << STATUS_ALL_FF_EMPTY_OFST)
#define STATUS_CYCL_RN_BSY_OFST (17)
#define STATUS_CYCL_RN_BSY_MSK (0x00000001 << STATUS_CYCL_RN_BSY_OFST)
#define STATUS_FRM_RN_BSY_OFST (18)
#define STATUS_FRM_RN_BSY_MSK (0x00000001 << STATUS_FRM_RN_BSY_OFST)
#define STATUS_ADC_DESERON_OFST (19)
#define STATUS_ADC_DESERON_MSK (0x00000001 << STATUS_ADC_DESERON_OFST)
#define STATUS_PLL_RCNFG_BSY_OFST (20)
#define STATUS_PLL_RCNFG_BSY_MSK (0x00000001 << STATUS_PLL_RCNFG_BSY_OFST)
#define STATUS_DT_STRMNG_BSY_OFST (21)
#define STATUS_DT_STRMNG_BSY_MSK (0x00000001 << STATUS_DT_STRMNG_BSY_OFST)
#define STATUS_FRM_PCKR_BSY_OFST (22)
#define STATUS_FRM_PCKR_BSY_MSK (0x00000001 << STATUS_FRM_PCKR_BSY_OFST)
#define STATUS_PLL_PHS_DN_OFST (23)
#define STATUS_PLL_PHS_DN_MSK (0x00000001 << STATUS_PLL_PHS_DN_OFST)
#define STATUS_PT_CNTRL_STTS_OFF_OFST (24)
#define STATUS_PT_CNTRL_STTS_OFF_MSK (0x000000FF << STATUS_PT_CNTRL_STTS_OFF_OFST)
#define STATUS_IDLE_MSK (0x7FFFF)
/* Look at me RO register TODO */
#define LOOK_AT_ME_REG (0x03 << MEM_MAP_SHIFT)
/* System Status RO register */
#define SYSTEM_STATUS_REG (0x04 << MEM_MAP_SHIFT)
#define SYSTEM_STATUS_DDR3_CLBRTN_OK_OFST (0)
#define SYSTEM_STATUS_DDR3_CLBRTN_OK_MSK (0x00000001 << SYSTEM_STATUS_DDR3_CLBRTN_OK_OFST)
#define SYSTEM_STATUS_DDR3_CLBRTN_FL_OFST (1)
#define SYSTEM_STATUS_DDR3_CLBRTN_FL_MSK (0x00000001 << SYSTEM_STATUS_DDR3_CLBRTN_FL_OFST)
#define SYSTEM_STATUS_DDR3_INT_DN_OFST (2)
#define SYSTEM_STATUS_DDR3_INT_DN_MSK (0x00000001 << SYSTEM_STATUS_DDR3_INT_DN_OFST)
#define SYSTEM_STATUS_RCNFG_PLL_LCK_OFST (3)
#define SYSTEM_STATUS_RCNFG_PLL_LCK_MSK (0x00000001 << SYSTEM_STATUS_RCNFG_PLL_LCK_OFST)
#define SYSTEM_STATUS_PLL_A_LCK_OFST (4)
#define SYSTEM_STATUS_PLL_A_LCK_MSK (0x00000001 << SYSTEM_STATUS_PLL_A_LCK_OFST)
/* PLL Param (Reconfiguratble PLL Parameter) RO register TODO FIXME: Same as PLL_PARAM_REG 0x50 */
//#define PLL_PARAM_REG (0x05 << MEM_MAP_SHIFT)
/* FIFO Data RO register TODO */
#define FIFO_DATA_REG (0x06 << MEM_MAP_SHIFT)
#define FIFO_DATA_HRDWR_SRL_NMBR_OFST (0)
#define FIFO_DATA_HRDWR_SRL_NMBR_MSK (0x0000FFFF << FIFO_DATA_HRDWR_SRL_NMBR_OFST)
//0xCACA#define FIFO_DATA_WRD_OFST (16)
//0xCACA#define FIFO_DATA_WRD_MSK (0x0000FFFF << FIFO_DATA_WRD_OFST)
/* FIFO Status RO register TODO */
#define FIFO_STATUS_REG (0x07 << MEM_MAP_SHIFT)
/* FIFO Empty RO register TODO */
#define FIFO_EMPTY_REG (0x08 << MEM_MAP_SHIFT)
/* FIFO Full RO register TODO */
#define FIFO_FULL_REG (0x09 << MEM_MAP_SHIFT)
/* MCB Serial Number RO register */
#define MOD_SERIAL_NUMBER_REG (0x0A << MEM_MAP_SHIFT)
#define MOD_SERIAL_NUMBER_OFST (0)
#define MOD_SERIAL_NUMBER_MSK (0x000000FF << MOD_SERIAL_NUMBER_OFST)
#define MOD_SERIAL_NUMBER_VRSN_OFST (16)
#define MOD_SERIAL_NUMBER_VRSN_MSK (0x0000003F << MOD_SERIAL_NUMBER_VRSN_OFST)
/* API Version RO register */
#define API_VERSION_REG (0x0F << MEM_MAP_SHIFT)
#define API_VERSION_OFST (0)
#define API_VERSION_MSK (0x00FFFFFF << API_VERSION_OFST)
#define API_VERSION_DTCTR_TYP_OFST (24)
#define API_VERSION_DTCTR_TYP_MSK (0x000000FF << API_VERSION_DTCTR_TYP_OFST)
/* Time from Start 64 bit RO register. t = GCLK x 50 ns. Reset using CONTROL_CRST. TODO */
#define TIME_FROM_START_LSB_REG (0x10 << MEM_MAP_SHIFT)
#define TIME_FROM_START_MSB_REG (0x11 << MEM_MAP_SHIFT)
/* Delay Left 64 bit RO register. t = DLY x 50 ns. TODO */
#define DELAY_LEFT_LSB_REG (0x12 << MEM_MAP_SHIFT)
#define DELAY_LEFT_MSB_REG (0x13 << MEM_MAP_SHIFT)
/* Cycles Left 64 bit RO register TODO */
#define CYCLES_LEFT_LSB_REG (0x14 << MEM_MAP_SHIFT)
#define CYCLES_LEFT_MSB_REG (0x15 << MEM_MAP_SHIFT)
/* Frames Left 64 bit RO register TODO */
#define FRAMES_LEFT_LSB_REG (0x16 << MEM_MAP_SHIFT)
#define FRAMES_LEFT_MSB_REG (0x17 << MEM_MAP_SHIFT)
/* Period Left 64 bit RO register. t = T x 50 ns. TODO */
#define PERIOD_LEFT_LSB_REG (0x18 << MEM_MAP_SHIFT)
#define PERIOD_LEFT_MSB_REG (0x19 << MEM_MAP_SHIFT)
/* Exposure Time Left 64 bit RO register */
//#define EXPTIME_LEFT_LSB_REG (0x1A << MEM_MAP_SHIFT) // Not used in FW
//#define EXPTIME_LEFT_MSB_REG (0x1B << MEM_MAP_SHIFT) // Not used in FW
/* Gates Left 64 bit RO register */
//#define GATES_LEFT_LSB_REG (0x1C << MEM_MAP_SHIFT) // Not used in FW
//#define GATES_LEFT_MSB_REG (0x1D << MEM_MAP_SHIFT) // Not used in FW
/* Data In 64 bit RO register TODO */
#define DATA_IN_LSB_REG (0x1E << MEM_MAP_SHIFT)
#define DATA_IN_MSB_REG (0x1F << MEM_MAP_SHIFT)
/* Pattern Out 64 bit RO register */
#define PATTERN_OUT_LSB_REG (0x20 << MEM_MAP_SHIFT)
#define PATTERN_OUT_MSB_REG (0x21 << MEM_MAP_SHIFT)
/* Frames From Start 64 bit RO register TODO */
//#define FRAMES_FROM_START_LSB_REG (0x22 << MEM_MAP_SHIFT) // Not used in FW
//#define FRAMES_FROM_START_MSB_REG (0x23 << MEM_MAP_SHIFT) // Not used in FW
/* Frames From Start PG 64 bit RO register. Reset using CONTROL_CRST. TODO */
#define FRAMES_FROM_START_PG_LSB_REG (0x24 << MEM_MAP_SHIFT)
#define FRAMES_FROM_START_PG_MSB_REG (0x25 << MEM_MAP_SHIFT)
/* Start Frame Time (Measurement Time) 64 bit register (timestamp at a frame start until reset) TODO */
#define START_FRAME_TIME_LSB_REG (0x26 << MEM_MAP_SHIFT)
#define START_FRAME_TIME_MSB_REG (0x27 << MEM_MAP_SHIFT)
/* Power Status RO register */
#define POWER_STATUS_REG (0x29 << MEM_MAP_SHIFT)
#define POWER_STATUS_ALRT_OFST (27)
#define POWER_STATUS_ALRT_MSK (0x0000001F << POWER_STATUS_ALRT_OFST)
/* DAC Value Out RO register */
//#define DAC_VAL_OUT_REG (0x2A << MEM_MAP_SHIFT)
/* Slow ADC SPI Value RO register */
#define ADC_SPI_SLOW_VAL_REG (0x2B << MEM_MAP_SHIFT)
/* FIFO Digital In Status RO register */
#define FIFO_DIN_STATUS_REG (0x3B << MEM_MAP_SHIFT)
/* FIFO Digital In 64 bit RO register */
#define FIFO_DIN_LSB_REG (0x3C << MEM_MAP_SHIFT)
#define FIFO_DIN_MSB_REG (0x3D << MEM_MAP_SHIFT)
/* SPI (Serial Peripheral Interface) DAC, HV RW register */
#define SPI_REG (0x40 << MEM_MAP_SHIFT)
#define SPI_DAC_SRL_DGTL_OTPT_OFST (0)
#define SPI_DAC_SRL_DGTL_OTPT_MSK (0x00000001 << SPI_DAC_SRL_DGTL_OTPT_OFST)
#define SPI_DAC_SRL_CLK_OTPT_OFST (1)
#define SPI_DAC_SRL_CLK_OTPT_MSK (0x00000001 << SPI_DAC_SRL_CLK_OTPT_OFST)
#define SPI_DAC_SRL_CS_OTPT_OFST (2)
#define SPI_DAC_SRL_CS_OTPT_MSK (0x00000001 << SPI_DAC_SRL_CS_OTPT_OFST)
#define SPI_HV_SRL_DGTL_OTPT_OFST (8)
#define SPI_HV_SRL_DGTL_OTPT_MSK (0x00000001 << SPI_HV_SRL_DGTL_OTPT_OFST)
#define SPI_HV_SRL_CLK_OTPT_OFST (9)
#define SPI_HV_SRL_CLK_OTPT_MSK (0x00000001 << SPI_HV_SRL_CLK_OTPT_OFST)
#define SPI_HV_SRL_CS_OTPT_OFST (10)
#define SPI_HV_SRL_CS_OTPT_MSK (0x00000001 << SPI_HV_SRL_CS_OTPT_OFST)
/* ADC SPI (Serial Peripheral Interface) RW register */
#define ADC_SPI_REG (0x41 << MEM_MAP_SHIFT)
#define ADC_SPI_SRL_CLK_OTPT_OFST (0)
#define ADC_SPI_SRL_CLK_OTPT_MSK (0x00000001 << ADC_SPI_SRL_CLK_OTPT_OFST)
#define ADC_SPI_SRL_DT_OTPT_OFST (1)
#define ADC_SPI_SRL_DT_OTPT_MSK (0x00000001 << ADC_SPI_SRL_DT_OTPT_OFST)
#define ADC_SPI_SRL_CS_OTPT_OFST (2)
#define ADC_SPI_SRL_CS_OTPT_MSK (0x0000000F << ADC_SPI_SRL_CS_OTPT_OFST)
#define ADC_SPI_SLOW_SRL_DT_OFST (8)
#define ADC_SPI_SLOW_SRL_DT_MSK (0x00000001 << ADC_SPI_SLOW_SRL_DT_OFST)
#define ADC_SPI_SLOW_SRL_CLK_OFST (9)
#define ADC_SPI_SLOW_SRL_CLK_MSK (0x00000001 << ADC_SPI_SLOW_SRL_CLK_OFST)
#define ADC_SPI_SLOW_SRL_CNV_OFST (10)
#define ADC_SPI_SLOW_SRL_CNV_MSK (0x00000001 << ADC_SPI_SLOW_SRL_CNV_OFST)
/* ADC Offset RW register */
#define ADC_OFFSET_REG (0x42 << MEM_MAP_SHIFT)
#define ADC_OFFSET_ADC_PPLN_OFST (0)
#define ADC_OFFSET_ADC_PPLN_MSK (0x000000FF << ADC_OFFSET_ADC_PPLN_OFST)
#define ADC_OFFSET_DBT_PPLN_OFST (16)
#define ADC_OFFSET_DBT_PPLN_MSK (0x000000FF << ADC_OFFSET_DBT_PPLN_OFST)
/* ADC Port Invert RW register */
#define ADC_PORT_INVERT_REG (0x43 << MEM_MAP_SHIFT)
#define ADC_PORT_INVERT_0_INPT_OFST (0)
#define ADC_PORT_INVERT_0_INPT_MSK (0x000000FF << ADC_PORT_INVERT_0_INPT_OFST)
#define ADC_PORT_INVERT_1_INPT_OFST (8)
#define ADC_PORT_INVERT_1_INPT_MSK (0x000000FF << ADC_PORT_INVERT_1_INPT_OFST)
#define ADC_PORT_INVERT_2_INPT_OFST (16)
#define ADC_PORT_INVERT_2_INPT_MSK (0x000000FF << ADC_PORT_INVERT_2_INPT_OFST)
#define ADC_PORT_INVERT_3_INPT_OFST (24)
#define ADC_PORT_INVERT_3_INPT_MSK (0x000000FF << ADC_PORT_INVERT_3_INPT_OFST)
/* Dummy RW register */
#define DUMMY_REG (0x44 << MEM_MAP_SHIFT)
#define DUMMY_FIFO_CHNNL_SLCT_OFST (0)
#define DUMMY_FIFO_CHNNL_SLCT_MSK (0x0000003F << DUMMY_FIFO_CHNNL_SLCT_OFST)
#define DUMMY_ANLG_FIFO_RD_STRBE_OFST (8)
#define DUMMY_ANLG_FIFO_RD_STRBE_MSK (0x00000001 << DUMMY_ANLG_FIFO_RD_STRBE_OFST)
#define DUMMY_DGTL_FIFO_RD_STRBE_OFST (9)
#define DUMMY_DGTL_FIFO_RD_STRBE_MSK (0x00000001 << DUMMY_DGTL_FIFO_RD_STRBE_OFST)
/* Receiver IP Address RW register */
#define RX_IP_REG (0x45 << MEM_MAP_SHIFT)
/* UDP Port RW register */
#define UDP_PORT_REG (0x46 << MEM_MAP_SHIFT)
#define UDP_PORT_RX_OFST (0)
#define UDP_PORT_RX_MSK (0x0000FFFF << UDP_PORT_RX_OFST)
#define UDP_PORT_TX_OFST (16)
#define UDP_PORT_TX_MSK (0x0000FFFF << UDP_PORT_TX_OFST)
/* Receiver Mac Address 64 bit RW register */
#define RX_MAC_LSB_REG (0x47 << MEM_MAP_SHIFT)
#define RX_MAC_MSB_REG (0x48 << MEM_MAP_SHIFT)
#define RX_MAC_LSB_OFST (0)
#define RX_MAC_LSB_MSK (0xFFFFFFFF << RX_MAC_LSB_OFST)
#define RX_MAC_MSB_OFST (0)
#define RX_MAC_MSB_MSK (0x0000FFFF << RX_MAC_MSB_OFST)
/* Detector/ Transmitter Mac Address 64 bit RW register */
#define TX_MAC_LSB_REG (0x49 << MEM_MAP_SHIFT)
#define TX_MAC_MSB_REG (0x4A << MEM_MAP_SHIFT)
#define TX_MAC_LSB_OFST (0)
#define TX_MAC_LSB_MSK (0xFFFFFFFF << TX_MAC_LSB_OFST)
#define TX_MAC_MSB_OFST (0)
#define TX_MAC_MSB_MSK (0x0000FFFF << TX_MAC_MSB_OFST)
/* Detector/ Transmitter IP Address RW register */
#define TX_IP_REG (0x4B << MEM_MAP_SHIFT)
/* Detector/ Transmitter IP Checksum RW register */
#define TX_IP_CHECKSUM_REG (0x4C << MEM_MAP_SHIFT)
#define TX_IP_CHECKSUM_OFST (0)
#define TX_IP_CHECKSUM_MSK (0x0000FFFF << TX_IP_CHECKSUM_OFST)
/* Configuration RW register */
#define CONFIG_REG (0x4D << MEM_MAP_SHIFT)
#define CONFIG_LED_DSBL_OFST (0)
#define CONFIG_LED_DSBL_MSK (0x00000001 << CONFIG_LED_DSBL_OFST)
#define CONFIG_DSBL_ANLG_OTPT_OFST (8)
#define CONFIG_DSBL_ANLG_OTPT_MSK (0x00000001 << CONFIG_DSBL_ANLG_OTPT_OFST)
#define CONFIG_ENBLE_DGTL_OTPT_OFST (9)
#define CONFIG_ENBLE_DGTL_OTPT_MSK (0x00000001 << CONFIG_ENBLE_DGTL_OTPT_OFST)
#define CONFIG_GB10_SND_UDP_OFST (12)
#define CONFIG_GB10_SND_UDP_MSK (0x00000001 << CONFIG_GB10_SND_UDP_OFST)
/* External Signal RW register */
#define EXT_SIGNAL_REG (0x4E << MEM_MAP_SHIFT)
#define EXT_SIGNAL_OFST (0)
#define EXT_SIGNAL_MSK (0x00000001 << EXT_SIGNAL_OFST)
#define EXT_SIGNAL_AUTO_VAL ((0x0 << EXT_SIGNAL_OFST) & EXT_SIGNAL_MSK)
#define EXT_SIGNAL_TRGGR_VAL ((0x1 << EXT_SIGNAL_OFST) & EXT_SIGNAL_MSK)
/* Control RW register */
#define CONTROL_REG (0x4F << MEM_MAP_SHIFT)
#define CONTROL_STRT_ACQSTN_OFST (0)
#define CONTROL_STRT_ACQSTN_MSK (0x00000001 << CONTROL_STRT_ACQSTN_OFST)
#define CONTROL_STP_ACQSTN_OFST (1)
#define CONTROL_STP_ACQSTN_MSK (0x00000001 << CONTROL_STP_ACQSTN_OFST)
//#define CONTROL_STRT_FF_TST_OFST (2)
//#define CONTROL_STRT_FF_TST_MSK (0x00000001 << CONTROL_STRT_FF_TST_OFST)
//#define CONTROL_STP_FF_TST_OFST (3)
//#define CONTROL_STP_FF_TST_MSK (0x00000001 << CONTROL_STP_FF_TST_OFST)
//#define CONTROL_STRT_RDT_OFST (4)
//#define CONTROL_STRT_RDT_MSK (0x00000001 << CONTROL_STRT_RDT_OFST)
//#define CONTROL_STP_RDT_OFST (5)
//#define CONTROL_STP_RDT_MSK (0x00000001 << CONTROL_STP_RDT_OFST)
#define CONTROL_STRT_EXPSR_OFST (6)
#define CONTROL_STRT_EXPSR_MSK (0x00000001 << CONTROL_STRT_RDT_OFST)
//#define CONTROL_STP_EXPSR_OFST (7)
//#define CONTROL_STP_EXPSR_MSK (0x00000001 << CONTROL_STP_RDT_OFST)
//#define CONTROL_STRT_TRN_OFST (8)
//#define CONTROL_STRT_TRN_MSK (0x00000001 << CONTROL_STRT_RDT_OFST)
//#define CONTROL_STP_TRN_OFST (9)
//#define CONTROL_STP_TRN_MSK (0x00000001 << CONTROL_STP_RDT_OFST)
#define CONTROL_CRE_RST_OFST (10)
#define CONTROL_CRE_RST_MSK (0x00000001 << CONTROL_CRE_RST_OFST)
#define CONTROL_PRPHRL_RST_OFST (11) // Only GBE10?
#define CONTROL_PRPHRL_RST_MSK (0x00000001 << CONTROL_PRPHRL_RST_OFST)
#define CONTROL_MMRY_RST_OFST (12)
#define CONTROL_MMRY_RST_MSK (0x00000001 << CONTROL_MMRY_RST_OFST)
//#define CONTROL_PLL_RCNFG_WR_OFST (13)
//#define CONTROL_PLL_RCNFG_WR_MSK (0x00000001 << CONTROL_PLL_RCNFG_WR_OFST)
#define CONTROL_SND_10GB_PCKT_OFST (14)
#define CONTROL_SND_10GB_PCKT_MSK (0x00000001 << CONTROL_SND_10GB_PCKT_OFST)
#define CONTROL_CLR_ACQSTN_FIFO_OFST (15)
#define CONTROL_CLR_ACQSTN_FIFO_MSK (0x00000001 << CONTROL_CLR_ACQSTN_FIFO_OFST)
/* Reconfiguratble PLL Paramater RW register */
#define PLL_PARAM_REG (0x50 << MEM_MAP_SHIFT)
/* Reconfiguratble PLL Control RW regiser */
#define PLL_CNTRL_REG (0x51 << MEM_MAP_SHIFT)
#define PLL_CNTRL_RCNFG_PRMTR_RST_OFST (0)
#define PLL_CNTRL_RCNFG_PRMTR_RST_MSK (0x00000001 << PLL_CNTRL_RCNFG_PRMTR_RST_OFST)
#define PLL_CNTRL_WR_PRMTR_OFST (2)
#define PLL_CNTRL_WR_PRMTR_MSK (0x00000001 << PLL_CNTRL_WR_PRMTR_OFST)
#define PLL_CNTRL_PLL_RST_OFST (3)
#define PLL_CNTRL_PLL_RST_MSK (0x00000001 << PLL_CNTRL_PLL_RST_OFST)
#define PLL_CNTRL_ADDR_OFST (16)
#define PLL_CNTRL_ADDR_MSK (0x0000003F << PLL_CNTRL_ADDR_OFST)
/* Pattern Control RW register */
#define PATTERN_CNTRL_REG (0x52 << MEM_MAP_SHIFT)
#define PATTERN_CNTRL_WR_OFST (0)
#define PATTERN_CNTRL_WR_MSK (0x00000001 << PATTERN_CNTRL_WR_OFST)
#define PATTERN_CNTRL_RD_OFST (1)
#define PATTERN_CNTRL_RD_MSK (0x00000001 << PATTERN_CNTRL_RD_OFST)
#define PATTERN_CNTRL_ADDR_OFST (16)
#define PATTERN_CNTRL_ADDR_MSK (0x0000FFFF << PATTERN_CNTRL_ADDR_OFST)
/* Pattern Limit RW regiser */
#define PATTERN_LIMIT_REG (0x53 << MEM_MAP_SHIFT)
/* Pattern Loop 0 Address RW regiser */
#define PATTERN_LOOP_0_ADDR_REG (0x54 << MEM_MAP_SHIFT)
#define PATTERN_LOOP_0_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_0_ADDR_STRT_MSK (0x0000FFFF << PATTERN_LOOP_0_ADDR_STRT_OFST)
#define PATTERN_LOOP_0_ADDR_STP_OFST (16)
#define PATTERN_LOOP_0_ADDR_STP_MSK (0x0000FFFF << PATTERN_LOOP_0_ADDR_STP_OFST)
/* Pattern Loop 0 Iteration RW regiser */
#define PATTERN_LOOP_0_ITERATION_REG (0x55 << MEM_MAP_SHIFT)
/* Pattern Loop 1 Address RW regiser */
#define PATTERN_LOOP_1_ADDR_REG (0x56 << MEM_MAP_SHIFT)
#define PATTERN_LOOP_1_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_1_ADDR_STRT_MSK (0x0000FFFF << PATTERN_LOOP_1_ADDR_STRT_OFST)
#define PATTERN_LOOP_1_ADDR_STP_OFST (16)
#define PATTERN_LOOP_1_ADDR_STP_MSK (0x0000FFFF << PATTERN_LOOP_1_ADDR_STP_OFST)
/* Pattern Loop 1 Iteration RW regiser */
#define PATTERN_LOOP_1_ITERATION_REG (0x57 << MEM_MAP_SHIFT)
/* Pattern Loop 2 Address RW regiser */
#define PATTERN_LOOP_2_ADDR_REG (0x58 << MEM_MAP_SHIFT)
#define PATTERN_LOOP_2_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_2_ADDR_STRT_MSK (0x0000FFFF << PATTERN_LOOP_2_ADDR_STRT_OFST)
#define PATTERN_LOOP_2_ADDR_STP_OFST (16)
#define PATTERN_LOOP_2_ADDR_STP_MSK (0x0000FFFF << PATTERN_LOOP_2_ADDR_STP_OFST)
/* Pattern Loop 2 Iteration RW regiser */
#define PATTERN_LOOP_2_ITERATION_REG (0x59 << MEM_MAP_SHIFT)
/* Pattern Wait 0 RW regiser */
#define PATTERN_WAIT_0_ADDR_REG (0x5A << MEM_MAP_SHIFT)
#define PATTERN_WAIT_0_ADDR_OFST (0)
#define PATTERN_WAIT_0_ADDR_MSK (0x0000FFFF << PATTERN_WAIT_0_ADDR_OFST)
//FIXME: is mask 3FF
/* Pattern Wait 1 RW regiser */
#define PATTERN_WAIT_1_ADDR_REG (0x5B << MEM_MAP_SHIFT)
#define PATTERN_WAIT_1_ADDR_OFST (0)
#define PATTERN_WAIT_1_ADDR_MSK (0x0000FFFF << PATTERN_WAIT_1_ADDR_OFST)
/* Pattern Wait 2 RW regiser */
#define PATTERN_WAIT_2_ADDR_REG (0x5C << MEM_MAP_SHIFT)
#define PATTERN_WAIT_2_ADDR_OFST (0)
#define PATTERN_WAIT_2_ADDR_MSK (0x0000FFFF << PATTERN_WAIT_2_ADDR_OFST)
/* Samples RW register */
#define SAMPLES_REG (0x5D << MEM_MAP_SHIFT)
/** Power RW register */
#define POWER_REG (0x5E << MEM_MAP_SHIFT)
#define POWER_ENBL_VLTG_RGLTR_OFST (16)
#define POWER_ENBL_VLTG_RGLTR_MSK (0x0000001F << POWER_ENBL_VLTG_RGLTR_OFST)
#define POWER_HV_SLCT_OFST (31)
#define POWER_HV_SLCT_MSK (0x00000001 << POWER_HV_SLCT_OFST)
/* Number of Words RW register TODO */
#define NUMBER_OF_WORDS_REG (0x5F << MEM_MAP_SHIFT)
/* Delay 64 bit RW register. t = DLY x 50 ns. */
#define DELAY_LSB_REG (0x60 << MEM_MAP_SHIFT)
#define DELAY_MSB_REG (0x61 << MEM_MAP_SHIFT)
/* Cycles 64 bit RW register */
#define CYCLES_LSB_REG (0x62 << MEM_MAP_SHIFT)
#define CYCLES_MSB_REG (0x63 << MEM_MAP_SHIFT)
/* Frames 64 bit RW register */
#define FRAMES_LSB_REG (0x64 << MEM_MAP_SHIFT)
#define FRAMES_MSB_REG (0x65 << MEM_MAP_SHIFT)
/* Period 64 bit RW register */
#define PERIOD_LSB_REG (0x66 << MEM_MAP_SHIFT)
#define PERIOD_MSB_REG (0x67 << MEM_MAP_SHIFT)
/* Period 64 bit RW register */
//#define EXPTIME_LSB_REG (0x68 << MEM_MAP_SHIFT) // Not used in FW
//#define EXPTIME_MSB_REG (0x69 << MEM_MAP_SHIFT) // Not used in FW
/* Gates 64 bit RW register */
//#define GATES_LSB_REG (0x6A << MEM_MAP_SHIFT) // Not used in FW
//#define GATES_MSB_REG (0x6B << MEM_MAP_SHIFT) // Not used in FW
/* Pattern IO Control 64 bit RW regiser
* Each bit configured as output(1)/ input(0) */
#define PATTERN_IO_CNTRL_LSB_REG (0x6C << MEM_MAP_SHIFT)
#define PATTERN_IO_CNTRL_MSB_REG (0x6D << MEM_MAP_SHIFT)
/* Pattern IO Clock Control 64 bit RW regiser
* When bit n enabled (1), clocked output for DIO[n] (T run clock)
* When bit n disabled (0), Dio[n] driven by its pattern output */
#define PATTERN_IO_CLK_CNTRL_LSB_REG (0x6E << MEM_MAP_SHIFT)
#define PATTERN_IO_CLK_CNTRL_MSB_REG (0x6F << MEM_MAP_SHIFT)
/* Pattern In 64 bit RW register */
#define PATTERN_IN_LSB_REG (0x70 << MEM_MAP_SHIFT)
#define PATTERN_IN_MSB_REG (0x71 << MEM_MAP_SHIFT)
/* Pattern Wait Timer 0 64 bit RW register. t = PWT1 x T run clock */
#define PATTERN_WAIT_TIMER_0_LSB_REG (0x72 << MEM_MAP_SHIFT)
#define PATTERN_WAIT_TIMER_0_MSB_REG (0x73 << MEM_MAP_SHIFT)
/* Pattern Wait Timer 1 64 bit RW register. t = PWT2 x T run clock */
#define PATTERN_WAIT_TIMER_1_LSB_REG (0x74 << MEM_MAP_SHIFT)
#define PATTERN_WAIT_TIMER_1_MSB_REG (0x75 << MEM_MAP_SHIFT)
/* Pattern Wait Timer 2 64 bit RW register. t = PWT3 x T run clock */
#define PATTERN_WAIT_TIMER_2_LSB_REG (0x76 << MEM_MAP_SHIFT)
#define PATTERN_WAIT_TIMER_2_MSB_REG (0x77 << MEM_MAP_SHIFT)
/* ADC Disable RW register TODO */
#define ADC_DISABLE_REG (0x78 << MEM_MAP_SHIFT)
/* DAC Value RW register TODO */
//#define DAC_VALUE_REG (0x79 << MEM_MAP_SHIFT)
/* DAC Number RW register TODO */
//#define DAC_NUMBER_REG (0x7A << MEM_MAP_SHIFT)
/* Digital Bit External Trigger RW register */
#define DBIT_EXT_TRG_REG (0x7B << MEM_MAP_SHIFT)
#define DBIT_EXT_TRG_SRC_OFST (0)
#define DBIT_EXT_TRG_SRC_MSK (0x0000003F << DBIT_EXT_TRG_SRC_OFST)
#define DBIT_EXT_TRG_OPRTN_MD_OFST (16)
#define DBIT_EXT_TRG_OPRTN_MD_MSK (0x00000001 << DBIT_EXT_TRG_OPRTN_MD_OFST)
/* Pin Delay 0 RW register */
#define PIN_DELAY_0_REG (0x7C << MEM_MAP_SHIFT)
#define PIN_DELAY_0_OTPT_STTNG_OFST (0) //t = OTPT_STTNG * 25 ps, max for Cyclone V = 775 ps
#define PIN_DELAY_0_OTPT_STTNG_MSK (0x0000001F << PIN_DELAY_0_OFST)
#define PIN_DELAY_0_OTPT_TRGGR_OFST (31)
#define PIN_DELAY_0_OTPT_TRGGR_MSK (0x00000001 << PIN_DELAY_0_OFST)
#define PIN_DELAY_0_OTPT_TRGGR_LD_VAL (1)
#define PIN_DELAY_0_OTPT_TRGGR_STRT_VAL (0)
/* Pin Delay 1 RW register
* Each bit configured as enable for dynamic output delay configuration */
#define PIN_DELAY_1_REG (0x7D << MEM_MAP_SHIFT)
/** I2C Control register */
#define I2C_TRANSFER_COMMAND_FIFO_REG (0x100 << MEM_MAP_SHIFT)
#define I2C_CONTROL_REG (0x102 << MEM_MAP_SHIFT)
#define I2C_RX_DATA_FIFO_LEVEL_REG (0x107 << MEM_MAP_SHIFT)
#define I2C_SCL_LOW_COUNT_REG (0x108 << MEM_MAP_SHIFT)
#define I2C_SCL_HIGH_COUNT_REG (0x109 << MEM_MAP_SHIFT)
#define I2C_SDA_HOLD_REG (0x10A << MEM_MAP_SHIFT)
//fixme: upto 0x10f

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slsDetectorServers/moenchDetectorServer/ansi.h Symbolic link
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../../slsSupportLib/include/ansi.h

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slsDetectorServers/moenchDetectorServer/blackfin.h Symbolic link
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../slsDetectorServer/blackfin.h

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slsDetectorServers/moenchDetectorServer/commonServerFunctions.h Symbolic link
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../slsDetectorServer/commonServerFunctions.h

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slsDetectorServers/moenchDetectorServer/communication_funcs.c Symbolic link
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../slsDetectorServer/communication_funcs.c

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slsDetectorServers/moenchDetectorServer/communication_funcs.h Symbolic link
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../slsDetectorServer/communication_funcs.h

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slsDetectorServers/moenchDetectorServer/gitInfoMoench.h Normal file
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#define GITURL "git@github.com:slsdetectorgroup/slsDetectorPackage.git"
#define GITREPUUID "91dd176a0fb314f583ca6e29140053f1eb742896"
#define GITAUTH "Dhanya_Thattil"
#define GITREV 0x4166
#define GITDATE 0x20181108
#define GITBRANCH "refactor"

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slsDetectorServers/moenchDetectorServer/gitInfoMoenchTmp.h Normal file
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#define GITURL ""
#define GITREPUUID ""
#define GITAUTH ""
#define GITREV ""
#define GITDATE ""
#define GITBRANCH ""

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slsDetectorServers/moenchDetectorServer/logger.h Symbolic link
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../slsDetectorServer/logger.h

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slsDetectorServers/moenchDetectorServer/programfpga.h Symbolic link
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../slsDetectorServer/programfpga.h

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slsDetectorServers/moenchDetectorServer/slsDetectorFunctionList.c Normal file
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slsDetectorServers/moenchDetectorServer/slsDetectorFunctionList.h Symbolic link
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../slsDetectorServer/slsDetectorFunctionList.h

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slsDetectorServers/moenchDetectorServer/slsDetectorServer.c Symbolic link
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../slsDetectorServer/slsDetectorServer.c

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slsDetectorServers/moenchDetectorServer/slsDetectorServer_defs.h Normal file
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#pragma once
#include "sls_detector_defs.h"
#include "RegisterDefs.h"
#define GOODBYE (-200)
#define MIN_REQRD_VRSN_T_RD_API 0x180314
#define REQRD_FRMWR_VRSN 0x180314
#define PROGRAMMING_MODE (0x2)
#define CTRL_SRVR_INIT_TIME_US (300 * 1000)
/* Struct Definitions */
typedef struct ip_header_struct {
uint16_t ip_len;
uint8_t ip_tos;
uint8_t ip_ihl:4 ,ip_ver:4;
uint16_t ip_offset:13,ip_flag:3;
uint16_t ip_ident;
uint16_t ip_chksum;
uint8_t ip_protocol;
uint8_t ip_ttl;
uint32_t ip_sourceip;
uint32_t ip_destip;
} ip_header;
/* Enums */
enum CLKINDEX {RUN_CLK, ADC_CLK, SYNC_CLK, DBIT_CLK, NUM_CLOCKS};
enum ADCINDEX {V_PWR_IO, V_PWR_A, V_PWR_B, V_PWR_C, V_PWR_D, I_PWR_IO, I_PWR_A, I_PWR_B, I_PWR_C, I_PWR_D};
enum DACINDEX {D0, D1, D2, D3, D4, D5, D6, D7, D8, D9,
D10, D11, D12, D13, D14, D15, D16, D17,
D_PWR_D, D_PWR_CHIP, D_PWR_C, D_PWR_B, D_PWR_A, D_PWR_IO};
/* Hardware Definitions */
#define NCHAN (36)
#define NCHAN_ANALOG (32)
#define NCHAN_DIGITAL (4)
#define NCHIP (1)
#define NDAC (24)
#define NPWR (6)
#define NDAC_ONLY (NDAC - NPWR)
//#define N_DAC (24)
//#define N_PWR (5)
//#define NADC (9)
//#define DAC_CMD_OFF 20
#define DYNAMIC_RANGE (16)
#define NUM_BYTES_PER_PIXEL (DYNAMIC_RANGE / 8)
#define CLK_FREQ (156.25) /* MHz */
#define I2C_POWER_VIO_DEVICE_ID (0x40)
#define I2C_POWER_VA_DEVICE_ID (0x41)
#define I2C_POWER_VB_DEVICE_ID (0x42)
#define I2C_POWER_VC_DEVICE_ID (0x43)
#define I2C_POWER_VD_DEVICE_ID (0x44)
#define I2C_SHUNT_RESISTER_OHMS (0.005)
/** Default Parameters */
#define DEFAULT_DATA_BYTES (NCHIP * NCHAN * NUM_BITS_PER_PIXEL)
#define DEFAULT_NUM_SAMPLES (1)
#define DEFAULT_NUM_FRAMES (100 * 1000 * 1000)
#define DEFAULT_NUM_CYCLES (1)
#define DEFAULT_PERIOD (1 * 1000 * 1000) //ns
#define DEFAULT_DELAY (0)
#define DEFAULT_HIGH_VOLTAGE (0)
#define DEFAULT_VLIMIT (-100)
#define DEFAULT_TIMING_MODE (AUTO_TIMING)
#define DEFAULT_TX_UDP_PORT (0x7e9a)
/* Defines in the Firmware */
#define WAIT_TME_US_FR_LK_AT_ME_REG (100) // wait time in us after acquisition done to ensure there is no data in fifo
#define WAIT_TIME_US_PLL (10 * 1000)
#define WAIT_TIME_US_STP_ACQ (100)
#define WAIT_TIME_CONFIGURE_MAC (500 * 1000)
#define MAX_DAC_VOLTAGE_VALUE (2500)
#define DAC_MAX_VOLTAGE_MV (2500)
#define VCHIP_MAX_MV (2700)
#define VCHIP_MIN_MV (1700)
#define POWER_RGLTR_MAX (2500)
#define POWER_RGLTR_MIN (600)
#define VCHIP_POWER_INCRMNT (200)
#define IP_PACKETSIZE (0x2032)
#define ADC_PORT_INVERT_VAL (0x453b2593) //FIXME: a default value?
#define MAXIMUM_ADC_CLK (40)
#define PLL_VCO_FREQ_MHZ (400)
/* MSB & LSB DEFINES */
#define MSB_OF_64_BIT_REG_OFST (32)
#define LSB_OF_64_BIT_REG_OFST (0)
#define BIT_32_MSK (0xFFFFFFFF)
/** PLL Reconfiguration Registers */
//https://www.altera.com/documentation/mcn1424769382940.html
#define PLL_MODE_REG (0x00)
#define PLL_MODE_WT_RQUST_VAL (0)
#define PLL_MODE_PLLNG_MD_VAL (1)
#define PLL_STATUS_REG (0x01)
#define PLL_START_REG (0x02)
#define PLL_N_COUNTER_REG (0x03)
#define PLL_M_COUNTER_REG (0x04)
#define PLL_C_COUNTER_REG (0x05)
#define PLL_C_COUNTER_LW_CNT_OFST (0)
#define PLL_C_COUNTER_LW_CNT_MSK (0x000000FF << PLL_C_COUNTER_LW_CNT_OFST)
#define PLL_C_COUNTER_HGH_CNT_OFST (8)
#define PLL_C_COUNTER_HGH_CNT_MSK (0x000000FF << PLL_C_COUNTER_HGH_CNT_OFST)
/* total_div = lw_cnt + hgh_cnt */
#define PLL_C_COUNTER_BYPSS_ENBL_OFST (16)
#define PLL_C_COUNTER_BYPSS_ENBL_MSK (0x00000001 << PLL_C_COUNTER_BYPSS_ENBL_OFST)
/* if bypss_enbl = 0, fout = f(vco)/total_div; else fout = f(vco) (c counter is bypassed) */
#define PLL_C_COUNTER_ODD_DVSN_OFST (17)
#define PLL_C_COUNTER_ODD_DVSN_MSK (0x00000001 << PLL_C_COUNTER_ODD_DVSN_OFST)
/** if odd_dvsn = 0 (even), duty cycle = hgh_cnt/ total_div; else duty cycle = (hgh_cnt - 0.5) / total_div */
#define PLL_C_COUNTER_SLCT_OFST (18)
#define PLL_C_COUNTER_SLCT_MSK (0x0000001F << PLL_C_COUNTER_SLCT_OFST)
#define PLL_PHASE_SHIFT_REG (0x06)
#define PLL_SHIFT_NUM_SHIFTS_OFST (0)
#define PLL_SHIFT_NUM_SHIFTS_MSK (0x0000FFFF << PLL_SHIFT_NUM_SHIFTS_OFST)
#define PLL_SHIFT_CNT_SELECT_OFST (16)
#define PLL_SHIFT_CNT_SELECT_MSK (0x0000001F << PLL_SHIFT_CNT_SELECT_OFST)
#define PLL_SHIFT_CNT_SLCT_C0_VAL ((0x0 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
#define PLL_SHIFT_CNT_SLCT_C1_VAL ((0x1 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
#define PLL_SHIFT_CNT_SLCT_C2_VAL ((0x2 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
#define PLL_SHIFT_CNT_SLCT_C3_VAL ((0x3 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
#define PLL_SHIFT_CNT_SLCT_C4_VAL ((0x4 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
#define PLL_SHIFT_CNT_SLCT_C5_VAL ((0x5 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
#define PLL_SHIFT_CNT_SLCT_C6_VAL ((0x6 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
#define PLL_SHIFT_CNT_SLCT_C7_VAL ((0x7 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
#define PLL_SHIFT_CNT_SLCT_C8_VAL ((0x8 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
#define PLL_SHIFT_CNT_SLCT_C9_VAL ((0x9 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
#define PLL_SHIFT_CNT_SLCT_C10_VAL ((0x10 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
#define PLL_SHIFT_CNT_SLCT_C11_VAL ((0x11 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
#define PLL_SHIFT_CNT_SLCT_C12_VAL ((0x12 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
#define PLL_SHIFT_CNT_SLCT_C13_VAL ((0x13 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
#define PLL_SHIFT_CNT_SLCT_C14_VAL ((0x14 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
#define PLL_SHIFT_CNT_SLCT_C15_VAL ((0x15 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
#define PLL_SHIFT_CNT_SLCT_C16_VAL ((0x16 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
#define PLL_SHIFT_CNT_SLCT_C17_VAL ((0x17 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
#define PLL_SHIFT_UP_DOWN_OFST (21)
#define PLL_SHIFT_UP_DOWN_MSK (0x00000001 << PLL_SHIFT_UP_DOWN_OFST)
#define PLL_SHIFT_UP_DOWN_NEG_VAL ((0x0 << PLL_SHIFT_UP_DOWN_OFST) & PLL_SHIFT_UP_DOWN_MSK)
#define PLL_SHIFT_UP_DOWN_POS_VAL ((0x1 << PLL_SHIFT_UP_DOWN_OFST) & PLL_SHIFT_UP_DOWN_MSK)
#define PLL_K_COUNTER_REG (0x07)
#define PLL_BANDWIDTH_REG (0x08)
#define PLL_CHARGEPUMP_REG (0x09)
#define PLL_VCO_DIV_REG (0x1c)
#define PLL_MIF_REG (0x1f)

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slsDetectorServers/moenchDetectorServer/slsDetectorServer_funcs.c Symbolic link
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../slsDetectorServer/slsDetectorServer_funcs.c

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slsDetectorServers/moenchDetectorServer/slsDetectorServer_funcs.h Symbolic link
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../slsDetectorServer/slsDetectorServer_funcs.h

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slsDetectorServers/moenchDetectorServer/sls_detector_defs.h Symbolic link
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../../slsSupportLib/include/sls_detector_defs.h

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slsDetectorServers/moenchDetectorServer/sls_detector_funcs.h Symbolic link
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../../slsSupportLib/include/sls_detector_funcs.h

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slsDetectorServers/moenchDetectorServer/updateAPIVersion.sh Executable file
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SRCFILE=gitInfoMoench.h
DSTFILE=versionAPI.h
SRCPATTERN=GITDATE
DSTPATTERN=APIMOENCH
awk -v a="$SRCFILE" -v b="$DSTFILE" -v c="$SRCPATTERN" -v d="$DSTPATTERN" 'FNR==NR&&$2==c{x=$3} NR!=FNR{if($2==d){$3="0x"substr(x,5)}print > b}' $SRCFILE $DSTFILE

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slsDetectorServers/moenchDetectorServer/updateGitVersion.sh Executable file
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SERVER=moenchDetectorServer
MAINDIR=slsDetectorPackage
SPECDIR=slsDetectorServers/$SERVER
TMPFILE=gitInfoMoenchTmp.h
INCLFILE=gitInfoMoench.h
#evaluate the variables
EVALFILE=../../evalVersionVariables.sh
source $EVALFILE
#get modified date
#RDATE1='git log --pretty=format:"%ci" -1'
RDATE1="find ../slsDetectorServer . -type f -exec stat --format '%Y :%y %n' '{}' \; | sort -nr | cut -d: -f2- | egrep -v 'gitInfo|bin|.git|updateGitVersion|.o' | head -n 1"
RDATE=`eval $RDATE1`
NEWDATE=$(sed "s/-//g" <<< $RDATE | awk '{print $1;}')
NEWDATE=${NEWDATE/#/0x}
#get old date from INCLFILE
OLDDATE=$(more $INCLFILE | grep '#define GITDATE' | awk '{print $3}')
#update INCLFILE if changes
if [ "$OLDDATE" != "$NEWDATE" ]; then
echo Path: ${MAINDIR}/${SPECDIR} $'\n'URL: ${GITREPO} $'\n'Repository Root: ${GITREPO} $'\n'Repsitory UUID: ${REPUID} $'\n'Revision: ${FOLDERREV} $'\n'Branch: ${BRANCH} $'\n'Last Changed Author: ${AUTH1}_${AUTH2} $'\n'Last Changed Rev: ${REV} $'\n'Last Changed Date: ${RDATE} > gitInfo.txt
cd ../../
./genVersionHeader.sh $SPECDIR/gitInfo.txt $SPECDIR/$TMPFILE $SPECDIR/$INCLFILE
cd $WD
fi

1
slsDetectorServers/moenchDetectorServer/versionAPI.h Symbolic link
View File

@ -0,0 +1 @@
../../slsSupportLib/include/versionAPI.h

10
slsDetectorServers/slsDetectorServer/MAX1932.h
View File

@ -52,13 +52,13 @@ void MAX1932_Configure(){
/**
* Set
* @param dacnum dac number
* @param data dac value to set
* Set value
* @param val value to set
*/
void MAX1932_Set (int dacnum, int data) {
FILE_LOG(logDEBUG1, ("\tSetting dac %d to %d\n", dacnum, data));
void MAX1932_Set (int val) {
FILE_LOG(logDEBUG1, ("\tSetting high voltage to %d\n", val));
}