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m3: trigger enable moved to config reg, always enabling trigger flow for all timing modes for m3

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This commit is contained in:
maliakal_d 2020-10-15 09:27:06 +02:00
parent 3021594e20
commit 9f2bc85a18
2 changed files with 16 additions and 9 deletions
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11
slsDetectorServers/mythen3DetectorServer/RegisterDefs.h
View File

@ -119,6 +119,9 @@
#define CONFIG_DYNAMIC_RANGE_8_VAL ((0x1 << CONFIG_DYNAMIC_RANGE_OFST) & CONFIG_DYNAMIC_RANGE_MSK) #define CONFIG_DYNAMIC_RANGE_8_VAL ((0x1 << CONFIG_DYNAMIC_RANGE_OFST) & CONFIG_DYNAMIC_RANGE_MSK)
#define CONFIG_DYNAMIC_RANGE_16_VAL ((0x2 << CONFIG_DYNAMIC_RANGE_OFST) & CONFIG_DYNAMIC_RANGE_MSK) #define CONFIG_DYNAMIC_RANGE_16_VAL ((0x2 << CONFIG_DYNAMIC_RANGE_OFST) & CONFIG_DYNAMIC_RANGE_MSK)
#define CONFIG_DYNAMIC_RANGE_24_VAL ((0x3 << CONFIG_DYNAMIC_RANGE_OFST) & CONFIG_DYNAMIC_RANGE_MSK) #define CONFIG_DYNAMIC_RANGE_24_VAL ((0x3 << CONFIG_DYNAMIC_RANGE_OFST) & CONFIG_DYNAMIC_RANGE_MSK)
#define CONFIG_TRIGGER_ENA_OFST (8)
#define CONFIG_TRIGGER_ENA_MSK (0x00000001 << CONGIG_TRIGGER_ENA_OFST)
/* Control RW register */ /* Control RW register */
#define CONTROL_REG (0x21 * REG_OFFSET + BASE_CONTROL) #define CONTROL_REG (0x21 * REG_OFFSET + BASE_CONTROL)
@ -466,11 +469,11 @@
#define SET_PERIOD_LSB_REG (0x28 * REG_OFFSET + BASE_FLOW_CONTROL) #define SET_PERIOD_LSB_REG (0x28 * REG_OFFSET + BASE_FLOW_CONTROL)
#define SET_PERIOD_MSB_REG (0x29 * REG_OFFSET + BASE_FLOW_CONTROL) #define SET_PERIOD_MSB_REG (0x29 * REG_OFFSET + BASE_FLOW_CONTROL)
/* External Signal register */ /* Flow Trigger register (for all timing modes) */
#define EXT_SIGNAL_REG (0x30 * REG_OFFSET + BASE_FLOW_CONTROL) #define FLOW_TRIGGER_REG (0x30 * REG_OFFSET + BASE_FLOW_CONTROL)
#define EXT_SIGNAL_OFST (0) #define FLOW_TRIGGER_OFST (0)
#define EXT_SIGNAL_MSK (0x00000001 << EXT_SIGNAL_OFST) #define FLOW_TRIGGER_MSK (0x00000001 << FLOW_TRIGGER_OFST)
/* Trigger Delay 64 bit register */ /* Trigger Delay 64 bit register */
#define SET_TRIGGER_DELAY_LSB_REG (0x32 * REG_OFFSET + BASE_FLOW_CONTROL) #define SET_TRIGGER_DELAY_LSB_REG (0x32 * REG_OFFSET + BASE_FLOW_CONTROL)

14
slsDetectorServers/mythen3DetectorServer/slsDetectorFunctionList.c
View File

@ -422,6 +422,9 @@ void setupDetector() {
setASICDefaults(); setASICDefaults();
setADIFDefaults(); setADIFDefaults();
// set trigger flow for m3 (for all timing modes)
bus_w(FLOW_TRIGGER_REG, bus_r(FLOW_TRIGGER_REG) | FLOW_TRIGGER_MSK);
// dynamic range // dynamic range
setDynamicRange(DEFAULT_DYNAMIC_RANGE); setDynamicRange(DEFAULT_DYNAMIC_RANGE);
// enable all counters // enable all counters
@ -1347,29 +1350,30 @@ int setHighVoltage(int val) {
/* parameters - timing */ /* parameters - timing */
void setTiming(enum timingMode arg) { void setTiming(enum timingMode arg) {
uint32_t addr = CONFIG_REG;
switch (arg) { switch (arg) {
case AUTO_TIMING: case AUTO_TIMING:
LOG(logINFO, ("Set Timing: Auto (Int. Trigger, Int. Gating)\n")); LOG(logINFO, ("Set Timing: Auto (Int. Trigger, Int. Gating)\n"));
bus_w(EXT_SIGNAL_REG, bus_r(EXT_SIGNAL_REG) & ~EXT_SIGNAL_MSK); bus_w(addr, bus_r(addr) & ~CONFIG_TRIGGER_ENA_MSK);
bus_w(ASIC_EXP_STATUS_REG, bus_w(ASIC_EXP_STATUS_REG,
bus_r(ASIC_EXP_STATUS_REG) & ~ASIC_EXP_STAT_GATE_SRC_EXT_MSK); bus_r(ASIC_EXP_STATUS_REG) & ~ASIC_EXP_STAT_GATE_SRC_EXT_MSK);
break; break;
case TRIGGER_EXPOSURE: case TRIGGER_EXPOSURE:
LOG(logINFO, ("Set Timing: Trigger (Ext. Trigger, Int. Gating)\n")); LOG(logINFO, ("Set Timing: Trigger (Ext. Trigger, Int. Gating)\n"));
bus_w(EXT_SIGNAL_REG, bus_r(EXT_SIGNAL_REG) | EXT_SIGNAL_MSK); bus_w(addr, bus_r(addr) | CONFIG_TRIGGER_ENA_MSK);
bus_w(ASIC_EXP_STATUS_REG, bus_w(ASIC_EXP_STATUS_REG,
bus_r(ASIC_EXP_STATUS_REG) & ~ASIC_EXP_STAT_GATE_SRC_EXT_MSK); bus_r(ASIC_EXP_STATUS_REG) & ~ASIC_EXP_STAT_GATE_SRC_EXT_MSK);
break; break;
case GATED: case GATED:
LOG(logINFO, ("Set Timing: Gating (Int. Trigger, Ext. Gating)\n")); LOG(logINFO, ("Set Timing: Gating (Int. Trigger, Ext. Gating)\n"));
bus_w(EXT_SIGNAL_REG, bus_r(EXT_SIGNAL_REG) & ~EXT_SIGNAL_MSK); bus_w(addr, bus_r(addr) & ~CONFIG_TRIGGER_ENA_MSK);
bus_w(ASIC_EXP_STATUS_REG, bus_w(ASIC_EXP_STATUS_REG,
bus_r(ASIC_EXP_STATUS_REG) | ASIC_EXP_STAT_GATE_SRC_EXT_MSK); bus_r(ASIC_EXP_STATUS_REG) | ASIC_EXP_STAT_GATE_SRC_EXT_MSK);
break; break;
case TRIGGER_GATED: case TRIGGER_GATED:
LOG(logINFO, LOG(logINFO,
("Set Timing: Trigger_Gating (Ext. Trigger, Ext. Gating)\n")); ("Set Timing: Trigger_Gating (Ext. Trigger, Ext. Gating)\n"));
bus_w(EXT_SIGNAL_REG, bus_r(EXT_SIGNAL_REG) | EXT_SIGNAL_MSK); bus_w(addr, bus_r(addr) | CONFIG_TRIGGER_ENA_MSK);
bus_w(ASIC_EXP_STATUS_REG, bus_w(ASIC_EXP_STATUS_REG,
bus_r(ASIC_EXP_STATUS_REG) | ASIC_EXP_STAT_GATE_SRC_EXT_MSK); bus_r(ASIC_EXP_STATUS_REG) | ASIC_EXP_STAT_GATE_SRC_EXT_MSK);
break; break;
@ -1380,7 +1384,7 @@ void setTiming(enum timingMode arg) {
} }
enum timingMode getTiming() { enum timingMode getTiming() {
uint32_t extTrigger = (bus_r(EXT_SIGNAL_REG) & EXT_SIGNAL_MSK); uint32_t extTrigger = (bus_r(CONFIG_REG) & CONFIG_TRIGGER_ENA_MSK);
uint32_t extGate = uint32_t extGate =
(bus_r(ASIC_EXP_STATUS_REG) & ASIC_EXP_STAT_GATE_SRC_EXT_MSK); (bus_r(ASIC_EXP_STATUS_REG) & ASIC_EXP_STAT_GATE_SRC_EXT_MSK);
if (extTrigger) { if (extTrigger) {