From 9f2bc85a189ba524d8419888a3c1c4997d8c26bf Mon Sep 17 00:00:00 2001
From: Dhanya Thattil <dhanya.thattil@psi.ch>
Date: Thu, 15 Oct 2020 09:27:06 +0200
Subject: [PATCH] m3: trigger enable moved to config reg, always enabling
 trigger flow for all timing modes for m3

---
 .../mythen3DetectorServer/RegisterDefs.h           | 11 +++++++----
 .../slsDetectorFunctionList.c                      | 14 +++++++++-----
 2 files changed, 16 insertions(+), 9 deletions(-)

diff --git a/slsDetectorServers/mythen3DetectorServer/RegisterDefs.h b/slsDetectorServers/mythen3DetectorServer/RegisterDefs.h
index cfbd16020..8eb6ebc68 100644
--- a/slsDetectorServers/mythen3DetectorServer/RegisterDefs.h
+++ b/slsDetectorServers/mythen3DetectorServer/RegisterDefs.h
@@ -119,6 +119,9 @@
 #define CONFIG_DYNAMIC_RANGE_8_VAL      ((0x1 << CONFIG_DYNAMIC_RANGE_OFST) & CONFIG_DYNAMIC_RANGE_MSK)
 #define CONFIG_DYNAMIC_RANGE_16_VAL     ((0x2 << CONFIG_DYNAMIC_RANGE_OFST) & CONFIG_DYNAMIC_RANGE_MSK)
 #define CONFIG_DYNAMIC_RANGE_24_VAL     ((0x3 << CONFIG_DYNAMIC_RANGE_OFST) & CONFIG_DYNAMIC_RANGE_MSK)
+#define CONFIG_TRIGGER_ENA_OFST         (8)
+#define CONFIG_TRIGGER_ENA_MSK          (0x00000001 << CONGIG_TRIGGER_ENA_OFST)
+
 
 /* Control RW register */
 #define CONTROL_REG                     (0x21 * REG_OFFSET + BASE_CONTROL)
@@ -466,11 +469,11 @@
 #define SET_PERIOD_LSB_REG              (0x28 * REG_OFFSET + BASE_FLOW_CONTROL)
 #define SET_PERIOD_MSB_REG              (0x29 * REG_OFFSET + BASE_FLOW_CONTROL)
 
-/* External Signal register */
-#define EXT_SIGNAL_REG                  (0x30 * REG_OFFSET + BASE_FLOW_CONTROL)
+/* Flow Trigger register (for all timing modes) */
+#define FLOW_TRIGGER_REG                (0x30 * REG_OFFSET + BASE_FLOW_CONTROL)
 
-#define EXT_SIGNAL_OFST                 (0)
-#define EXT_SIGNAL_MSK                  (0x00000001 << EXT_SIGNAL_OFST)
+#define FLOW_TRIGGER_OFST               (0)
+#define FLOW_TRIGGER_MSK                (0x00000001 << FLOW_TRIGGER_OFST)
 
 /* Trigger Delay 64 bit register */
 #define SET_TRIGGER_DELAY_LSB_REG       (0x32 * REG_OFFSET + BASE_FLOW_CONTROL)
diff --git a/slsDetectorServers/mythen3DetectorServer/slsDetectorFunctionList.c b/slsDetectorServers/mythen3DetectorServer/slsDetectorFunctionList.c
index 73a290e15..bc7d9261c 100644
--- a/slsDetectorServers/mythen3DetectorServer/slsDetectorFunctionList.c
+++ b/slsDetectorServers/mythen3DetectorServer/slsDetectorFunctionList.c
@@ -422,6 +422,9 @@ void setupDetector() {
     setASICDefaults();
     setADIFDefaults();
 
+    // set trigger flow for m3 (for all timing modes)
+    bus_w(FLOW_TRIGGER_REG, bus_r(FLOW_TRIGGER_REG) | FLOW_TRIGGER_MSK);
+
     // dynamic range
     setDynamicRange(DEFAULT_DYNAMIC_RANGE);
     // enable all counters
@@ -1347,29 +1350,30 @@ int setHighVoltage(int val) {
 
 /* parameters - timing */
 void setTiming(enum timingMode arg) {
+    uint32_t addr = CONFIG_REG;
     switch (arg) {
     case AUTO_TIMING:
         LOG(logINFO, ("Set Timing: Auto (Int. Trigger, Int. Gating)\n"));
-        bus_w(EXT_SIGNAL_REG, bus_r(EXT_SIGNAL_REG) & ~EXT_SIGNAL_MSK);
+        bus_w(addr, bus_r(addr) & ~CONFIG_TRIGGER_ENA_MSK);
         bus_w(ASIC_EXP_STATUS_REG,
               bus_r(ASIC_EXP_STATUS_REG) & ~ASIC_EXP_STAT_GATE_SRC_EXT_MSK);
         break;
     case TRIGGER_EXPOSURE:
         LOG(logINFO, ("Set Timing: Trigger (Ext. Trigger, Int. Gating)\n"));
-        bus_w(EXT_SIGNAL_REG, bus_r(EXT_SIGNAL_REG) | EXT_SIGNAL_MSK);
+        bus_w(addr, bus_r(addr) | CONFIG_TRIGGER_ENA_MSK);
         bus_w(ASIC_EXP_STATUS_REG,
               bus_r(ASIC_EXP_STATUS_REG) & ~ASIC_EXP_STAT_GATE_SRC_EXT_MSK);
         break;
     case GATED:
         LOG(logINFO, ("Set Timing: Gating (Int. Trigger, Ext. Gating)\n"));
-        bus_w(EXT_SIGNAL_REG, bus_r(EXT_SIGNAL_REG) & ~EXT_SIGNAL_MSK);
+        bus_w(addr, bus_r(addr) & ~CONFIG_TRIGGER_ENA_MSK);
         bus_w(ASIC_EXP_STATUS_REG,
               bus_r(ASIC_EXP_STATUS_REG) | ASIC_EXP_STAT_GATE_SRC_EXT_MSK);
         break;
     case TRIGGER_GATED:
         LOG(logINFO,
             ("Set Timing: Trigger_Gating (Ext. Trigger, Ext. Gating)\n"));
-        bus_w(EXT_SIGNAL_REG, bus_r(EXT_SIGNAL_REG) | EXT_SIGNAL_MSK);
+        bus_w(addr, bus_r(addr) | CONFIG_TRIGGER_ENA_MSK);
         bus_w(ASIC_EXP_STATUS_REG,
               bus_r(ASIC_EXP_STATUS_REG) | ASIC_EXP_STAT_GATE_SRC_EXT_MSK);
         break;
@@ -1380,7 +1384,7 @@ void setTiming(enum timingMode arg) {
 }
 
 enum timingMode getTiming() {
-    uint32_t extTrigger = (bus_r(EXT_SIGNAL_REG) & EXT_SIGNAL_MSK);
+    uint32_t extTrigger = (bus_r(CONFIG_REG) & CONFIG_TRIGGER_ENA_MSK);
     uint32_t extGate =
         (bus_r(ASIC_EXP_STATUS_REG) & ASIC_EXP_STAT_GATE_SRC_EXT_MSK);
     if (extTrigger) {