mirror of
https://github.com/slsdetectorgroup/slsDetectorPackage.git
synced 2025-06-13 13:27:14 +02:00
updated calibration settings for jungfrau, default special dac values for high gain 0, temporary fix for firmwarebug (config_V11_status has to be flipped to be read)
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@ -842,7 +842,14 @@ int selectStoragecellStart(int pos) {
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offset = CONFIG_V11_STATUS_STRG_CLL_OFST;
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offset = CONFIG_V11_STATUS_STRG_CLL_OFST;
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}
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}
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#endif
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#endif
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int retval = ((bus_r(addr) & mask) >> offset);
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uint32_t regval = bus_r(addr);
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#ifndef VIRTUAL
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// flip all contents of register //TODO FIRMWARE FIX
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if (getChipVersion() == 11) {
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regval ^= BIT32_MASK;
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}
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#endif
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uint32_t retval = ((regval & mask) >> offset);
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if (getChipVersion() == 11) {
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if (getChipVersion() == 11) {
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// get which bit
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// get which bit
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int max = getMaxStoragecellStart();
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int max = getMaxStoragecellStart();
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@ -2164,9 +2171,13 @@ int getFilterResistor() {
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uint32_t addr = CONFIG_V11_REG;
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uint32_t addr = CONFIG_V11_REG;
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#else
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#else
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uint32_t addr = CONFIG_V11_STATUS_REG;
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uint32_t addr = CONFIG_V11_STATUS_REG;
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#endif
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uint32_t regval = bus_r(addr);
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#ifndef VIRTUAL
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regval ^= BIT32_MASK;
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#endif
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#endif
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// 0 for lower value, 1 for higher value
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// 0 for lower value, 1 for higher value
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if (bus_r(addr) & CONFIG_V11_STATUS_FLTR_RSSTR_SMLR_MSK) {
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if (regval & CONFIG_V11_STATUS_FLTR_RSSTR_SMLR_MSK) {
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return 0;
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return 0;
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}
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}
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return 1;
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return 1;
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@ -2197,10 +2208,14 @@ int getFilterCell() {
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#else
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#else
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uint32_t addr = CONFIG_V11_STATUS_REG;
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uint32_t addr = CONFIG_V11_STATUS_REG;
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#endif
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#endif
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uint32_t value =
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uint32_t regval = bus_r(addr);
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(bus_r(addr) & CONFIG_V11_FLTR_CLL_MSK) >> CONFIG_V11_FLTR_CLL_OFST;
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#ifndef VIRTUAL
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// flip all contents of register //TODO FIRMWARE FIX
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regval ^= BIT32_MASK;
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#endif
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uint32_t retval = (regval & CONFIG_V11_FLTR_CLL_MSK) >> CONFIG_V11_FLTR_CLL_OFST;
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// count number of bits = which icell
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// count number of bits = which icell
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return (__builtin_popcount(value));
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return (__builtin_popcount(retval));
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}
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}
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void setFilterCell(int iCell) {
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void setFilterCell(int iCell) {
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@ -2321,7 +2336,12 @@ int getFixCurrentSource() {
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int getNormalCurrentSource() {
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int getNormalCurrentSource() {
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if (getChipVersion() == 11) {
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if (getChipVersion() == 11) {
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int low = ((bus_r(CONFIG_V11_STATUS_REG) &
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//TODO FIRMWARE FIX TOGGLING
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int regval = bus_r(CONFIG_V11_STATUS_REG);
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#ifndef VIRTUAL
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regval ^= BIT32_MASK;
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#endif
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int low = ((regval &
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CONFIG_V11_STATUS_CRRNT_SRC_LOW_MSK) >>
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CONFIG_V11_STATUS_CRRNT_SRC_LOW_MSK) >>
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CONFIG_V11_STATUS_CRRNT_SRC_LOW_OFST);
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CONFIG_V11_STATUS_CRRNT_SRC_LOW_OFST);
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return (low == 0 ? 1 : 0);
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return (low == 0 ? 1 : 0);
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@ -73,7 +73,7 @@ enum DACINDEX {
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#define SPECIAL_DEFAULT_DYNAMIC_GAIN_VALS \
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#define SPECIAL_DEFAULT_DYNAMIC_GAIN_VALS \
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{ 1450, 480, 420 }
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{ 1450, 480, 420 }
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#define SPECIAL_DEFAULT_DYNAMICHG0_GAIN_VALS \
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#define SPECIAL_DEFAULT_DYNAMICHG0_GAIN_VALS \
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{ 1450, 480, 420 }
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{ 1550, 450, 620 }
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enum NETWORKINDEX { TXN_FRAME, FLOWCTRL_10G };
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enum NETWORKINDEX { TXN_FRAME, FLOWCTRL_10G };
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enum CLKINDEX { RUN_CLK, ADC_CLK, DBIT_CLK, NUM_CLOCKS };
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enum CLKINDEX { RUN_CLK, ADC_CLK, DBIT_CLK, NUM_CLOCKS };
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@ -154,7 +154,7 @@ enum CLKINDEX { RUN_CLK, ADC_CLK, DBIT_CLK, NUM_CLOCKS };
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#define ADC_PHASE_HALF_SPEED_CHIP11 (160)
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#define ADC_PHASE_HALF_SPEED_CHIP11 (160)
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#define ADC_PHASE_QUARTER_SPEED_CHIP11 (160)
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#define ADC_PHASE_QUARTER_SPEED_CHIP11 (160)
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#define DBIT_PHASE_FULL_SPEED_CHIP11 (75)
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#define DBIT_PHASE_FULL_SPEED_CHIP11 (80)
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#define DBIT_PHASE_HALF_SPEED_CHIP11 (135)
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#define DBIT_PHASE_HALF_SPEED_CHIP11 (135)
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#define DBIT_PHASE_QUARTER_SPEED_CHIP11 (135)
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#define DBIT_PHASE_QUARTER_SPEED_CHIP11 (135)
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@ -177,9 +177,9 @@ enum CLKINDEX { RUN_CLK, ADC_CLK, DBIT_CLK, NUM_CLOCKS };
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#define ADC_PHASE_HALF_SPEED_CHIP10 (160)
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#define ADC_PHASE_HALF_SPEED_CHIP10 (160)
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#define ADC_PHASE_QUARTER_SPEED_CHIP10 (160)
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#define ADC_PHASE_QUARTER_SPEED_CHIP10 (160)
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#define DBIT_PHASE_FULL_SPEED_CHIP10 (100)
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#define DBIT_PHASE_FULL_SPEED_CHIP10 (125)
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#define DBIT_PHASE_HALF_SPEED_CHIP10 (150)
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#define DBIT_PHASE_HALF_SPEED_CHIP10 (175)
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#define DBIT_PHASE_QUARTER_SPEED_CHIP10 (150)
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#define DBIT_PHASE_QUARTER_SPEED_CHIP10 (175)
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#define ADC_OFST_FULL_SPEED_VAL_CHIP10 (0x10)
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#define ADC_OFST_FULL_SPEED_VAL_CHIP10 (0x10)
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#define ADC_OFST_HALF_SPEED_VAL_CHIP10 (0x08)
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#define ADC_OFST_HALF_SPEED_VAL_CHIP10 (0x08)
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@ -9,7 +9,7 @@
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#define APICTB 0x211019
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#define APICTB 0x211019
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#define APIGOTTHARD 0x211019
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#define APIGOTTHARD 0x211019
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#define APIGOTTHARD2 0x211019
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#define APIGOTTHARD2 0x211019
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#define APIJUNGFRAU 0x211019
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#define APIMYTHEN3 0x211019
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#define APIMYTHEN3 0x211019
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#define APIMOENCH 0x211019
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#define APIMOENCH 0x211019
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#define APIEIGER 0x211019
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#define APIEIGER 0x211019
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#define APIJUNGFRAU 0x211020
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