updated calibration settings for jungfrau, default special dac values for high gain 0, temporary fix for firmwarebug (config_V11_status has to be flipped to be read)

This commit is contained in:
maliakal_d 2021-10-20 17:20:09 +02:00
parent ae736cd0e5
commit 9dc217aaa3
4 changed files with 32 additions and 12 deletions

View File

@ -842,7 +842,14 @@ int selectStoragecellStart(int pos) {
offset = CONFIG_V11_STATUS_STRG_CLL_OFST;
}
#endif
int retval = ((bus_r(addr) & mask) >> offset);
uint32_t regval = bus_r(addr);
#ifndef VIRTUAL
// flip all contents of register //TODO FIRMWARE FIX
if (getChipVersion() == 11) {
regval ^= BIT32_MASK;
}
#endif
uint32_t retval = ((regval & mask) >> offset);
if (getChipVersion() == 11) {
// get which bit
int max = getMaxStoragecellStart();
@ -2164,9 +2171,13 @@ int getFilterResistor() {
uint32_t addr = CONFIG_V11_REG;
#else
uint32_t addr = CONFIG_V11_STATUS_REG;
#endif
uint32_t regval = bus_r(addr);
#ifndef VIRTUAL
regval ^= BIT32_MASK;
#endif
// 0 for lower value, 1 for higher value
if (bus_r(addr) & CONFIG_V11_STATUS_FLTR_RSSTR_SMLR_MSK) {
if (regval & CONFIG_V11_STATUS_FLTR_RSSTR_SMLR_MSK) {
return 0;
}
return 1;
@ -2197,10 +2208,14 @@ int getFilterCell() {
#else
uint32_t addr = CONFIG_V11_STATUS_REG;
#endif
uint32_t value =
(bus_r(addr) & CONFIG_V11_FLTR_CLL_MSK) >> CONFIG_V11_FLTR_CLL_OFST;
uint32_t regval = bus_r(addr);
#ifndef VIRTUAL
// flip all contents of register //TODO FIRMWARE FIX
regval ^= BIT32_MASK;
#endif
uint32_t retval = (regval & CONFIG_V11_FLTR_CLL_MSK) >> CONFIG_V11_FLTR_CLL_OFST;
// count number of bits = which icell
return (__builtin_popcount(value));
return (__builtin_popcount(retval));
}
void setFilterCell(int iCell) {
@ -2321,7 +2336,12 @@ int getFixCurrentSource() {
int getNormalCurrentSource() {
if (getChipVersion() == 11) {
int low = ((bus_r(CONFIG_V11_STATUS_REG) &
//TODO FIRMWARE FIX TOGGLING
int regval = bus_r(CONFIG_V11_STATUS_REG);
#ifndef VIRTUAL
regval ^= BIT32_MASK;
#endif
int low = ((regval &
CONFIG_V11_STATUS_CRRNT_SRC_LOW_MSK) >>
CONFIG_V11_STATUS_CRRNT_SRC_LOW_OFST);
return (low == 0 ? 1 : 0);

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@ -73,7 +73,7 @@ enum DACINDEX {
#define SPECIAL_DEFAULT_DYNAMIC_GAIN_VALS \
{ 1450, 480, 420 }
#define SPECIAL_DEFAULT_DYNAMICHG0_GAIN_VALS \
{ 1450, 480, 420 }
{ 1550, 450, 620 }
enum NETWORKINDEX { TXN_FRAME, FLOWCTRL_10G };
enum CLKINDEX { RUN_CLK, ADC_CLK, DBIT_CLK, NUM_CLOCKS };
@ -154,7 +154,7 @@ enum CLKINDEX { RUN_CLK, ADC_CLK, DBIT_CLK, NUM_CLOCKS };
#define ADC_PHASE_HALF_SPEED_CHIP11 (160)
#define ADC_PHASE_QUARTER_SPEED_CHIP11 (160)
#define DBIT_PHASE_FULL_SPEED_CHIP11 (75)
#define DBIT_PHASE_FULL_SPEED_CHIP11 (80)
#define DBIT_PHASE_HALF_SPEED_CHIP11 (135)
#define DBIT_PHASE_QUARTER_SPEED_CHIP11 (135)
@ -177,9 +177,9 @@ enum CLKINDEX { RUN_CLK, ADC_CLK, DBIT_CLK, NUM_CLOCKS };
#define ADC_PHASE_HALF_SPEED_CHIP10 (160)
#define ADC_PHASE_QUARTER_SPEED_CHIP10 (160)
#define DBIT_PHASE_FULL_SPEED_CHIP10 (100)
#define DBIT_PHASE_HALF_SPEED_CHIP10 (150)
#define DBIT_PHASE_QUARTER_SPEED_CHIP10 (150)
#define DBIT_PHASE_FULL_SPEED_CHIP10 (125)
#define DBIT_PHASE_HALF_SPEED_CHIP10 (175)
#define DBIT_PHASE_QUARTER_SPEED_CHIP10 (175)
#define ADC_OFST_FULL_SPEED_VAL_CHIP10 (0x10)
#define ADC_OFST_HALF_SPEED_VAL_CHIP10 (0x08)

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@ -9,7 +9,7 @@
#define APICTB 0x211019
#define APIGOTTHARD 0x211019
#define APIGOTTHARD2 0x211019
#define APIJUNGFRAU 0x211019
#define APIMYTHEN3 0x211019
#define APIMOENCH 0x211019
#define APIEIGER 0x211019
#define APIJUNGFRAU 0x211020