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Merge branch '3.0-rc' into developer

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Dhanya Maliakal 2017-08-17 14:34:24 +02:00
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<h1><a class="anchor" id="ctb">Chiptest board </a></h1><p>Commands specific for the new chiptest board as pattern generator</p>
<ul>
<li><b>adcinvert [mask]</b> Sets/gets ADC inversion mask (8 digits hex format)</li>
</ul>
<ul>
<li><b>adcdisable [mask]</b> Sets/gets ADC disable mask (8 digits hex format)</li>
</ul>
<ul>
<li><b>pattern fn</b> loads binary pattern file fn</li>
</ul>
<ul>
<li><b>patword addr [word]</b> sets/gets 64 bit word at address addr of pattern memory. Both address and word in hex format. Advanced!</li>
</ul>
<ul>
<li><b>patioctrl [word]</b> sets/gets 64 bit mask defining input (0) and output (1) signals. hex format.</li>
</ul>
<ul>
<li><b>patclkctrl [word]</b> sets/gets 64 bit mask defining if output signal is a clock and runs. hex format. Unused at the moment.</li>
</ul>
<ul>
<li><b>patlimits [addr1 addr2]</b> sets/gets the start and stop limits of the pattern to be executed. hex format. Advanced!</li>
</ul>
<ul>
<li><b>patloop0 [addr1 addr2]</b> sets/gets the start and stop limits of the level 0 loop. hex format. Advanced!</li>
</ul>
<ul>
<li><b>patnloop0 [n]</b> sets/gets the number of cyclesof the level 0 loop (int).</li>
</ul>
<ul>
<li><b>patwait0 [addr]</b> sets/gets the address of the level 0 wait point. hex format. Advanced!</li>
</ul>
<ul>
<li><b>patwaittime0 [n]</b> sets/gets the duration of the witing of the 0 waiting point in clock cycles (int).</li>
</ul>
<ul>
<li><b>patloop1 [addr1 addr2]</b> sets/gets the start and stop limits of the level 1 loop. hex format. Advanced!</li>
</ul>
<ul>
<li><b>patnloop1 [n]</b> sets/gets the number of cyclesof the level 1 loop (int).</li>
</ul>
<ul>
<li><b>patwait1 [addr]</b> sets/gets the address of the level 1 wait point. hex format. Advanced!</li>
</ul>
<ul>
<li><b>patwaittime1 [n]</b> sets/gets the duration of the witing of the 1 waiting point in clock cycles (int).</li>
</ul>
<ul>
<li><b>patloop2 [addr1 addr2]</b> sets/gets the start and stop limits of the level 2 loop. hex format. Advanced!</li>
</ul>
<ul>
<li><b>patnloop2 [n]</b> sets/gets the number of cyclesof the level 2 loop (int).</li>
</ul>
<ul>
<li><b>patwait2 [addr]</b> sets/gets the address of the level 2 wait point. hex format. Advanced!</li>
</ul>
<ul>
<li><b>patwaittime2 [n]</b> sets/gets the duration of the waiting of the 2 waiting point in clock cycles (int).</li>
</ul>
<ul>
<li><b>dut_clk [i]</b> sets/gets the signal to be used as a clock for the digital data coming from the device under test. Advanced! </li>
</ul>
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manual/slsDetectorClientDocs/latex/ctb.tex Normal file
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Commands specific for the new chiptest board as pattern generator
\begin{DoxyItemize}
\item {\bfseries adcinvert \mbox{[}mask\mbox{]}} Sets/gets ADC inversion mask (8 digits hex format)
\end{DoxyItemize}
\begin{DoxyItemize}
\item {\bfseries adcdisable \mbox{[}mask\mbox{]}} Sets/gets ADC disable mask (8 digits hex format)
\end{DoxyItemize}
\begin{DoxyItemize}
\item {\bfseries pattern fn} loads binary pattern file fn
\end{DoxyItemize}
\begin{DoxyItemize}
\item {\bfseries patword addr \mbox{[}word\mbox{]}} sets/gets 64 bit word at address addr of pattern memory. Both address and word in hex format. Advanced!
\end{DoxyItemize}
\begin{DoxyItemize}
\item {\bfseries patioctrl \mbox{[}word\mbox{]}} sets/gets 64 bit mask defining input (0) and output (1) signals. hex format.
\end{DoxyItemize}
\begin{DoxyItemize}
\item {\bfseries patclkctrl \mbox{[}word\mbox{]}} sets/gets 64 bit mask defining if output signal is a clock and runs. hex format. Unused at the moment.
\end{DoxyItemize}
\begin{DoxyItemize}
\item {\bfseries patlimits \mbox{[}addr1 addr2\mbox{]}} sets/gets the start and stop limits of the pattern to be executed. hex format. Advanced!
\end{DoxyItemize}
\begin{DoxyItemize}
\item {\bfseries patloop0 \mbox{[}addr1 addr2\mbox{]}} sets/gets the start and stop limits of the level 0 loop. hex format. Advanced!
\end{DoxyItemize}
\begin{DoxyItemize}
\item {\bfseries patnloop0 \mbox{[}n\mbox{]}} sets/gets the number of cyclesof the level 0 loop (int).
\end{DoxyItemize}
\begin{DoxyItemize}
\item {\bfseries patwait0 \mbox{[}addr\mbox{]}} sets/gets the address of the level 0 wait point. hex format. Advanced!
\end{DoxyItemize}
\begin{DoxyItemize}
\item {\bfseries patwaittime0 \mbox{[}n\mbox{]}} sets/gets the duration of the witing of the 0 waiting point in clock cycles (int).
\end{DoxyItemize}
\begin{DoxyItemize}
\item {\bfseries patloop1 \mbox{[}addr1 addr2\mbox{]}} sets/gets the start and stop limits of the level 1 loop. hex format. Advanced!
\end{DoxyItemize}
\begin{DoxyItemize}
\item {\bfseries patnloop1 \mbox{[}n\mbox{]}} sets/gets the number of cyclesof the level 1 loop (int).
\end{DoxyItemize}
\begin{DoxyItemize}
\item {\bfseries patwait1 \mbox{[}addr\mbox{]}} sets/gets the address of the level 1 wait point. hex format. Advanced!
\end{DoxyItemize}
\begin{DoxyItemize}
\item {\bfseries patwaittime1 \mbox{[}n\mbox{]}} sets/gets the duration of the witing of the 1 waiting point in clock cycles (int).
\end{DoxyItemize}
\begin{DoxyItemize}
\item {\bfseries patloop2 \mbox{[}addr1 addr2\mbox{]}} sets/gets the start and stop limits of the level 2 loop. hex format. Advanced!
\end{DoxyItemize}
\begin{DoxyItemize}
\item {\bfseries patnloop2 \mbox{[}n\mbox{]}} sets/gets the number of cyclesof the level 2 loop (int).
\end{DoxyItemize}
\begin{DoxyItemize}
\item {\bfseries patwait2 \mbox{[}addr\mbox{]}} sets/gets the address of the level 2 wait point. hex format. Advanced!
\end{DoxyItemize}
\begin{DoxyItemize}
\item {\bfseries patwaittime2 \mbox{[}n\mbox{]}} sets/gets the duration of the waiting of the 2 waiting point in clock cycles (int).
\end{DoxyItemize}
\begin{DoxyItemize}
\item {\bfseries dut\_\-clk \mbox{[}i\mbox{]}} sets/gets the signal to be used as a clock for the digital data coming from the device under test. Advanced!
\end{DoxyItemize}