detectors/slsDetectorPackage
25
0
Fork 0
mirror of https://github.com/slsdetectorgroup/slsDetectorPackage.git synced 2025-06-23 10:07:59 +02:00
Code Issues Actions Packages Releases Activity

gotthard server done editing

Browse Source
This commit is contained in:
maliakal_d
2018-11-08 17:15:48 +01:00
parent a99584a0da
commit 91dd176a0f
31 changed files with 2716 additions and 5159 deletions
Download Patch File Download Diff File Expand all files Collapse all files

42
slsDetectorServers/gotthardDetectorServer/Makefile
View File

@ -1,19 +1,18 @@
CROSS = bfin-uclinux-
CC = $(CROSS)gcc
CROSS = bfin-uclinux-
CC = $(CROSS)gcc
CFLAGS += -Wall -DGOTTHARDD -DDEBUG # -DVERBOSE #-DVERYVERBOSE #-DVIRTUAL
CFLAGS += -Wall -DGOTTHARDD -DSTOP_SERVER # -DVERBOSE
LDLIBS += -lm -lstdc++
PROGS= gotthardDetectorServer
INSTDIR= /tftpboot
INSTMODE= 0777
PROGS = gotthardDetectorServer
DESTDIR ?= bin
INSTMODE = 0777
SRCS = communication_funcs.c slsDetectorServer.c slsDetectorServer_funcs.c slsDetectorFunctionList.c
OBJS = $(SRCS:%.c=%.o)
BINS = testlib_sharedlibc
SRCS = server.c firmware_funcs.c server_funcs.c communication_funcs.c
OBJS = $(SRCS:%.c=%.o)
all: clean versioning $(PROGS)
all: clean versioning $(PROGS)
boot: $(OBJS)
@ -21,21 +20,14 @@ versioning:
@echo `tput setaf 6; ./updateGitVersion.sh; tput sgr0;`
$(PROGS): $(OBJS)
echo $(OBJS)
$(CC) $(CFLAGS) -o $@ $^ $(LDLIBS_$@) $(LDFLAGS_$@)
rm gotthardDetectorServer.gdb
install: $(PROGS)
$(INSTALL) -d $(INSTDIR)
$(INSTALL) -m $(INSTMODE) $(PROGS) $(INSTDIR)
romfs:
$(ROMFSINST) /bin/$(PROGS)
# echo $(OBJS)
mkdir -p $(DESTDIR)
$(CC) -o $@ $^ $(CFLAGS) $(LDLIBS)
mv $(PROGS) $(DESTDIR)
rm *.gdb
clean:
rm -rf $(PROGS) *.o *.gdb
rm -rf $(DESTDIR)/$(PROGS) *.o *.gdb

43
slsDetectorServers/gotthardDetectorServer/Makefile.virtual
View File

@ -1,30 +1,27 @@
CC = gcc
CFLAGS += -Wall -DGOTTHARDD -DVIRTUAL -DSTOP_SERVER #-DVERBOSEI #-DVERBOSE
LDLIBS += -lm -lstdc++ -pthread
DESTDIR ?= ./
PROGS = gotthardDetectorServer_virtual
DESTDIR ?= bin
INSTMODE = 0777
CC = gcc
CFLAGS += -Wall -DGOTTHARDD -DVIRTUAL
PROGS= $(DESTDIR)/gotthardDetectorServer_virtual
SRCS = server.c server_funcs.c communication_funcs.c firmware_funcs.c
OBJS = $(SRCS:%.c=%.o)
gotthardVirtualServer = $(PROGS)
all: clean $(PROGS)
SRC_CLNT = communication_funcs.c slsDetectorServer.c slsDetectorServer_funcs.c slsDetectorFunctionList.c
OBJS = $(SRC_CLNT:.c=.o)
all: clean versioning $(PROGS)
boot: $(OBJS)
versioning:
@echo `tput setaf 6; ./updateGitVersion.sh; tput sgr0;`
$(PROGS): $(OBJS)
$(CC) $(CFLAGS) -o $@ $^ $(LDLIBS_$@) $(LDFLAGS_$@)
# echo $(OBJS)
mkdir -p $(DESTDIR)
$(CC) -o $@ $^ $(CFLAGS) $(LDLIBS)
mv $(PROGS) $(DESTDIR)
clean:
rm -rf $(PROGS) *.o *.gdb
rm -rf $(DESTDIR)/$(PROGS) *.o

328
slsDetectorServers/gotthardDetectorServer/RegisterDefs.h Executable file
View File

@ -0,0 +1,328 @@
#pragma once
/* Definitions for FPGA*/
#define MEM_MAP_SHIFT 11
/** Gain register */
#define GAIN_REG (0x10 << MEM_MAP_SHIFT)
#define GAIN_CONFGAIN_OFST (0)
#define GAIN_CONFGAIN_MSK (0x000000FF << GAIN_CONFGAIN_OFST)
#define GAIN_CONFGAIN_HGH_GAIN_VAL ((0x0 << GAIN_CONFGAIN_OFST) & GAIN_CONFGAIN_MSK)
#define GAIN_CONFGAIN_DYNMC_GAIN_VAL ((0x8 << GAIN_CONFGAIN_OFST) & GAIN_CONFGAIN_MSK)
#define GAIN_CONFGAIN_LW_GAIN_VAL ((0x6 << GAIN_CONFGAIN_OFST) & GAIN_CONFGAIN_MSK)
#define GAIN_CONFGAIN_MDM_GAIN_VAL ((0x2 << GAIN_CONFGAIN_OFST) & GAIN_CONFGAIN_MSK)
#define GAIN_CONFGAIN_VRY_HGH_GAIN_VAL ((0x1 << GAIN_CONFGAIN_OFST) & GAIN_CONFGAIN_MSK)
/** Multi Purpose register */
#define MULTI_PURPOSE_REG (0x14 << MEM_MAP_SHIFT)
#define PHS_STP_OFST (0)
#define PHS_STP_MSK (0x00000001 << PHS_STP_OFST)
#define RST_CNTR_OFST (2)
#define RST_CNTR_MSK (0x00000001 << RST_CNTR_OFST)
#define SW1_OFST (5)
#define SW1_MSK (0x00000001 << SW1_OFST)
#define WRT_BCK_OFST (6)
#define WRT_BCK_MSK (0x00000001 << WRT_BCK_OFST)
#define RST_OFST (7)
#define RST_MSK (0x00000001 << RST_OFST)
#define PLL_CLK_SL_OFST (8)
#define PLL_CLK_SL_MSK (0x00000007 << PLL_CLK_SL_OFST)
#define PLL_CLK_SL_MSTR_VAL ((0x1 << PLL_CLK_SL_OFST) & PLL_CLK_SL_MSK)
#define PLL_CLK_SL_MSTR_ADC_VAL ((0x2 << PLL_CLK_SL_OFST) & PLL_CLK_SL_MSK)
#define PLL_CLK_SL_SLV_VAL ((0x3 << PLL_CLK_SL_OFST) & PLL_CLK_SL_MSK)
#define PLL_CLK_SL_SLV_ADC_VAL ((0x4 << PLL_CLK_SL_OFST) & PLL_CLK_SL_MSK)
#define ENT_RSTN_OFST (11)
#define ENT_RSTN_MSK (0x00000001 << ENT_RSTN_OFST)
#define INT_RSTN_OFST (12)
#define INT_RSTN_MSK (0x00000001 << INT_RSTN_OFST)
#define DGTL_TST_OFST (14)
#define DGTL_TST_MSK (0x00000001 << DGTL_TST_OFST)
#define CHNG_AT_PWR_ON_OFST (15) // Not used in SW
#define CHNG_AT_PWR_ON_MSK (0x00000001 << CHNG_AT_PWR_ON_OFST) // Not used in SW
#define RST_TO_SW1_DLY_OFST (16)
#define RST_TO_SW1_DLY_MSK (0x0000000F << RST_TO_SW1_DLY_OFST)
#define STRT_ACQ_DLY_OFST (20)
#define STRT_ACQ_DLY_MSK (0x0000000F << STRT_ACQ_DLY_OFST)
/** DAQ register */
#define DAQ_REG (0x15 << MEM_MAP_SHIFT)
#define DAQ_TKN_TMNG_OFST (0)
#define DAQ_TKN_TMNG_MSK (0x0000FFFF << DAQ_TKN_TMNG_OFST)
#define DAQ_TKN_TMNG_BRD_RVSN_1_VAL ((0x1f16 << DAQ_TKN_TMNG_OFST) & DAQ_TKN_TMNG_MSK)
#define DAQ_TKN_TMNG_BRD_RVSN_2_VAL ((0x1f0f << DAQ_TKN_TMNG_OFST) & DAQ_TKN_TMNG_MSK)
#define DAQ_PCKT_LNGTH_OFST (16)
#define DAQ_PCKT_LNGTH_MSK (0x0000FFFF << DAQ_PCKT_LNGTH_OFST)
#define DAQ_PCKT_LNGTH_NO_ROI_VAL ((0x0013f << DAQ_PCKT_LNGTH_OFST) & DAQ_PCKT_LNGTH_MSK)
#define DAQ_PCKT_LNGTH_ROI_VAL ((0x0007f << DAQ_PCKT_LNGTH_OFST) & DAQ_PCKT_LNGTH_MSK)
/** DAC Control register */
#define DAC_CNTRL_REG (0x17 << MEM_MAP_SHIFT)
#define DAC_CNTRL_CS_OFST (0)
#define DAC_CNTRL_CS_MSK (0x00000001 << DAC_CNTRL_CS_OFST)
#define DAC_CNTRL_CLK_OFST (1)
#define DAC_CNTRL_CLK_MSK (0x00000001 << DAC_CNTRL_CLK_OFST)
#define DAQ_CNTRL_DGTL_OFST (2)
#define DAQ_CNTRL_DGTL_MSK (0x00000001 << DAQ_CNTRL_DGTL_OFST)
/** ADC SPI register */
#define ADC_SPI_REG (0x18 << MEM_MAP_SHIFT)
#define ADC_SERIAL_CLK_OUT_OFST (0)
#define ADC_SERIAL_CLK_OUT_MSK (0x00000001 << ADC_SERIAL_CLK_OUT_OFST)
#define ADC_SERIAL_DATA_OUT_OFST (1)
#define ADC_SERIAL_DATA_OUT_MSK (0x00000001 << ADC_SERIAL_DATA_OUT_OFST)
#define ADC_SERIAL_CS_OUT_OFST (2)
#define ADC_SERIAL_CS_OUT_MSK (0x0000000F << ADC_SERIAL_CS_OUT_OFST)
/** ADC Sync register */
#define ADC_SYNC_REG (0x19 << MEM_MAP_SHIFT)
#define ADC_SYNC_ENET_STRT_DLY_OFST (0)
#define ADC_SYNC_ENET_STRT_DLY_MSK (0x0000000F << ADC_SYNC_ENET_STRT_DLY_OFST)
#define ADC_SYNC_ENET_STRT_DLY_VAL ((0x4 << ADC_SYNC_ENET_STRT_DLY_OFST) & ADC_SYNC_ENET_STRT_DLY_MSK)
#define ADC_SYNC_TKN1_HGH_DLY_OFST (4)
#define ADC_SYNC_TKN1_HGH_DLY_MSK (0x0000000F << ADC_SYNC_TKN1_HGH_DLY_OFST)
#define ADC_SYNC_TKN1_HGH_DLY_VAL ((0x1 << ADC_SYNC_TKN1_HGH_DLY_OFST) & ADC_SYNC_TKN1_HGH_DLY_MSK)
#define ADC_SYNC_TKN2_HGH_DLY_OFST (8)
#define ADC_SYNC_TKN2_HGH_DLY_MSK (0x0000000F << ADC_SYNC_TKN2_HGH_DLY_OFST)
#define ADC_SYNC_TKN2_HGH_DLY_VAL ((0x2 << ADC_SYNC_TKN2_HGH_DLY_OFST) & ADC_SYNC_TKN2_HGH_DLY_MSK)
#define ADC_SYNC_TKN1_LOW_DLY_OFST (12)
#define ADC_SYNC_TKN1_LOW_DLY_MSK (0x0000000F << ADC_SYNC_TKN1_LOW_DLY_OFST)
#define ADC_SYNC_TKN1_LOW_DLY_VAL ((0x2 << ADC_SYNC_TKN1_LOW_DLY_OFST) & ADC_SYNC_TKN1_LOW_DLY_MSK)
#define ADC_SYNC_TKN2_LOW_DLY_OFST (16)
#define ADC_SYNC_TKN2_LOW_DLY_MSK (0x0000000F << ADC_SYNC_TKN2_LOW_DLY_OFST)
#define ADC_SYNC_TKN2_LOW_DLY_VAL ((0x3 << ADC_SYNC_TKN2_LOW_DLY_OFST) & ADC_SYNC_TKN2_LOW_DLY_MSK)
//0x32214
#define ADC_SYNC_TKN_VAL (ADC_SYNC_ENET_STRT_DLY_VAL | ADC_SYNC_TKN1_HGH_DLY_VAL | ADC_SYNC_TKN2_HGH_DLY_VAL | ADC_SYNC_TKN1_LOW_DLY_VAL | ADC_SYNC_TKN2_LOW_DLY_VAL)
#define ADC_SYNC_CLEAN_FIFOS_OFST (20)
#define ADC_SYNC_CLEAN_FIFOS_MSK (0x00000001 << ADC_SYNC_CLEAN_FIFOS_OFST)// FIXME: tried with 1, works? else put 0x011 as mask
#define ADC_SYNC_ENET_DELAY_OFST (24)
#define ADC_SYNC_ENET_DELAY_MSK (0x000000FF << ADC_SYNC_ENET_DELAY_OFST)
#define ADC_SYNC_ENET_DELAY_NO_ROI_VAL ((0x88 << ADC_SYNC_ENET_DELAY_OFST) & ADC_SYNC_ENET_DELAY_MSK)
#define ADC_SYNC_ENET_DELAY_ROI_VAL ((0x1b << ADC_SYNC_ENET_DELAY_OFST) & ADC_SYNC_ENET_DELAY_MSK)
//FIXME: try with just 0x8 and 0x1.. it is anded with 0000 in firmware anyway
/** Temperatre SPI In register */
#define TEMP_SPI_IN_REG (0x1b << MEM_MAP_SHIFT)
#define TEMP_SPI_IN_T1_CLK_OFST (0)
#define TEMP_SPI_IN_T1_CLK_MSK (0x00000001 << TEMP_SPI_IN_T1_CLK_OFST)
#define TEMP_SPI_IN_T1_CS_OFST (1)
#define TEMP_SPI_IN_T1_CS_MSK (0x00000001 << TEMP_SPI_IN_T1_CS_OFST)
#define TEMP_SPI_IN_T2_CLK_OFST (2)
#define TEMP_SPI_IN_T2_CLK_MSK (0x00000001 << TEMP_SPI_IN_T2_CLK_OFST)
#define TEMP_SPI_IN_T2_CS_OFST (3)
#define TEMP_SPI_IN_T2_CS_MSK (0x00000001 << TEMP_SPI_IN_T2_CS_OFST)
/** Temperatre SPI Out register */
#define TEMP_SPI_OUT_REG (0x1c << MEM_MAP_SHIFT)
#define TEMP_SPI_OUT_T1_DT_OFST (0)
#define TEMP_SPI_OUT_T1_DT_MSK (0x00000001 << TEMP_SPI_OUT_T1_DT_OFST)
#define TEMP_SPI_OUT_T2_DT_OFST (1)
#define TEMP_SPI_OUT_T2_DT_MSK (0x00000001 << TEMP_SPI_OUT_T2_DT_OFST)
/** TSE Configure register */
#define TSE_CONF_REG (0x1d << MEM_MAP_SHIFT)
/** SPI Configure register */
#define ENET_CONF_REG (0x1e << MEM_MAP_SHIFT)
/** High Voltage register */
#define HV_REG (0x20 << MEM_MAP_SHIFT)
#define HV_ENBL_OFST (0)
#define HV_ENBL_MSK (0x00000001 << HV_ENBL_OFST)
#define HV_SEL_OFST (1)
#define HV_SEL_MSK (0x00000007 << HV_SEL_OFST)
#define HV_SEL_90_VAL ((0x0 << HV_SEL_OFST) & HV_SEL_MSK)
#define HV_SEL_110_VAL ((0x1 << HV_SEL_OFST) & HV_SEL_MSK)
#define HV_SEL_120_VAL ((0x2 << HV_SEL_OFST) & HV_SEL_MSK)
#define HV_SEL_150_VAL ((0x3 << HV_SEL_OFST) & HV_SEL_MSK)
#define HV_SEL_180_VAL ((0x4 << HV_SEL_OFST) & HV_SEL_MSK)
#define HV_SEL_200_VAL ((0x5 << HV_SEL_OFST) & HV_SEL_MSK)
/** Dummy register */
#define DUMMY_REG (0x21 << MEM_MAP_SHIFT)
/** Firmware Version register */
#define FPGA_VERSION_REG (0x22 << MEM_MAP_SHIFT)
#define FPGA_VERSION_OFST (0)
#define FPGA_VERSION_MSK (0x00FFFFFF << FPGA_VERSION_OFST) // to get in format yymmdd
/* Fix Pattern register */
#define FIX_PATT_REG (0x23 << MEM_MAP_SHIFT)
#define FIXED_PATT_VAL (0xACDC1980)
/** Config register */
#define Config_REG (0x26 << MEM_MAP_SHIFT)
#define CONFIG_SLAVE_OFST (0) // Not used in FW & SW
#define CONFIG_SLAVE_MSK (0x00000001 << CONFIG_SLAVE_OFST)
#define CONFIG_MASTER_OFST (1) // Not used in FW & SW
#define CONFIG_MASTER_MSK (0x00000001 << CONFIG_MASTER_OFST)
#define CONFIG_TM_GT_ENBL_OFST (2) // Not used in FW & SW
#define CONFIG_TM_GT_ENBL_MSK (0x00000001 << CONFIG_TM_GT_ENBL_OFST)
#define CONFIG_CPU_RDT_OFST (12)
#define CONFIG_CPU_RDT_MSK (0x00000001 << CONFIG_CPU_RDT_OFST)
#define CONFIG_CNTNS_RDT_OFST (23) // Not used in FW & SW
#define CONFIG_CNTNS_RDT_MSK (0x00000001 << CONFIG_CNTNS_RDT_OFST)
#define CONFIG_ACCMLT_CNTS_OFST (24) // Not used in FW & SW
#define CONFIG_ACCMLT_CNTS_MSK (0x00000001 << CONFIG_ACCMLT_CNTS_OFST)
/** 16 bit Control register */
#define CONTROL_REG (0x24 << MEM_MAP_SHIFT)
#define CONTROL_STRT_ACQ_OFST (0)
#define CONTROL_STRT_ACQ_MSK (0x00000001 << CONTROL_STRT_ACQ_OFST)
#define CONTROL_STP_ACQ_OFST (1)
#define CONTROL_STP_ACQ_MSK (0x00000001 << CONTROL_STP_ACQ_OFST)
#define CONTROL_STRT_FF_TST_OFST (2) // Not used in FW & SW
#define CONTROL_STRT_FF_TST_MSK (0x00000001 << CONTROL_STRT_FF_TST_OFST)
#define CONTROL_STP_FF_TST_OFST (3) // Not used in FW & SW
#define CONTROL_STP_FF_TST_MSK (0x00000001 << CONTROL_STP_FF_TST_OFST)
#define CONTROL_STRT_RDT_OFST (4)
#define CONTROL_STRT_RDT_MSK (0x00000001 << CONTROL_STRT_RDT_OFST)
#define CONTROL_STP_RDT_OFST (5)
#define CONTROL_STP_RDT_MSK (0x00000001 << CONTROL_STP_RDT_OFST)
#define CONTROL_STRT_EXPSR_OFST (6)
#define CONTROL_STRT_EXPSR_MSK (0x00000001 << CONTROL_STRT_EXPSR_OFST)
#define CONTROL_STP_EXPSR_OFST (7)
#define CONTROL_STP_EXPSR_MSK (0x00000001 << CONTROL_STP_EXPSR_OFST)
#define CONTROL_STRT_TRN_OFST (8)
#define CONTROL_STRT_TRN_MSK (0x00000001 << CONTROL_STRT_TRN_OFST)
#define CONTROL_STP_TRN_OFST (9)
#define CONTROL_STP_TRN_MSK (0x00000001 << CONTROL_STP_TRN_OFST)
#define CONTROL_SYNC_RST_OFST (10)
#define CONTROL_SYNC_RST_MSK (0x00000001 << CONTROL_SYNC_RST_OFST)
/** Status register */
#define STATUS_REG (0x25 << MEM_MAP_SHIFT)
#define STATUS_RN_BSY_OFST (0)
#define STATUS_RN_BSY_MSK (0x00000001 << STATUS_RN_BSY_OFST)
#define STATUS_RDT_BSY_OFST (1)
#define STATUS_RDT_BSY_MSK (0x00000001 << STATUS_RDT_BSY_OFST)
#define STATUS_WTNG_FR_TRGGR_OFST (3)
#define STATUS_WTNG_FR_TRGGR_MSK (0x00000001 << STATUS_WTNG_FR_TRGGR_OFST)
#define STATUS_DLY_BFR_OFST (4)
#define STATUS_DLY_BFR_MSK (0x00000001 << STATUS_DLY_BFR_OFST)
#define STATUS_DLY_AFTR_OFST (5)
#define STATUS_DLY_AFTR_MSK (0x00000001 << STATUS_DLY_AFTR_OFST)
#define STATUS_EXPSNG_OFST (6)
#define STATUS_EXPSNG_MSK (0x00000001 << STATUS_EXPSNG_OFST)
#define STATUS_CNT_ENBL_OFST (7)
#define STATUS_CNT_ENBL_MSK (0x00000001 << STATUS_CNT_ENBL_OFST)
#define STATUS_RD_STT_OFST (8)
#define STATUS_RD_STT_MSK (0x00000007 << STATUS_RD_STT_OFST)
#define STATUS_RN_STT_OFST (12)
#define STATUS_RN_STT_MSK (0x00000007 << STATUS_RN_STT_OFST)
#define STATUS_SM_FF_FLL_OFST (15)
#define STATUS_SM_FF_FLL_MSK (0x00000001 << STATUS_SM_FF_FLL_OFST)
#define STATUS_ALL_FF_EMPTY_OFST (11)
#define STATUS_ALL_FF_EMPTY_MSK (0x00000001 << STATUS_ALL_FF_EMPTY_OFST)
#define STATUS_RN_MSHN_BSY_OFST (17)
#define STATUS_RN_MSHN_BSY_MSK (0x00000001 << STATUS_RN_MSHN_BSY_OFST)
#define STATUS_RD_MSHN_BSY_OFST (18)
#define STATUS_RD_MSHN_BSY_MSK (0x00000001 << STATUS_RD_MSHN_BSY_OFST)
#define STATUS_RN_FNSHD_OFST (20)
#define STATUS_RN_FNSHD_MSK (0x00000001 << STATUS_RN_FNSHD_OFST)
#define STATUS_IDLE_MSK (0x0000FFFF << 0)
/** External Signal register */
#define EXT_SIGNAL_REG (0x27 << MEM_MAP_SHIFT)
#define EXT_SIGNAL_OFST (0)
#define EXT_SIGNAL_MSK (0x00000007 << EXT_SIGNAL_OFST)
#define EXT_SIGNAL_OFF_VAL ((0x0 << EXT_SIGNAL_OFST) & EXT_SIGNAL_MSK)
#define EXT_SIGNAL_TRGGR_IN_RSNG_VAL ((0x3 << EXT_SIGNAL_OFST) & EXT_SIGNAL_MSK)
#define EXT_SIGNAL_TRGGR_IN_FLLNG_VAL ((0x4 << EXT_SIGNAL_OFST) & EXT_SIGNAL_MSK)
/*
#define FPGA_SVN_REG 0x29<<11
#define LOOK_AT_ME_REG 0x28<<11
*/
/** Chip of Interest register */
#define CHIP_OF_INTRST_REG (0x2a << MEM_MAP_SHIFT)
#define CHIP_OF_INTRST_ADC_SEL_OFST (0)
#define CHIP_OF_INTRST_ADC_SEL_MSK (0x0000001F << CHIP_OF_INTRST_ADC_SEL_OFST)
#define CHIP_OF_INTRST_NUM_CHNNLS_OFST (16)
#define CHIP_OF_INTRST_NUM_CHNNLS_MSK (0x0000FFFF << CHIP_OF_INTRST_NUM_CHNNLS_OFST)
/** Board Version register */
#define BOARD_REVISION_REG (0x2c << MEM_MAP_SHIFT)
#define BOARD_REVISION_OFST (0)
#define BOARD_REVISION_MSK (0x0000FFFF << BOARD_REVISION_OFST)
#define DETECTOR_TYPE_OFST (16)
#define DETECTOR_TYPE_MSK (0x0000000F << DETECTOR_TYPE_OFST)
//#define DETECTOR_TYPE_GOTTHARD_VAL (??)
#define DETECTOR_TYPE_MOENCH_VAL (2)
/* 16 bit Fifo Data register */
//#define FIFO_DATA_REG (0x50 << MEM_MAP_SHIFT) // Not used in FW and SW (16bit)
/*
#define MOD_DACS1_REG 0x65<<11
#define MOD_DACS2_REG 0x66<<11
#define MOD_DACS3_REG 0x67<<11
*/
/* Set Delay 64 bit register */
#define SET_DELAY_LSB_REG (0x68 << MEM_MAP_SHIFT)
#define SET_DELAY_MSB_REG (0x69 << MEM_MAP_SHIFT)
/* Get Delay 64 bit register */
#define GET_DELAY_LSB_REG (0x6a << MEM_MAP_SHIFT)
#define GET_DELAY_MSB_REG (0x6b << MEM_MAP_SHIFT)
/* Set Cycles 64 bit register */
#define SET_TRAINS_LSB_REG (0x6c << MEM_MAP_SHIFT)
#define SET_TRAINS_MSB_REG (0x6d << MEM_MAP_SHIFT)
/* Get Cycles 64 bit register */
#define GET_TRAINS_LSB_REG (0x6e << MEM_MAP_SHIFT)
#define GET_TRAINS_MSB_REG (0x6f << MEM_MAP_SHIFT)
/* Set Frames 64 bit register */
#define SET_FRAMES_LSB_REG (0x70 << MEM_MAP_SHIFT)
#define SET_FRAMES_MSB_REG (0x71 << MEM_MAP_SHIFT)
/* Get Frames 64 bit register */
#define GET_FRAMES_LSB_REG (0x72 << MEM_MAP_SHIFT)
#define GET_FRAMES_MSB_REG (0x73 << MEM_MAP_SHIFT)
/* Set Period 64 bit register */
#define SET_PERIOD_LSB_REG (0x74 << MEM_MAP_SHIFT)
#define SET_PERIOD_MSB_REG (0x75 << MEM_MAP_SHIFT)
/* Get Period 64 bit register */
#define GET_PERIOD_LSB_REG (0x76 << MEM_MAP_SHIFT)
#define GET_PERIOD_MSB_REG (0x77 << MEM_MAP_SHIFT)
/* Set Exptime 64 bit register */
#define SET_EXPTIME_LSB_REG (0x78 << MEM_MAP_SHIFT)
#define SET_EXPTIME_MSB_REG (0x79 << MEM_MAP_SHIFT)
/* Get Exptime 64 bit register */
#define GET_EXPTIME_LSB_REG (0x7a << MEM_MAP_SHIFT)
#define GET_EXPTIME_MSB_REG (0x7b << MEM_MAP_SHIFT)
/* Set Gates 64 bit register */
//#define SET_GATES_LSB_REG (0x7c << MEM_MAP_SHIFT) // Not used in SW and FW
//#define SET_GATES_MSB_REG (0x7d << MEM_MAP_SHIFT) // Not used in SW and FW
/* Dark Image starting address */
#define DARK_IMAGE_REG (0x81 << MEM_MAP_SHIFT)
/* Gain Image starting address */
#define GAIN_IMAGE_REG (0x82 << MEM_MAP_SHIFT)
/* Counter Block Memory starting address */
#define COUNTER_MEMORY_REG (0x85 << MEM_MAP_SHIFT)

1
slsDetectorServers/gotthardDetectorServer/blackfin.h Symbolic link
View File

@ -0,0 +1 @@
../slsDetectorServer/blackfin.h

2098
slsDetectorServers/gotthardDetectorServer/firmware_funcs.c
View File

File diff suppressed because it is too large Load Diff

120
slsDetectorServers/gotthardDetectorServer/firmware_funcs.h
View File

@ -1,120 +0,0 @@
#ifndef FIRMWARE_FUNCS_H
#define FIRMWARE_FUNCS_H
#include "sls_detector_defs.h"
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <sys/mman.h>
#include <fcntl.h>
#include <stdarg.h>
#include <unistd.h>
#include <sys/types.h>
#include <sys/stat.h>
int mapCSP0(void);
u_int16_t bus_r16(u_int32_t offset);
u_int16_t bus_w16(u_int32_t offset, u_int16_t data);//aldos function
u_int32_t bus_w(u_int32_t offset, u_int32_t data);
u_int32_t bus_r(u_int32_t offset);
int initDetector();
int setDefaultDacs();
void setMasterSlaveConfiguration();
int configureADC();
int setPhaseShiftOnce();
int setPhaseShift(int numphaseshift);
int cleanFifo();
int setDAQRegister();
u_int32_t putout(char *s);
int setConfigurationRegister(int d);
int sendviaUDP(int d);
int setDACRegister(int idac, int val);
u_int32_t setExtSignal(enum externalSignalFlag mode);
int getExtSignal();
u_int32_t setFPGASignal(enum externalSignalFlag mode);
int getFPGASignal();
int setTiming(int t);
u_int64_t getDetectorNumber();
u_int32_t getFirmwareVersion();
u_int32_t getFirmwareSVNVersion();
u_int32_t testFpga(void);
int testBus(void);
int initHighVoltage(int val);
int getTemperature(int tempSensor);
int setSettings(int i);
int initConfGain(int isettings,int val);
ROI* setROI(int n, ROI arg[], int *retvalsize, int *ret);
int setADC(int adc);
int configureMAC(int ipad, long long int macad, long long int detectormacadd, int detipad, int ival, int udpport);
int getAdcConfigured();
int64_t set64BitReg(int64_t value, int aLSB, int aMSB);
int64_t get64BitReg(int aLSB, int aMSB);
int64_t setFrames(int64_t value);
int64_t getFrames();
int64_t setExposureTime(int64_t value);
int64_t getExposureTime();
int64_t setGates(int64_t value);
int64_t getGates();
int64_t setPeriod(int64_t value);
int64_t getPeriod();
int64_t setDelay(int64_t value);
int64_t getDelay();
int64_t setTrains(int64_t value);
int64_t getTrains();
int64_t getActualTime();
int64_t getMeasurementTime();
u_int32_t fifoReadStatus();
u_int32_t fifo_full(void);
u_int32_t runBusy(void);
u_int32_t runState(void);
int startStateMachine();
int stopStateMachine();
int startReadOut();
void waitForAcquisitionFinish();
int getStatus();
int loadImage(int index, short int ImageVals[]);
int readCounterBlock(int startACQ, short int CounterVals[]);
int resetCounterBlock(int startACQ);
int copyModule(sls_detector_module *destMod, sls_detector_module *srcMod);
int setDAC(int ind,int val,int mV, int retval[]);
int getDAC(int ind);
int setModule(sls_detector_module);
void getModule(sls_detector_module*);
void initDACs(int* v);
void initDAC(int dac_addr, int value);
void clearDACSregister();
void nextDAC();
void program_one_dac(int addr, int value);
#endif

BIN
slsDetectorServers/gotthardDetectorServer/gotthardDetectorServer_refactor
View File

Binary file not shown.

BIN
slsDetectorServers/gotthardDetectorServer/gotthardDetectorServer_virtual
View File

Binary file not shown.

1
slsDetectorServers/gotthardDetectorServer/logger.h Symbolic link
View File

@ -0,0 +1 @@
../slsDetectorServer/logger.h

103
slsDetectorServers/gotthardDetectorServer/server.c
View File

@ -1,103 +0,0 @@
/* A simple server in the internet domain using TCP
The port number is passed as an argument */
#include "sls_detector_defs.h"
#include "communication_funcs.h"
#include "server_funcs.h"
#include <stdlib.h>
#include <string.h>
extern int sockfd;
extern int phase_shift;
void error(char *msg)
{
perror(msg);
}
int main(int argc, char *argv[])
{
int portno, b;
char cmd[100];
int retval=OK;
int sd, fd;
int iarg;
for(iarg=1; iarg<argc; iarg++){
if(!strcasecmp(argv[iarg],"-phaseshift")){
if ( sscanf(argv[iarg+1],"%d",&phase_shift)==0) {
printf("could not decode phase shift\n");
return 1;
}
argc=1;
}
}
if (argc==1) {
portno = DEFAULT_PORTNO;
sprintf(cmd,"%s %d &",argv[0],DEFAULT_PORTNO+1);
printf("\n\nControl Server\nOpening control server on port %d\n",portno );
system(cmd);
b=1;
} else {
portno = DEFAULT_PORTNO+1;
if ( sscanf(argv[1],"%d",&portno) ==0) {
printf("could not open stop server: unknown port\n");
return 1;
}
b=0;
printf("\n\nStop Server\nOpening stop server on port %d\n",portno);
}
init_detector(b);
sd=bindSocket(portno);
sockfd=sd;
if (getServerError(sd)) {
printf("server error!\n");
return -1;
}
/* assign function table */
function_table();
#ifdef VERBOSE
printf("function table assigned \n");
#endif
/* waits for connection */
while(retval!=GOODBYE) {
#ifdef VERBOSE
printf("\n");
#endif
#ifdef VERY_VERBOSE
printf("Waiting for client call\n");
#endif
fd=acceptConnection(sockfd);
#ifdef VERY_VERBOSE
printf("Conenction accepted\n");
#endif
retval=decode_function(fd);
#ifdef VERY_VERBOSE
printf("function executed\n");
#endif
closeConnection(fd);
#ifdef VERY_VERBOSE
printf("connection closed\n");
#endif
}
exitServer(sockfd);
printf("Goodbye!\n");
return 0;
}

69
slsDetectorServers/gotthardDetectorServer/server_defs.h
View File

@ -1,69 +0,0 @@
#ifndef SERVER_DEFS_H
#define SERVER_DEFS_H
#include "sls_detector_defs.h"
#include <stdint.h>
// Hardware definitions
#define NCHAN 128
#define NCHIP 10
#define NDAC 8
#define NADC 5
#define NCHANS NCHAN*NCHIP
#define NDACS NDAC
#define NCHIPS_PER_ADC 2
#define DYNAMIC_RANGE 16
#define DATA_BYTES (NCHIP*NCHAN*2)
// for 25 um
#define CONFIG_FILE "config.txt"
#define ADCSYNC_VAL 0x32214
#define TOKEN_RESTART_DELAY 0x88000000
#define TOKEN_RESTART_DELAY_ROI 0x1b000000
#define TOKEN_TIMING_REV1 0x1f16
#define TOKEN_TIMING_REV2 0x1f0f
#define DEFAULT_PHASE_SHIFT 120
#define DEFAULT_IP_PACKETSIZE 0x0522
#define DEFAULT_UDP_PACKETSIZE 0x050E
#define ADC1_IP_PACKETSIZE (256*2+14+20)
#define ADC1_UDP_PACKETSIZE (256*2+4+8+2)
#define CLK_FREQ 32.007729
#define DAC_DR 1024
#define CONF_GAIN { \
0, /*standard gain*/ \
0, /*fast gain*/ \
0, /*high gain*/ \
8, /*dynamic gain*/ \
6, /*low gain*/ \
2, /*medium gain*/ \
1 /*very high gain*/ \
};
//dynamic gain confgain yet to be figured out-probably 8 or 16
// DAC definitions
enum dacsVal{VREF_DS, VCASCN_PB, VCASCP_PB, VOUT_CM, VCASC_OUT, VIN_CM, VREF_COMP, IB_TESTC,HIGH_VOLTAGE, CONFGAIN};
#define DEFAULT_DAC_VALS { \
660, /* VREF_DS */ \
650, /* VCASCN_PB */ \
1480, /* VCASCP_PB */ \
1520, /* VOUT_CM */ \
1320, /* VCASC_OUT */ \
1350, /* VIN_CM */ \
350, /* VREF_COMP */ \
2001 /* IB_TESTC */ \
};
//Register Definitions for temp,hv,dac gain
enum adcVals{TEMP_FPGA, TEMP_ADC};
#endif

2185
slsDetectorServers/gotthardDetectorServer/server_funcs.c
View File

File diff suppressed because it is too large Load Diff

70
slsDetectorServers/gotthardDetectorServer/server_funcs.h
View File

@ -1,70 +0,0 @@
#ifndef SERVER_FUNCS_H
#define SERVER_FUNCS_H
#include "sls_detector_defs.h"
#include <stdio.h>
/*
#include <sys/types.h>
#include <sys/socket.h>
#include <netinet/in.h>
*/
#include "communication_funcs.h"
#define GOODBYE -200
int sockfd;
int function_table();
int decode_function(int);
int init_detector(int);
int M_nofunc(int);
// General purpose functions
int exec_command(int);
int get_detector_type(int);
int set_external_signal_flag(int);
int set_external_communication_mode(int);
int get_id(int);
int digital_test(int);
int set_dac(int);
int get_adc(int);
int write_register(int);
int read_register(int);
int set_module(int);
int get_module(int);
int set_settings(int);
int start_acquisition(int);
int stop_acquisition(int);
int start_readout(int);
int get_run_status(int);
int start_and_read_all(int);
int read_all(int);
int set_timer(int);
int get_time_left(int);
int set_dynamic_range(int);
int set_readout_flags(int);
int set_roi(int);
int set_speed(int);
int exit_server(int);
int lock_server(int);
int get_last_client_ip(int);
int set_port(int);
int send_update(int);
int update_client(int);
int configure_mac(int);
int load_image(int);
int read_counter_block(int);
int reset_counter_block(int);
int write_adc_register(int);
int check_version(int);
#endif

1810
slsDetectorServers/gotthardDetectorServer/slsDetectorFunctionList.c Normal file
View File

File diff suppressed because it is too large Load Diff

1
slsDetectorServers/gotthardDetectorServer/slsDetectorFunctionList.h Symbolic link
View File

@ -0,0 +1 @@
../slsDetectorServer/slsDetectorFunctionList.h

1
slsDetectorServers/gotthardDetectorServer/slsDetectorServer.c Symbolic link
View File

@ -0,0 +1 @@
../slsDetectorServer/slsDetectorServer.c

121
slsDetectorServers/gotthardDetectorServer/slsDetectorServer_defs.h Normal file
View File

@ -0,0 +1,121 @@
#pragma once
#include "sls_detector_defs.h" //default dynamicgain in settings
#define GOODBYE (-200)
/* Enums */
enum ADCINDEX {TEMP_FPGA, TEMP_ADC};
enum DACINDEX {VREF_DS, VCASCN_PB, VCASCP_PB, VOUT_CM, VCASC_OUT, VIN_CM, VREF_COMP, IB_TESTC};
#define DEFAULT_DAC_VALS { \
660, /* VREF_DS */ \
650, /* VCASCN_PB */ \
1480, /* VCASCP_PB */ \
1520, /* VOUT_CM */ \
1320, /* VCASC_OUT */ \
1350, /* VIN_CM */ \
350, /* VREF_COMP */ \
2001 /* IB_TESTC */ \
};
/* for 25 um */
#define CONFIG_FILE "config.txt"
/* Hardware Definitions */
#define NCHAN (128)
#define NCHIP (10)
#define NDAC (8)
#define NCHIPS_PER_ADC (2)
#define DYNAMIC_RANGE (16)
#define NUM_BITS_PER_PIXEL (DYNAMIC_RANGE / 8)
#define DATA_BYTES (NCHIP * NCHAN * NUM_BITS_PER_PIXEL)
#define CLK_FREQ (32.007729) /* MHz */
/** Firmware Definitions */
#define IP_PACKET_SIZE_NO_ROI (NCHIP * (NCHAN / 2) * 2 + 14 + 20) // 2 packets, so divide by 2
#define IP_PACKET_SIZE_ROI (NCHIPS_PER_ADC * NCHAN * 2 + 14 + 20)
#define UDP_PACKETSIZE_NO_ROI (NCHIP * (NCHAN / 2) * 2 + 4 + 8 + 2) // 2 packets, so divide by 2
#define UDP_PACKETSIZE_ROI (NCHIPS_PER_ADC * NCHAN * 2 + 4 + 8 + 2)
/** Default Parameters */
#define DEFAULT_NUM_FRAMES (1)
#define DEFAULT_NUM_CYCLES (1)
#define DEFAULT_EXPTIME (1 * 1000 * 1000) // 1 ms
#define DEFAULT_PERIOD (1 * 1000 * 1000 * 1000) // 1 s
#define DEFAULT_DELAY (0)
#define DEFAULT_SETTINGS (DYNAMICGAIN)
#define DEFAULT_TIMING_MODE (AUTO_TIMING)
#define DEFAULT_TRIGGER_MODE (TRIGGER_IN_RISING_EDGE)
#define DEFAULT_HIGH_VOLTAGE (0)
#define DEFAULT_PHASE_SHIFT (120)
#define DEFAULT_TX_UDP_PORT (0xE185)
/** ENEt conf structs */
typedef struct mac_header_struct{
u_int8_t mac_dest_mac2;
u_int8_t mac_dest_mac1;
u_int8_t mac_dummy1;
u_int8_t mac_dummy2;
u_int8_t mac_dest_mac6;
u_int8_t mac_dest_mac5;
u_int8_t mac_dest_mac4;
u_int8_t mac_dest_mac3;
u_int8_t mac_src_mac4;
u_int8_t mac_src_mac3;
u_int8_t mac_src_mac2;
u_int8_t mac_src_mac1;
u_int16_t mac_ether_type;
u_int8_t mac_src_mac6;
u_int8_t mac_src_mac5;
} mac_header;
typedef struct ip_header_struct {
u_int16_t ip_len;
u_int8_t ip_tos;
u_int8_t ip_ihl:4 ,ip_ver:4;
u_int16_t ip_offset:13,ip_flag:3;
u_int16_t ip_ident;
u_int16_t ip_chksum;
u_int8_t ip_protocol;
u_int8_t ip_ttl;
u_int32_t ip_sourceip;
u_int32_t ip_destip;
} ip_header;
typedef struct udp_header_struct{
u_int16_t udp_destport;
u_int16_t udp_srcport;
u_int16_t udp_chksum;
u_int16_t udp_len;
} udp_header;
typedef struct mac_conf_struct{
mac_header mac;
ip_header ip;
udp_header udp;
u_int32_t npack;
u_int32_t lpack;
u_int32_t npad;
u_int32_t cdone;
} mac_conf;
typedef struct tse_conf_struct{
u_int32_t rev; //0x0
u_int32_t scratch;
u_int32_t command_config;
u_int32_t mac_0; //0x3
u_int32_t mac_1;
u_int32_t frm_length;
u_int32_t pause_quant;
u_int32_t rx_section_empty; //0x7
u_int32_t rx_section_full;
u_int32_t tx_section_empty;
u_int32_t tx_section_full;
u_int32_t rx_almost_empty; //0xB
u_int32_t rx_almost_full;
u_int32_t tx_almost_empty;
u_int32_t tx_almost_full;
u_int32_t mdio_addr0; //0xF
u_int32_t mdio_addr1;
}tse_conf;

1
slsDetectorServers/gotthardDetectorServer/slsDetectorServer_funcs.c Symbolic link
View File

@ -0,0 +1 @@
../slsDetectorServer/slsDetectorServer_funcs.c

1
slsDetectorServers/gotthardDetectorServer/slsDetectorServer_funcs.h Symbolic link
View File

@ -0,0 +1 @@
../slsDetectorServer/slsDetectorServer_funcs.h

46
slsDetectorServers/gotthardDetectorServer/stop_server.c
View File

@ -1,46 +0,0 @@
/* A simple server in the internet domain using TCP
The port number is passed as an argument */
#include "sls_detector_defs.h"
#include "communication_funcs.h"
#include "firmware_funcs.h"
int sockfd;
int main(int argc, char *argv[])
{
int portno;
int retval=0;
portno = DEFAULT_PORTNO;
bindSocket(portno);
if (getServerError())
return -1;
/* waits for connection */
while(retval!=GOODBYE) {
#ifdef VERBOSE
printf("\n");
#endif
#ifdef VERY_VERBOSE
printf("Stop server: waiting for client call\n");
#endif
acceptConnection();
retval=stopStateMachine();
closeConnection();
}
exitServer();
printf("Goodbye!\n");
return 0;
}