detectors/slsDetectorPackage
25
0
Fork 0
mirror of https://github.com/slsdetectorgroup/slsDetectorPackage.git synced 2025-05-12 15:32:13 +02:00
Code Issues Actions Packages Releases Activity

update xilinx regs (#1123)

Browse Source 
Co-authored-by: Martin Mueller <martin.mueller@psi.ch>
This commit is contained in:
Martin Mueller 2025-03-04 10:38:14 +01:00 committed by GitHub
parent b4dc1dde6c
commit 905a509a17
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
3 changed files with 329 additions and 855 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1126
slsDetectorServers/xilinx_ctbDetectorServer/RegisterDefs.h
View File

File diff suppressed because it is too large Load Diff

20
slsDetectorServers/xilinx_ctbDetectorServer/chip_config_xilinx.txt
View File

@ -1,24 +1,24 @@
# Prepare MH02 configuration # Prepare MH02 configuration
reg 0x600 0x00000041 reg 0xB1B0 0x00000041
reg 0x604 0x01200004 reg 0xB1B4 0x01200004
# configure Matterhorn SPI # configure Matterhorn SPI
setbit 0x608 0 setbit 0xB1B8 0
# wait till config is done # wait till config is done
pollbit 0x608 3 0 pollbit 0xB1B8 3 0
# reset transceiver # reset transceiver
reg 0x658 0x0 reg 0xB820 0x0
reg 0x658 0x1 reg 0xB820 0x1
reg 0x658 0x0 reg 0xB820 0x0
# set MSB LSB inversions and polarity for transceiver # set MSB LSB inversions and polarity for transceiver
reg 0x658 0x61e0 reg 0xB820 0x61e0
# Enable MH02 PLL clock # Enable MH02 PLL clock
pattern enable_clock_pattern.pyat pattern enable_clock_pattern.pyat
# start the flow # start the flow
setbit 0x108 0 setbit 0xB004 0
clearbit 0x108 0 clearbit 0xB004 0
sleep 1 sleep 1

38
slsDetectorServers/xilinx_ctbDetectorServer/reset_chip_xilinx.txt
View File

@ -1,39 +1,39 @@
# turn off clock # turn off clock
setbit 0x600 16 setbit 0xB1B0 16
setbit 0x608 0 setbit 0xB1B8 0
sleep 1 sleep 1
# reset Matterhorn periphery # reset Matterhorn periphery
setbit 0x608 1 setbit 0xB1B8 1
sleep 1 sleep 1
# turn on clock # turn on clock
clearbit 0x600 16 clearbit 0xB1B0 16
setbit 0x608 0 setbit 0xB1B8 0
sleep 1 sleep 1
# reset rx transceiver datapath # reset rx transceiver datapath
setbit 0x658 4 setbit 0xB820 4
sleep 1 sleep 1
# reset 8b10b counters # reset 8b10b counters
setbit 0x658 9 setbit 0xB820 9
setbit 0x658 10 setbit 0xB820 10
setbit 0x658 11 setbit 0xB820 11
setbit 0x658 12 setbit 0xB820 12
sleep 1 sleep 1
clearbit 0x658 9 clearbit 0xB820 9
clearbit 0x658 10 clearbit 0xB820 10
# reset buffer fifos # reset buffer fifos
reg 0x5C8 0xFFFFFFFF reg 0x9024 0xFFFFFFFF
reg 0x5D0 0xFFFFFFFF reg 0x9028 0xFFFFFFFF
reg 0x5D8 0xFFFFFFFF reg 0x902C 0xFFFFFFFF
reg 0x5C8 0x0 reg 0x9024 0x0
reg 0x5D0 0x0 reg 0x9028 0x0
reg 0x5D8 0x0 reg 0x902C 0x0
setbit 0x500 18 setbit 0xA000 18
# load default pattern # load default pattern
pattern readout_pattern.pyat pattern readout_pattern.pyat