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mythen3: fix of external signals to not allow master output inversion, but can edge detect not configurable, and default dout pulse length

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This commit is contained in:
maliakal_d
2020-05-28 13:09:09 +02:00
parent 754536898a
commit 8aa7144252
6 changed files with 51 additions and 20 deletions
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26
slsDetectorServers/mythen3DetectorServer/RegisterDefs.h
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@ -186,12 +186,16 @@
/** DOUTIF1 Master Ouput Register */
#define DOUTIF1_REG (0x01 * REG_OFFSET + BASE_PIPELINE)
#define DOUTIF1_BYPASS_OFST (0)
#define DOUTIF1_BYPASS_MSK (0x0000000F << DOUTIF1_BYPASS_OFST)
#define DOUTIF1_TRIGGER_BYPASS_OFST (0)
#define DOUTIF1_TRIGGER_BYPASS_MSK (0x00000001 << DOUTIF1_TRIGGER_BYPASS_OFST)
#define DOUTIF1_BYPASS_GATE_OFST (1)
#define DOUTIF1_BYPASS_GATE_MSK (0x00000007 << DOUTIF1_BYPASS_GATE_OFST)
#define DOUTIF1_INVERSION_OFST (4)
#define DOUTIF1_INVERSION_MSK (0x0000000F << DOUTIF1_INVERSION_OFST)
#define DOUTIF1_RISING_OFST (8)
#define DOUTIF1_RISING_MSK (0x0000000F << DOUTIF1_RISING_OFST)
#define DOUTIF1_RISING_TRIGGER_OFST (8)
#define DOUTIF1_RISING_TRIGGER_MSK (0x00000001 << DOUTIF1_RISING_TRIGGER_OFST)
#define DOUTIF1_RISING_GATE_OFST (9)
#define DOUTIF1_RISING_GATE_MSK (0x00000007 << DOUTIF1_RISING_GATE_OFST)
#define DOUTIF1_FALLING_OFST (12)
#define DOUTIF1_FALLING_MSK (0x0000000F << DOUTIF1_FALLING_OFST)
@ -211,13 +215,13 @@
#define DOUTIF_RISING_LNGTH_REG (0x03 * REG_OFFSET + BASE_PIPELINE)
#define DOUTIF_RISING_LNGTH_PORT_1_OFST (0)
#define DOUTIF_RISING_LNGTH_PORT_1_MSK (0x0000000F << DOUTIF_RISING_LNGTH_PORT_1_OFST)
#define DOUTIF_RISING_LNGTH_PORT_2_OFST (0)
#define DOUTIF_RISING_LNGTH_PORT_2_MSK (0x0000000F << DOUTIF_RISING_LNGTH_PORT_2_OFST)
#define DOUTIF_RISING_LNGTH_PORT_3_OFST (0)
#define DOUTIF_RISING_LNGTH_PORT_3_MSK (0x0000000F << DOUTIF_RISING_LNGTH_PORT_3_OFST)
#define DOUTIF_RISING_LNGTH_PORT_4_OFST (0)
#define DOUTIF_RISING_LNGTH_PORT_4_MSK (0x0000000F << DOUTIF_RISING_LNGTH_PORT_4_OFST)
#define DOUTIF_RISING_LNGTH_PORT_1_MSK (0x000000FF << DOUTIF_RISING_LNGTH_PORT_1_OFST)
#define DOUTIF_RISING_LNGTH_PORT_2_OFST (8)
#define DOUTIF_RISING_LNGTH_PORT_2_MSK (0x000000FF << DOUTIF_RISING_LNGTH_PORT_2_OFST)
#define DOUTIF_RISING_LNGTH_PORT_3_OFST (16)
#define DOUTIF_RISING_LNGTH_PORT_3_MSK (0x000000FF << DOUTIF_RISING_LNGTH_PORT_3_OFST)
#define DOUTIF_RISING_LNGTH_PORT_4_OFST (24)
#define DOUTIF_RISING_LNGTH_PORT_4_MSK (0x000000FF << DOUTIF_RISING_LNGTH_PORT_4_OFST)
/* ASIC Exposure Control registers

20
slsDetectorServers/mythen3DetectorServer/slsDetectorFunctionList.c
View File

@ -1245,14 +1245,28 @@ enum timingMode getTiming() {
void setInitialExtSignals() {
LOG(logINFOBLUE, ("Setting Initial External Signals\n"));
// default, everything is 0
bus_w(DINF1_REG, 0);
bus_w(DOUTIF1_REG, 0);
bus_w(DINF2_REG, 0);
bus_w(DOUTIF_RISING_LNGTH_REG, 0);
// bypass everything
// (except master input can edge detect)
// (except master triggers can edge detect)
bus_w(DINF1_REG, DINF1_BYPASS_GATE_MSK);
bus_w(DOUTIF1_REG, DOUTIF1_BYPASS_MSK);
bus_w(DOUTIF1_REG, DOUTIF1_BYPASS_GATE_MSK);
bus_w(DINF2_REG, DINF2_BYPASS_MSK);
// master input can edge detect, so rising is 1
// master input/output can edge detect, so rising is 1
bus_w(DINF1_REG, bus_r(DINF1_REG) | DINF1_RISING_TRIGGER_MSK);
bus_w(DOUTIF1_REG, bus_r(DOUTIF1_REG) | DOUTIF1_RISING_TRIGGER_MSK);
// set default value for master output rising pulse length for port1
bus_w(DOUTIF_RISING_LNGTH_REG,
bus_r(DOUTIF_RISING_LNGTH_REG) & ~DOUTIF_RISING_LNGTH_PORT_1_MSK);
bus_w(DOUTIF_RISING_LNGTH_REG, bus_r(DOUTIF_RISING_LNGTH_REG) |
((DEFAULT_MSTR_OTPT_P1_NUM_PULSES
<< DOUTIF_RISING_LNGTH_PORT_1_OFST) &
DOUTIF_RISING_LNGTH_PORT_1_MSK));
}
void setExtSignal(int signalIndex, enum externalSignalFlag mode) {

1
slsDetectorServers/mythen3DetectorServer/slsDetectorServer_defs.h
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@ -41,6 +41,7 @@
#define DEFAULT_SYSTEM_C1 (10) //(125000000) // chip_clk, 125 MHz
#define DEFAULT_SYSTEM_C2 (10) //(125000000) // sync_clk, 125 MHz
#define DEFAULT_ASIC_LATCHING_NUM_PULSES (10)
#define DEFAULT_MSTR_OTPT_P1_NUM_PULSES (20)
/* Firmware Definitions */
#define IP_HEADER_SIZE (20)