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Dev/m3 readout speed (#985)

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* added readoutspeed command to m3 (fullspeed - 10, half speed - 20, quarter speed - 40), removed reaodut pll, moved up system pll clock indices, leaving pll index in common altera code, default speed is half speed, allow only system_c0 to be set, the others can be obtained, same for clkphase, maxclkphaseshift, clkfreq. added to readoutspeedlist commands, updated help and updated tests

* updated readoutspeedlist command
This commit is contained in:
maliakal_d
2024-09-30 17:22:24 +02:00
committed by GitHub
parent 5b832cb6aa
commit 8a7ed30676
12 changed files with 140 additions and 78 deletions
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3
slsDetectorServers/mythen3DetectorServer/RegisterDefs.h
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@ -7,9 +7,6 @@
/* Base addresses 0x1804 0000 ---------------------------------------------*/
/* Reconfiguration core for readout pll */
#define BASE_READOUT_PLL (0x0000) // 0x1804_0000 - 0x1804_07FF
/* Reconfiguration core for system pll */
#define BASE_SYSTEM_PLL (0x0800) // 0x1804_0800 - 0x1804_0FFF

BIN
slsDetectorServers/mythen3DetectorServer/bin/mythen3DetectorServer_developer
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73
slsDetectorServers/mythen3DetectorServer/slsDetectorFunctionList.c
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@ -451,8 +451,6 @@ void setupDetector() {
if (updateModuleId() == FAIL)
return;
clkDivider[READOUT_C0] = DEFAULT_READOUT_C0;
clkDivider[READOUT_C1] = DEFAULT_READOUT_C1;
clkDivider[SYSTEM_C0] = DEFAULT_SYSTEM_C0;
clkDivider[SYSTEM_C1] = DEFAULT_SYSTEM_C1;
clkDivider[SYSTEM_C2] = DEFAULT_SYSTEM_C2;
@ -472,16 +470,10 @@ void setupDetector() {
// pll defines
ALTERA_PLL_C10_SetDefines(
REG_OFFSET, BASE_READOUT_PLL, BASE_SYSTEM_PLL, PLL_RESET_REG,
PLL_RESET_READOUT_MSK, PLL_RESET_SYSTEM_MSK, SYSTEM_STATUS_REG,
SYSTEM_STATUS_RDO_PLL_LCKD_MSK, SYSTEM_STATUS_R_PLL_LCKD_MSK,
READOUT_PLL_VCO_FREQ_HZ, SYSTEM_PLL_VCO_FREQ_HZ);
ALTERA_PLL_C10_ResetPLL(READOUT_PLL);
REG_OFFSET, 0, BASE_SYSTEM_PLL, PLL_RESET_REG, 0, PLL_RESET_SYSTEM_MSK,
SYSTEM_STATUS_REG, SYSTEM_STATUS_RDO_PLL_LCKD_MSK,
SYSTEM_STATUS_R_PLL_LCKD_MSK, 0, SYSTEM_PLL_VCO_FREQ_HZ);
ALTERA_PLL_C10_ResetPLL(SYSTEM_PLL);
// change startup clock divider in software
// because firmware only sets max clock divider
setClockDividerWithTimeUpdateOption(READOUT_C0, DEFAULT_READOUT_C0_STARTUP,
0);
// hv
DAC6571_SetDefines(HV_HARD_MAX_VOLTAGE, HV_DRIVER_FILE_NAME);
@ -552,6 +544,7 @@ void setupDetector() {
}
setAllTrimbits(DEFAULT_TRIMBIT_VALUE);
setReadoutSpeed(DEFAULT_READOUT_SPEED);
}
int resetToDefaultDacs(int hardReset) {
@ -2246,9 +2239,7 @@ int setPhase(enum CLKINDEX ind, int val, int degrees) {
relativePhase *= -1;
direction = 0;
}
int pllIndex = (int)(ind >= SYSTEM_C0 ? SYSTEM_PLL : READOUT_PLL);
int clkIndex = (int)(ind >= SYSTEM_C0 ? ind - SYSTEM_C0 : ind);
ALTERA_PLL_C10_SetPhaseShift(pllIndex, clkIndex, relativePhase, direction);
ALTERA_PLL_C10_SetPhaseShift(SYSTEM_PLL, ind, relativePhase, direction);
clkPhase[ind] = valShift;
return OK;
@ -2318,8 +2309,7 @@ int getVCOFrequency(enum CLKINDEX ind) {
LOG(logERROR, ("Unknown clock index %d to get vco frequency\n", ind));
return -1;
}
int pllIndex = (int)(ind >= SYSTEM_C0 ? SYSTEM_PLL : READOUT_PLL);
return ALTERA_PLL_C10_GetVCOFrequency(pllIndex);
return ALTERA_PLL_C10_GetVCOFrequency(SYSTEM_PLL);
}
int getMaxClockDivider() { return ALTERA_PLL_C10_GetMaxClockDivider(); }
@ -2358,9 +2348,7 @@ int setClockDividerWithTimeUpdateOption(enum CLKINDEX ind, int val,
}
// Calculate and set output frequency
int pllIndex = (int)(ind >= SYSTEM_C0 ? SYSTEM_PLL : READOUT_PLL);
int clkIndex = (int)(ind >= SYSTEM_C0 ? ind - SYSTEM_C0 : ind);
ALTERA_PLL_C10_SetOuputClockDivider(pllIndex, clkIndex, val);
ALTERA_PLL_C10_SetOuputClockDivider(SYSTEM_PLL, ind, val);
// Update time settings that depend on system frequency
// timeUpdate = 0 for setChipRegister/setTrimbits etc
@ -2392,14 +2380,9 @@ int setClockDividerWithTimeUpdateOption(enum CLKINDEX ind, int val,
clkDivider[ind]));
// phase is reset by pll (when setting output frequency)
if (ind < SYSTEM_C0) {
clkPhase[READOUT_C0] = 0;
clkPhase[READOUT_C1] = 0;
} else {
clkPhase[SYSTEM_C0] = 0;
clkPhase[SYSTEM_C1] = 0;
clkPhase[SYSTEM_C2] = 0;
}
clkPhase[SYSTEM_C0] = 0;
clkPhase[SYSTEM_C1] = 0;
clkPhase[SYSTEM_C2] = 0;
// set the phase in degrees (reset by pll)
for (int i = 0; i < NUM_CLOCKS; ++i) {
@ -2422,6 +2405,42 @@ int getClockDivider(enum CLKINDEX ind) {
return clkDivider[ind];
}
int setReadoutSpeed(int val) {
enum speedLevel speed = FULL_SPEED;
switch (val) {
case FULL_SPEED:
LOG(logINFO, ("Setting Full Speed (100 MHz):\n"));
speed = FULL_SPEED_CLKDIV;
break;
case HALF_SPEED:
LOG(logINFO, ("Setting Half Speed (50 MHz):\n"));
speed = HALF_SPEED_CLKDIV;
break;
case QUARTER_SPEED:
LOG(logINFO, ("Setting Quarter Speed (25 MHz):\n"));
speed = QUARTER_SPEED_CLKDIV;
break;
default:
LOG(logERROR, ("Unknown readout speed %d\n", val));
return FAIL;
}
return setClockDivider(SYSTEM_C0, speed);
}
int getReadoutSpeed(int *retval) {
int clkdiv = getClockDivider(SYSTEM_C0);
if (clkdiv == FULL_SPEED_CLKDIV) {
*retval = FULL_SPEED;
} else if (clkdiv == HALF_SPEED_CLKDIV) {
*retval = HALF_SPEED;
} else if (clkdiv == QUARTER_SPEED_CLKDIV) {
*retval = QUARTER_SPEED;
} else {
return FAIL;
}
return OK;
}
int setBadChannels(int numChannels, int *channelList) {
LOG(logINFO, ("Setting %d bad channels\n", numChannels));
memset(badChannelMask, 0, NCHAN_PER_MODULE * sizeof(char));

35
slsDetectorServers/mythen3DetectorServer/slsDetectorServer_defs.h
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@ -57,15 +57,16 @@
#define DEFAULT_SETTINGS (STANDARD)
#define DEFAULT_TRIMBIT_VALUE (0)
#define DEFAULT_COUNTER_DISABLED_VTH_VAL (2800)
#define DEFAULT_READOUT_SPEED (HALF_SPEED)
#define DEFAULT_READOUT_C0 (10) //(100000000) // rdo_clk, 100 MHz
#define DEFAULT_READOUT_C1 (10) //(100000000) // rdo_smp_clk, 100 MHz
#define DEFAULT_SYSTEM_C0 (10) //(100000000) // run_clk, 100 MHz
#define DEFAULT_SYSTEM_C1 (6) //(166666666) // str_clk, 166 MHz const
#define DEFAULT_SYSTEM_C2 (5) //(200000000) // smp_clk, 200 MHz const
#define DEFAULT_TRIMMING_RUN_CLKDIV (40) // (25000000) // 25 MHz
#define DEFAULT_READOUT_C0_STARTUP (20) //(50000000) // rdo_clk, 50 MHz
#define FULL_SPEED_CLKDIV (10) //(100000000) 100 MHz
#define HALF_SPEED_CLKDIV (20) //( 50000000) 50 MHz
#define QUARTER_SPEED_CLKDIV (40) //( 25000000) 25 MHz
#define DEFAULT_ASIC_LATCHING_NUM_PULSES (10)
#define DEFAULT_MSTR_OTPT_P1_NUM_PULSES (20)
@ -73,12 +74,11 @@
#define DEFAULT_ADIF_ADD_OFST_VAL (0)
/* Firmware Definitions */
#define MAX_TIMESLOT_VAL (0xFFFFFF)
#define IP_HEADER_SIZE (20)
#define FIXED_PLL_FREQUENCY (020000000) // 20MHz
#define READOUT_PLL_VCO_FREQ_HZ (1000000000) // 1GHz
#define SYSTEM_PLL_VCO_FREQ_HZ (1000000000) // 1GHz
#define MAX_NUM_DESERIALIZERS (40)
#define MAX_TIMESLOT_VAL (0xFFFFFF)
#define IP_HEADER_SIZE (20)
#define FIXED_PLL_FREQUENCY (020000000) // 20MHz
#define SYSTEM_PLL_VCO_FREQ_HZ (1000000000) // 1GHz
#define MAX_NUM_DESERIALIZERS (40)
/** Other Definitions */
#define BIT16_MASK (0xFFFF)
@ -140,19 +140,12 @@ enum ADCINDEX { TEMP_FPGA };
#define SPECIAL_DEFAULT_HIGHGAIN_DAC_VALS \
{ 1300, 1100 }
enum CLKINDEX {
READOUT_C0,
READOUT_C1,
SYSTEM_C0,
SYSTEM_C1,
SYSTEM_C2,
NUM_CLOCKS
};
#define NUM_CLOCKS_TO_SET (3)
enum CLKINDEX { SYSTEM_C0, SYSTEM_C1, SYSTEM_C2, NUM_CLOCKS };
#define NUM_CLOCKS_TO_SET (1)
#define CLK_NAMES \
"READOUT_C0", "READOUT_C1", "SYSTEM_C0", "SYSTEM_C1", "SYSTEM_C2"
enum PLLINDEX { READOUT_PLL, SYSTEM_PLL };
#define CLK_NAMES "SYSTEM_C0", "SYSTEM_C1", "SYSTEM_C2"
#define SYSTEM_PLL (1)
/* Struct Definitions */
typedef struct udp_header_struct {