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Revert "updated RegisterDefs.h from firmware update"

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This reverts commit 64f1b2546e.
This commit is contained in:
maliakal_d
2025-02-03 09:34:59 +01:00
parent 64f1b2546e
commit 73059736bc
1 changed files with 120 additions and 145 deletions
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81
slsDetectorServers/xilinx_ctbDetectorServer/RegisterDefs.h
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@ -2,7 +2,6 @@
// Copyright (C) 2021 Contributors to the SLS Detector Package
#pragma once
#define CTRL_REG (0x0)
#define POWER_VIO_OFST (0)
@ -32,7 +31,7 @@
#define FPGADETTYPE_OFST (24)
#define FPGADETTYPE_MSK (0x000000ff << FPGADETTYPE_OFST)
#define FPGA_GIT_HEAD (0x14)
#define EMPTY14REG (0x14)
#define FIXEDPATTERNREG (0x18)
#define FIXEDPATTERNVAL (0xACDC2016)
@ -270,7 +269,8 @@
#define PATTERN_LOOP_0_ADDR_REG (0x230)
#define PATTERN_LOOP_0_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_0_ADDR_STRT_MSK (0x00001fff << PATTERN_LOOP_0_ADDR_STRT_OFST)
#define PATTERN_LOOP_0_ADDR_STRT_MSK \
(0x00001fff << PATTERN_LOOP_0_ADDR_STRT_OFST)
#define PATTERN_LOOP_0_ADDR_STP_OFST (16)
#define PATTERN_LOOP_0_ADDR_STP_MSK (0x00001fff << PATTERN_LOOP_0_ADDR_STP_OFST)
@ -294,7 +294,8 @@
#define PATTERN_LOOP_1_ADDR_REG (0x250)
#define PATTERN_LOOP_1_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_1_ADDR_STRT_MSK (0x00001fff << PATTERN_LOOP_1_ADDR_STRT_OFST)
#define PATTERN_LOOP_1_ADDR_STRT_MSK \
(0x00001fff << PATTERN_LOOP_1_ADDR_STRT_OFST)
#define PATTERN_LOOP_1_ADDR_STP_OFST (16)
#define PATTERN_LOOP_1_ADDR_STP_MSK (0x00001fff << PATTERN_LOOP_1_ADDR_STP_OFST)
@ -318,7 +319,8 @@
#define PATTERN_LOOP_2_ADDR_REG (0x270)
#define PATTERN_LOOP_2_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_2_ADDR_STRT_MSK (0x00001fff << PATTERN_LOOP_2_ADDR_STRT_OFST)
#define PATTERN_LOOP_2_ADDR_STRT_MSK \
(0x00001fff << PATTERN_LOOP_2_ADDR_STRT_OFST)
#define PATTERN_LOOP_2_ADDR_STP_OFST (16)
#define PATTERN_LOOP_2_ADDR_STP_MSK (0x00001fff << PATTERN_LOOP_2_ADDR_STP_OFST)
@ -342,7 +344,8 @@
#define PATTERN_LOOP_3_ADDR_REG (0x290)
#define PATTERN_LOOP_3_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_3_ADDR_STRT_MSK (0x00001fff << PATTERN_LOOP_3_ADDR_STRT_OFST)
#define PATTERN_LOOP_3_ADDR_STRT_MSK \
(0x00001fff << PATTERN_LOOP_3_ADDR_STRT_OFST)
#define PATTERN_LOOP_3_ADDR_STP_OFST (16)
#define PATTERN_LOOP_3_ADDR_STP_MSK (0x00001fff << PATTERN_LOOP_3_ADDR_STP_OFST)
@ -366,7 +369,8 @@
#define PATTERN_LOOP_4_ADDR_REG (0x310)
#define PATTERN_LOOP_4_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_4_ADDR_STRT_MSK (0x00001fff << PATTERN_LOOP_4_ADDR_STRT_OFST)
#define PATTERN_LOOP_4_ADDR_STRT_MSK \
(0x00001fff << PATTERN_LOOP_4_ADDR_STRT_OFST)
#define PATTERN_LOOP_4_ADDR_STP_OFST (16)
#define PATTERN_LOOP_4_ADDR_STP_MSK (0x00001fff << PATTERN_LOOP_4_ADDR_STP_OFST)
@ -390,7 +394,8 @@
#define PATTERN_LOOP_5_ADDR_REG (0x330)
#define PATTERN_LOOP_5_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_5_ADDR_STRT_MSK (0x00001fff << PATTERN_LOOP_5_ADDR_STRT_OFST)
#define PATTERN_LOOP_5_ADDR_STRT_MSK \
(0x00001fff << PATTERN_LOOP_5_ADDR_STRT_OFST)
#define PATTERN_LOOP_5_ADDR_STP_OFST (16)
#define PATTERN_LOOP_5_ADDR_STP_MSK (0x00001fff << PATTERN_LOOP_5_ADDR_STP_OFST)
@ -642,7 +647,8 @@
#define RO_MODE_X_OFST (15)
#define RO_MODE_X_MSK (0x00000001 << RO_MODE_X_OFST)
#define COUNT_FRAMES_FROM_UPDATE_OFST (16)
#define COUNT_FRAMES_FROM_UPDATE_MSK (0x00000001 << COUNT_FRAMES_FROM_UPDATE_OFST)
#define COUNT_FRAMES_FROM_UPDATE_MSK \
(0x00000001 << COUNT_FRAMES_FROM_UPDATE_OFST)
#define START_STREAMING_P_OFST (17)
#define START_STREAMING_P_MSK (0x00000001 << START_STREAMING_P_OFST)
@ -883,10 +889,7 @@
#define GTTPOWERGOOD_OFST (26)
#define GTTPOWERGOOD_MSK (0x0000000f << GTTPOWERGOOD_OFST)
#define TRANSCEIVERSTATUS2 (0x654)
#define RXLOCKED_OFST (0)
#define RXLOCKED_MSK (0x0000000f << RXLOCKED_OFST)
#define EMPTY654REG (0x654)
#define TRANSCEIVERCONTROL (0x658)
@ -902,58 +905,30 @@
#define RESETRXDATAPATHIN_MSK (0x00000001 << RESETRXDATAPATHIN_OFST)
#define RXPOLARITY_OFST (5)
#define RXPOLARITY_MSK (0x0000000f << RXPOLARITY_OFST)
#define RXERRORCNTRESET_OFST (9)
#define RXERRORCNTRESET_MSK (0x0000000f << RXERRORCNTRESET_OFST)
#define RXMSBLSBINVERT_OFST (13)
#define RXMSBLSBINVERT_MSK (0x0000000f << RXMSBLSBINVERT_OFST)
#define TRANSCEIVERERRCNT_REG0 (0x65C)
#define EMPTY65CREG (0x65C)
#define TRANSCEIVERERRCNT_REG1 (0x660)
#define EMPTY660REG (0x660)
#define TRANSCEIVERERRCNT_REG2 (0x664)
#define EMPTY664REG (0x664)
#define TRANSCEIVERERRCNT_REG3 (0x668)
#define EMPTY668REG (0x668)
#define TRANSCEIVERALIGNCNT_REG0 (0x66C)
#define EMPTY66CREG (0x66C)
#define RXALIGNCNTCH0_OFST (0)
#define RXALIGNCNTCH0_MSK (0x0000ffff << RXALIGNCNTCH0_OFST)
#define EMPTY670REG (0x670)
#define TRANSCEIVERALIGNCNT_REG1 (0x670)
#define EMPTY674REG (0x674)
#define RXALIGNCNTCH1_OFST (0)
#define RXALIGNCNTCH1_MSK (0x0000ffff << RXALIGNCNTCH1_OFST)
#define EMPTY678REG (0x678)
#define TRANSCEIVERALIGNCNT_REG2 (0x674)
#define EMPTY67CREG (0x67C)
#define RXALIGNCNTCH2_OFST (0)
#define RXALIGNCNTCH2_MSK (0x0000ffff << RXALIGNCNTCH2_OFST)
#define EMPTY680REG (0x680)
#define TRANSCEIVERALIGNCNT_REG3 (0x678)
#define EMPTY684REG (0x684)
#define RXALIGNCNTCH3_OFST (0)
#define RXALIGNCNTCH3_MSK (0x0000ffff << RXALIGNCNTCH3_OFST)
#define TRANSCEIVERLASTWORD_REG0 (0x67C)
#define RXDATACH0_OFST (0)
#define RXDATACH0_MSK (0x0000ffff << RXDATACH0_OFST)
#define TRANSCEIVERLASTWORD_REG1 (0x680)
#define RXDATACH1_OFST (0)
#define RXDATACH1_MSK (0x0000ffff << RXDATACH1_OFST)
#define TRANSCEIVERLASTWORD_REG2 (0x684)
#define RXDATACH2_OFST (0)
#define RXDATACH2_MSK (0x0000ffff << RXDATACH2_OFST)
#define TRANSCEIVERLASTWORD_REG3 (0x688)
#define RXDATACH3_OFST (0)
#define RXDATACH3_MSK (0x0000ffff << RXDATACH3_OFST)
#define EMPTY688REG (0x688)
#define EMPTY68CREG (0x68C)