mirror of
https://github.com/slsdetectorgroup/slsDetectorPackage.git
synced 2025-06-23 18:17:59 +02:00
Revert "updated RegisterDefs.h from firmware update"
This reverts commit 64f1b2546e.
This commit is contained in:
@ -2,11 +2,10 @@
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// Copyright (C) 2021 Contributors to the SLS Detector Package
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#pragma once
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#define CTRL_REG (0x0)
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#define POWER_VIO_OFST (0)
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#define POWER_VIO_MSK (0x00000001 << POWER_VIO_OFST)
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#define POWER_VIO_OFST (0)
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#define POWER_VIO_MSK (0x00000001 << POWER_VIO_OFST)
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#define POWER_VCC_A_OFST (1)
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#define POWER_VCC_A_MSK (0x00000001 << POWER_VCC_A_OFST)
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#define POWER_VCC_B_OFST (2)
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@ -29,10 +28,10 @@
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#define FPGACOMPDATE_OFST (0)
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#define FPGACOMPDATE_MSK (0x00ffffff << FPGACOMPDATE_OFST)
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#define FPGADETTYPE_OFST (24)
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#define FPGADETTYPE_MSK (0x000000ff << FPGADETTYPE_OFST)
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#define FPGADETTYPE_OFST (24)
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#define FPGADETTYPE_MSK (0x000000ff << FPGADETTYPE_OFST)
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#define FPGA_GIT_HEAD (0x14)
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#define EMPTY14REG (0x14)
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#define FIXEDPATTERNREG (0x18)
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#define FIXEDPATTERNVAL (0xACDC2016)
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@ -43,15 +42,15 @@
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#define APICOMPDATE_OFST (0)
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#define APICOMPDATE_MSK (0x00ffffff << APICOMPDATE_OFST)
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#define APIDETTYPE_OFST (24)
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#define APIDETTYPE_MSK (0x000000ff << APIDETTYPE_OFST)
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#define APIDETTYPE_OFST (24)
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#define APIDETTYPE_MSK (0x000000ff << APIDETTYPE_OFST)
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#define EMPTY24REG (0x24)
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#define PKTPACKETLENGTHREG (0x28)
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#define PACKETLENGTH1G_OFST (0)
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#define PACKETLENGTH1G_MSK (0x0000ffff << PACKETLENGTH1G_OFST)
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#define PACKETLENGTH1G_OFST (0)
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#define PACKETLENGTH1G_MSK (0x0000ffff << PACKETLENGTH1G_OFST)
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#define PACKETLENGTH10G_OFST (16)
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#define PACKETLENGTH10G_MSK (0x0000ffff << PACKETLENGTH10G_OFST)
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@ -59,8 +58,8 @@
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#define PKTNOPACKETSREG (0x30)
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#define NOPACKETS1G_OFST (0)
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#define NOPACKETS1G_MSK (0x0000003f << NOPACKETS1G_OFST)
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#define NOPACKETS1G_OFST (0)
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#define NOPACKETS1G_MSK (0x0000003f << NOPACKETS1G_OFST)
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#define NOPACKETS10G_OFST (16)
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#define NOPACKETS10G_MSK (0x0000003f << NOPACKETS10G_OFST)
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@ -68,12 +67,12 @@
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#define PKTCTRLREG (0x38)
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#define NOSERVERS_OFST (0)
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#define NOSERVERS_MSK (0x0000003f << NOSERVERS_OFST)
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#define NOSERVERS_OFST (0)
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#define NOSERVERS_MSK (0x0000003f << NOSERVERS_OFST)
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#define SERVERSTART_OFST (8)
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#define SERVERSTART_MSK (0x0000001f << SERVERSTART_OFST)
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#define ETHINTERF_OFST (16)
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#define ETHINTERF_MSK (0x00000001 << ETHINTERF_OFST)
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#define ETHINTERF_OFST (16)
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#define ETHINTERF_MSK (0x00000001 << ETHINTERF_OFST)
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#define EMPTY3CREG (0x3C)
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@ -135,25 +134,25 @@
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#define FLOW_STATUS_REG (0x100)
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#define RSM_BUSY_OFST (0)
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#define RSM_BUSY_MSK (0x00000001 << RSM_BUSY_OFST)
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#define RSM_BUSY_OFST (0)
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#define RSM_BUSY_MSK (0x00000001 << RSM_BUSY_OFST)
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#define RSM_TRG_WAIT_OFST (3)
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#define RSM_TRG_WAIT_MSK (0x00000001 << RSM_TRG_WAIT_OFST)
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#define CSM_BUSY_OFST (17)
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#define CSM_BUSY_MSK (0x00000001 << CSM_BUSY_OFST)
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#define CSM_BUSY_OFST (17)
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#define CSM_BUSY_MSK (0x00000001 << CSM_BUSY_OFST)
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#define EMPTY104REG (0x104)
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#define FLOW_CONTROL_REG (0x108)
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#define START_F_OFST (0)
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#define START_F_MSK (0x00000001 << START_F_OFST)
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#define STOP_F_OFST (1)
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#define STOP_F_MSK (0x00000001 << STOP_F_OFST)
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#define RST_F_OFST (2)
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#define RST_F_MSK (0x00000001 << RST_F_OFST)
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#define SW_TRIGGER_F_OFST (3)
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#define SW_TRIGGER_F_MSK (0x00000001 << SW_TRIGGER_F_OFST)
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#define START_F_OFST (0)
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#define START_F_MSK (0x00000001 << START_F_OFST)
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#define STOP_F_OFST (1)
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#define STOP_F_MSK (0x00000001 << STOP_F_OFST)
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#define RST_F_OFST (2)
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#define RST_F_MSK (0x00000001 << RST_F_OFST)
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#define SW_TRIGGER_F_OFST (3)
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#define SW_TRIGGER_F_MSK (0x00000001 << SW_TRIGGER_F_OFST)
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#define TRIGGER_ENABLE_OFST (4)
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#define TRIGGER_ENABLE_MSK (0x00000001 << TRIGGER_ENABLE_OFST)
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@ -249,10 +248,10 @@
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#define PATTERN_CNTRL_REG (0x220)
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#define PATTERN_CNTRL_WR_OFST (0)
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#define PATTERN_CNTRL_WR_MSK (0x00000001 << PATTERN_CNTRL_WR_OFST)
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#define PATTERN_CNTRL_RD_OFST (1)
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#define PATTERN_CNTRL_RD_MSK (0x00000001 << PATTERN_CNTRL_RD_OFST)
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#define PATTERN_CNTRL_WR_OFST (0)
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#define PATTERN_CNTRL_WR_MSK (0x00000001 << PATTERN_CNTRL_WR_OFST)
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#define PATTERN_CNTRL_RD_OFST (1)
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#define PATTERN_CNTRL_RD_MSK (0x00000001 << PATTERN_CNTRL_RD_OFST)
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#define PATTERN_CNTRL_ADDR_OFST (16)
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#define PATTERN_CNTRL_ADDR_MSK (0x00001fff << PATTERN_CNTRL_ADDR_OFST)
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@ -262,15 +261,16 @@
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#define PATTERN_LIMIT_STRT_OFST (0)
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#define PATTERN_LIMIT_STRT_MSK (0x00001fff << PATTERN_LIMIT_STRT_OFST)
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#define PATTERN_LIMIT_STP_OFST (16)
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#define PATTERN_LIMIT_STP_MSK (0x00001fff << PATTERN_LIMIT_STP_OFST)
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#define PATTERN_LIMIT_STP_OFST (16)
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#define PATTERN_LIMIT_STP_MSK (0x00001fff << PATTERN_LIMIT_STP_OFST)
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#define EMPTY22CREG (0x22C)
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#define PATTERN_LOOP_0_ADDR_REG (0x230)
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#define PATTERN_LOOP_0_ADDR_STRT_OFST (0)
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#define PATTERN_LOOP_0_ADDR_STRT_MSK (0x00001fff << PATTERN_LOOP_0_ADDR_STRT_OFST)
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#define PATTERN_LOOP_0_ADDR_STRT_MSK \
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(0x00001fff << PATTERN_LOOP_0_ADDR_STRT_OFST)
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#define PATTERN_LOOP_0_ADDR_STP_OFST (16)
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#define PATTERN_LOOP_0_ADDR_STP_MSK (0x00001fff << PATTERN_LOOP_0_ADDR_STP_OFST)
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@ -294,7 +294,8 @@
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#define PATTERN_LOOP_1_ADDR_REG (0x250)
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#define PATTERN_LOOP_1_ADDR_STRT_OFST (0)
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#define PATTERN_LOOP_1_ADDR_STRT_MSK (0x00001fff << PATTERN_LOOP_1_ADDR_STRT_OFST)
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#define PATTERN_LOOP_1_ADDR_STRT_MSK \
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(0x00001fff << PATTERN_LOOP_1_ADDR_STRT_OFST)
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#define PATTERN_LOOP_1_ADDR_STP_OFST (16)
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#define PATTERN_LOOP_1_ADDR_STP_MSK (0x00001fff << PATTERN_LOOP_1_ADDR_STP_OFST)
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@ -318,7 +319,8 @@
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#define PATTERN_LOOP_2_ADDR_REG (0x270)
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#define PATTERN_LOOP_2_ADDR_STRT_OFST (0)
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#define PATTERN_LOOP_2_ADDR_STRT_MSK (0x00001fff << PATTERN_LOOP_2_ADDR_STRT_OFST)
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#define PATTERN_LOOP_2_ADDR_STRT_MSK \
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(0x00001fff << PATTERN_LOOP_2_ADDR_STRT_OFST)
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#define PATTERN_LOOP_2_ADDR_STP_OFST (16)
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#define PATTERN_LOOP_2_ADDR_STP_MSK (0x00001fff << PATTERN_LOOP_2_ADDR_STP_OFST)
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@ -342,7 +344,8 @@
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#define PATTERN_LOOP_3_ADDR_REG (0x290)
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#define PATTERN_LOOP_3_ADDR_STRT_OFST (0)
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#define PATTERN_LOOP_3_ADDR_STRT_MSK (0x00001fff << PATTERN_LOOP_3_ADDR_STRT_OFST)
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#define PATTERN_LOOP_3_ADDR_STRT_MSK \
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(0x00001fff << PATTERN_LOOP_3_ADDR_STRT_OFST)
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#define PATTERN_LOOP_3_ADDR_STP_OFST (16)
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#define PATTERN_LOOP_3_ADDR_STP_MSK (0x00001fff << PATTERN_LOOP_3_ADDR_STP_OFST)
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@ -366,7 +369,8 @@
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#define PATTERN_LOOP_4_ADDR_REG (0x310)
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#define PATTERN_LOOP_4_ADDR_STRT_OFST (0)
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#define PATTERN_LOOP_4_ADDR_STRT_MSK (0x00001fff << PATTERN_LOOP_4_ADDR_STRT_OFST)
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#define PATTERN_LOOP_4_ADDR_STRT_MSK \
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(0x00001fff << PATTERN_LOOP_4_ADDR_STRT_OFST)
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#define PATTERN_LOOP_4_ADDR_STP_OFST (16)
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#define PATTERN_LOOP_4_ADDR_STP_MSK (0x00001fff << PATTERN_LOOP_4_ADDR_STP_OFST)
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@ -390,7 +394,8 @@
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#define PATTERN_LOOP_5_ADDR_REG (0x330)
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#define PATTERN_LOOP_5_ADDR_STRT_OFST (0)
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#define PATTERN_LOOP_5_ADDR_STRT_MSK (0x00001fff << PATTERN_LOOP_5_ADDR_STRT_OFST)
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#define PATTERN_LOOP_5_ADDR_STRT_MSK \
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(0x00001fff << PATTERN_LOOP_5_ADDR_STRT_OFST)
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#define PATTERN_LOOP_5_ADDR_STP_OFST (16)
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#define PATTERN_LOOP_5_ADDR_STP_MSK (0x00001fff << PATTERN_LOOP_5_ADDR_STP_OFST)
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@ -629,20 +634,21 @@
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#define FIFO_TO_GB_CONTROL_REG (0x500)
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#define ENABLED_CHANNELS_ADC_OFST (0)
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#define ENABLED_CHANNELS_ADC_MSK (0x000000ff << ENABLED_CHANNELS_ADC_OFST)
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#define ENABLED_CHANNELS_D_OFST (8)
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#define ENABLED_CHANNELS_D_MSK (0x00000001 << ENABLED_CHANNELS_D_OFST)
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#define ENABLED_CHANNELS_X_OFST (9)
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#define ENABLED_CHANNELS_X_MSK (0x0000000f << ENABLED_CHANNELS_X_OFST)
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#define RO_MODE_ADC_OFST (13)
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#define RO_MODE_ADC_MSK (0x00000001 << RO_MODE_ADC_OFST)
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#define RO_MODE_D_OFST (14)
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#define RO_MODE_D_MSK (0x00000001 << RO_MODE_D_OFST)
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#define RO_MODE_X_OFST (15)
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#define RO_MODE_X_MSK (0x00000001 << RO_MODE_X_OFST)
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#define ENABLED_CHANNELS_ADC_OFST (0)
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#define ENABLED_CHANNELS_ADC_MSK (0x000000ff << ENABLED_CHANNELS_ADC_OFST)
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#define ENABLED_CHANNELS_D_OFST (8)
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#define ENABLED_CHANNELS_D_MSK (0x00000001 << ENABLED_CHANNELS_D_OFST)
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#define ENABLED_CHANNELS_X_OFST (9)
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#define ENABLED_CHANNELS_X_MSK (0x0000000f << ENABLED_CHANNELS_X_OFST)
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#define RO_MODE_ADC_OFST (13)
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#define RO_MODE_ADC_MSK (0x00000001 << RO_MODE_ADC_OFST)
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#define RO_MODE_D_OFST (14)
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#define RO_MODE_D_MSK (0x00000001 << RO_MODE_D_OFST)
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#define RO_MODE_X_OFST (15)
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#define RO_MODE_X_MSK (0x00000001 << RO_MODE_X_OFST)
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#define COUNT_FRAMES_FROM_UPDATE_OFST (16)
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#define COUNT_FRAMES_FROM_UPDATE_MSK (0x00000001 << COUNT_FRAMES_FROM_UPDATE_OFST)
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#define COUNT_FRAMES_FROM_UPDATE_MSK \
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(0x00000001 << COUNT_FRAMES_FROM_UPDATE_OFST)
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#define START_STREAMING_P_OFST (17)
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#define START_STREAMING_P_MSK (0x00000001 << START_STREAMING_P_OFST)
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@ -811,14 +817,14 @@
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#define MATTERHORNSPICTRL (0x608)
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#define CONFIGSTART_P_OFST (0)
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#define CONFIGSTART_P_MSK (0x00000001 << CONFIGSTART_P_OFST)
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#define PERIPHERYRST_P_OFST (1)
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#define PERIPHERYRST_P_MSK (0x00000001 << PERIPHERYRST_P_OFST)
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#define STARTREAD_P_OFST (2)
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#define STARTREAD_P_MSK (0x00000001 << STARTREAD_P_OFST)
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#define BUSY_OFST (3)
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#define BUSY_MSK (0x00000001 << BUSY_OFST)
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#define CONFIGSTART_P_OFST (0)
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#define CONFIGSTART_P_MSK (0x00000001 << CONFIGSTART_P_OFST)
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#define PERIPHERYRST_P_OFST (1)
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#define PERIPHERYRST_P_MSK (0x00000001 << PERIPHERYRST_P_OFST)
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#define STARTREAD_P_OFST (2)
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#define STARTREAD_P_MSK (0x00000001 << STARTREAD_P_OFST)
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#define BUSY_OFST (3)
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#define BUSY_MSK (0x00000001 << BUSY_OFST)
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#define READOUTFROMASIC_OFST (4)
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#define READOUTFROMASIC_MSK (0x00000001 << READOUTFROMASIC_OFST)
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@ -860,100 +866,69 @@
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#define LINKDOWNLATCHEDOUT_OFST (0)
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#define LINKDOWNLATCHEDOUT_MSK (0x00000001 << LINKDOWNLATCHEDOUT_OFST)
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#define TXUSERCLKACTIVE_OFST (1)
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#define TXUSERCLKACTIVE_MSK (0x00000001 << TXUSERCLKACTIVE_OFST)
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#define RXUSERCLKACTIVE_OFST (2)
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#define RXUSERCLKACTIVE_MSK (0x00000001 << RXUSERCLKACTIVE_OFST)
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#define RXCOMMADET_OFST (3)
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#define RXCOMMADET_MSK (0x0000000f << RXCOMMADET_OFST)
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#define RXBYTEREALIGN_OFST (7)
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#define RXBYTEREALIGN_MSK (0x0000000f << RXBYTEREALIGN_OFST)
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#define RXBYTEISALIGNED_OFST (11)
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#define RXBYTEISALIGNED_MSK (0x0000000f << RXBYTEISALIGNED_OFST)
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#define GTWIZRXCDRSTABLE_OFST (15)
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#define GTWIZRXCDRSTABLE_MSK (0x00000001 << GTWIZRXCDRSTABLE_OFST)
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#define RESETTXDONE_OFST (16)
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#define RESETTXDONE_MSK (0x00000001 << RESETTXDONE_OFST)
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#define RESETRXDONE_OFST (17)
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#define RESETRXDONE_MSK (0x00000001 << RESETRXDONE_OFST)
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#define RXPMARESETDONE_OFST (18)
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#define RXPMARESETDONE_MSK (0x0000000f << RXPMARESETDONE_OFST)
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#define TXPMARESETDONE_OFST (22)
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#define TXPMARESETDONE_MSK (0x0000000f << TXPMARESETDONE_OFST)
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#define GTTPOWERGOOD_OFST (26)
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#define GTTPOWERGOOD_MSK (0x0000000f << GTTPOWERGOOD_OFST)
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#define TXUSERCLKACTIVE_OFST (1)
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#define TXUSERCLKACTIVE_MSK (0x00000001 << TXUSERCLKACTIVE_OFST)
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#define RXUSERCLKACTIVE_OFST (2)
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#define RXUSERCLKACTIVE_MSK (0x00000001 << RXUSERCLKACTIVE_OFST)
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#define RXCOMMADET_OFST (3)
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#define RXCOMMADET_MSK (0x0000000f << RXCOMMADET_OFST)
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#define RXBYTEREALIGN_OFST (7)
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#define RXBYTEREALIGN_MSK (0x0000000f << RXBYTEREALIGN_OFST)
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#define RXBYTEISALIGNED_OFST (11)
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#define RXBYTEISALIGNED_MSK (0x0000000f << RXBYTEISALIGNED_OFST)
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#define GTWIZRXCDRSTABLE_OFST (15)
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#define GTWIZRXCDRSTABLE_MSK (0x00000001 << GTWIZRXCDRSTABLE_OFST)
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#define RESETTXDONE_OFST (16)
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#define RESETTXDONE_MSK (0x00000001 << RESETTXDONE_OFST)
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#define RESETRXDONE_OFST (17)
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#define RESETRXDONE_MSK (0x00000001 << RESETRXDONE_OFST)
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#define RXPMARESETDONE_OFST (18)
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#define RXPMARESETDONE_MSK (0x0000000f << RXPMARESETDONE_OFST)
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#define TXPMARESETDONE_OFST (22)
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#define TXPMARESETDONE_MSK (0x0000000f << TXPMARESETDONE_OFST)
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#define GTTPOWERGOOD_OFST (26)
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#define GTTPOWERGOOD_MSK (0x0000000f << GTTPOWERGOOD_OFST)
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#define TRANSCEIVERSTATUS2 (0x654)
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#define RXLOCKED_OFST (0)
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#define RXLOCKED_MSK (0x0000000f << RXLOCKED_OFST)
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#define EMPTY654REG (0x654)
|
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|
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#define TRANSCEIVERCONTROL (0x658)
|
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|
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#define GTWIZRESETALL_OFST (0)
|
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#define GTWIZRESETALL_MSK (0x00000001 << GTWIZRESETALL_OFST)
|
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#define GTWIZRESETALL_OFST (0)
|
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#define GTWIZRESETALL_MSK (0x00000001 << GTWIZRESETALL_OFST)
|
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#define RESETTXPLLANDDATAPATH_OFST (1)
|
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#define RESETTXPLLANDDATAPATH_MSK (0x00000001 << RESETTXPLLANDDATAPATH_OFST)
|
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#define RESETTXDATAPATHIN_OFST (2)
|
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#define RESETTXDATAPATHIN_MSK (0x00000001 << RESETTXDATAPATHIN_OFST)
|
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#define RESETTXDATAPATHIN_OFST (2)
|
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#define RESETTXDATAPATHIN_MSK (0x00000001 << RESETTXDATAPATHIN_OFST)
|
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#define RESETRXPLLANDDATAPATH_OFST (3)
|
||||
#define RESETRXPLLANDDATAPATH_MSK (0x00000001 << RESETRXPLLANDDATAPATH_OFST)
|
||||
#define RESETRXDATAPATHIN_OFST (4)
|
||||
#define RESETRXDATAPATHIN_MSK (0x00000001 << RESETRXDATAPATHIN_OFST)
|
||||
#define RXPOLARITY_OFST (5)
|
||||
#define RXPOLARITY_MSK (0x0000000f << RXPOLARITY_OFST)
|
||||
#define RXERRORCNTRESET_OFST (9)
|
||||
#define RXERRORCNTRESET_MSK (0x0000000f << RXERRORCNTRESET_OFST)
|
||||
#define RXMSBLSBINVERT_OFST (13)
|
||||
#define RXMSBLSBINVERT_MSK (0x0000000f << RXMSBLSBINVERT_OFST)
|
||||
#define RESETRXDATAPATHIN_OFST (4)
|
||||
#define RESETRXDATAPATHIN_MSK (0x00000001 << RESETRXDATAPATHIN_OFST)
|
||||
#define RXPOLARITY_OFST (5)
|
||||
#define RXPOLARITY_MSK (0x0000000f << RXPOLARITY_OFST)
|
||||
|
||||
#define TRANSCEIVERERRCNT_REG0 (0x65C)
|
||||
#define EMPTY65CREG (0x65C)
|
||||
|
||||
#define TRANSCEIVERERRCNT_REG1 (0x660)
|
||||
#define EMPTY660REG (0x660)
|
||||
|
||||
#define TRANSCEIVERERRCNT_REG2 (0x664)
|
||||
#define EMPTY664REG (0x664)
|
||||
|
||||
#define TRANSCEIVERERRCNT_REG3 (0x668)
|
||||
#define EMPTY668REG (0x668)
|
||||
|
||||
#define TRANSCEIVERALIGNCNT_REG0 (0x66C)
|
||||
#define EMPTY66CREG (0x66C)
|
||||
|
||||
#define RXALIGNCNTCH0_OFST (0)
|
||||
#define RXALIGNCNTCH0_MSK (0x0000ffff << RXALIGNCNTCH0_OFST)
|
||||
#define EMPTY670REG (0x670)
|
||||
|
||||
#define TRANSCEIVERALIGNCNT_REG1 (0x670)
|
||||
#define EMPTY674REG (0x674)
|
||||
|
||||
#define RXALIGNCNTCH1_OFST (0)
|
||||
#define RXALIGNCNTCH1_MSK (0x0000ffff << RXALIGNCNTCH1_OFST)
|
||||
#define EMPTY678REG (0x678)
|
||||
|
||||
#define TRANSCEIVERALIGNCNT_REG2 (0x674)
|
||||
#define EMPTY67CREG (0x67C)
|
||||
|
||||
#define RXALIGNCNTCH2_OFST (0)
|
||||
#define RXALIGNCNTCH2_MSK (0x0000ffff << RXALIGNCNTCH2_OFST)
|
||||
#define EMPTY680REG (0x680)
|
||||
|
||||
#define TRANSCEIVERALIGNCNT_REG3 (0x678)
|
||||
#define EMPTY684REG (0x684)
|
||||
|
||||
#define RXALIGNCNTCH3_OFST (0)
|
||||
#define RXALIGNCNTCH3_MSK (0x0000ffff << RXALIGNCNTCH3_OFST)
|
||||
|
||||
#define TRANSCEIVERLASTWORD_REG0 (0x67C)
|
||||
|
||||
#define RXDATACH0_OFST (0)
|
||||
#define RXDATACH0_MSK (0x0000ffff << RXDATACH0_OFST)
|
||||
|
||||
#define TRANSCEIVERLASTWORD_REG1 (0x680)
|
||||
|
||||
#define RXDATACH1_OFST (0)
|
||||
#define RXDATACH1_MSK (0x0000ffff << RXDATACH1_OFST)
|
||||
|
||||
#define TRANSCEIVERLASTWORD_REG2 (0x684)
|
||||
|
||||
#define RXDATACH2_OFST (0)
|
||||
#define RXDATACH2_MSK (0x0000ffff << RXDATACH2_OFST)
|
||||
|
||||
#define TRANSCEIVERLASTWORD_REG3 (0x688)
|
||||
|
||||
#define RXDATACH3_OFST (0)
|
||||
#define RXDATACH3_MSK (0x0000ffff << RXDATACH3_OFST)
|
||||
#define EMPTY688REG (0x688)
|
||||
|
||||
#define EMPTY68CREG (0x68C)
|
||||
|
||||
@ -1015,18 +990,18 @@
|
||||
|
||||
#define DBITFIFOCTRLREG (0x700)
|
||||
|
||||
#define DBITRD_OFST (0)
|
||||
#define DBITRD_MSK (0x00000001 << DBITRD_OFST)
|
||||
#define DBITRST_OFST (1)
|
||||
#define DBITRST_MSK (0x00000001 << DBITRST_OFST)
|
||||
#define DBITFULL_OFST (2)
|
||||
#define DBITFULL_MSK (0x00000001 << DBITFULL_OFST)
|
||||
#define DBITEMPTY_OFST (3)
|
||||
#define DBITEMPTY_MSK (0x00000001 << DBITEMPTY_OFST)
|
||||
#define DBITRD_OFST (0)
|
||||
#define DBITRD_MSK (0x00000001 << DBITRD_OFST)
|
||||
#define DBITRST_OFST (1)
|
||||
#define DBITRST_MSK (0x00000001 << DBITRST_OFST)
|
||||
#define DBITFULL_OFST (2)
|
||||
#define DBITFULL_MSK (0x00000001 << DBITFULL_OFST)
|
||||
#define DBITEMPTY_OFST (3)
|
||||
#define DBITEMPTY_MSK (0x00000001 << DBITEMPTY_OFST)
|
||||
#define DBITUNDERFLOW_OFST (4)
|
||||
#define DBITUNDERFLOW_MSK (0x00000001 << DBITUNDERFLOW_OFST)
|
||||
#define DBITOVERFLOW_OFST (5)
|
||||
#define DBITOVERFLOW_MSK (0x00000001 << DBITOVERFLOW_OFST)
|
||||
#define DBITOVERFLOW_OFST (5)
|
||||
#define DBITOVERFLOW_MSK (0x00000001 << DBITOVERFLOW_OFST)
|
||||
|
||||
#define EMPTYREG (0x704)
|
||||
|
||||
|
||||
Reference in New Issue
Block a user