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MY3.0:read and write Registers, frames, cycles, delay (#64)

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* MY3.0:read and write Registers, frames, cycles, delay

* write pattern seems to work

* done all corrections. added default clks: run_clk=125MHz, tick_clk=20MHz (fix), sampling_clk=80MHz (from Carlos)

* clk check for aquistition time

* clk check for aquistition time

* Update slsDetectorServer_defs.h

* Update slsDetectorFunctionList.c
This commit is contained in:
Marie Andrä
2019-09-30 14:36:33 +02:00
committed by Dhanya Thattil
parent 3d52a2f169
commit 6e6fcec698
9 changed files with 490 additions and 56 deletions
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2
slsSupportLib/include/versionAPI.h
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@ -8,5 +8,5 @@
#define APIGOTTHARD 0x190902
#define APIJUNGFRAU 0x190902
#define APIEIGER 0x190902
#define APIMYTHEN3 0x190903
#define APIGOTTHARD2 0x190927
#define APIMYTHEN3 0x190930