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MY3.0:read and write Registers, frames, cycles, delay (#64)

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* MY3.0:read and write Registers, frames, cycles, delay

* write pattern seems to work

* done all corrections. added default clks: run_clk=125MHz, tick_clk=20MHz (fix), sampling_clk=80MHz (from Carlos)

* clk check for aquistition time

* clk check for aquistition time

* Update slsDetectorServer_defs.h

* Update slsDetectorFunctionList.c
This commit is contained in:
Marie Andrä
2019-09-30 14:36:33 +02:00
committed by Dhanya Thattil
parent 3d52a2f169
commit 6e6fcec698
9 changed files with 490 additions and 56 deletions
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166
slsDetectorServers/mythen3DetectorServer/RegisterDefs.h
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@ -2,39 +2,159 @@
#pragma once
/* Definitions for FPGA*/
#define MEM_MAP_SHIFT 1
#define BASE_CONTROL (0x0)
#define BASE_PATTERN_CONTROL (0x200 )
#define BASE_PATTERN_RAM (0x10000 )
/* Basic detector FPGA registers --------------------------------------------------*/
/* FPGA Version register */
#define FPGA_VERSION_REG (0x04 + BASE_CONTROL)
#define FPGA_COMPILATION_DATE_OFST (0)
#define FPGA_COMPILATION_DATE_MSK (0x00FFFFFF << FPGA_COMPILATION_DATE_OFST)
#define DETECTOR_TYPE_OFST (24)
#define DETECTOR_TYPE_MSK (0x000000FF << DETECTOR_TYPE_OFST)
/* Module Control Board Serial Number Register */
#define MCB_SERIAL_NO_REG (0x00 + BASE_CONTROL)
/* API Version Register */
#define API_VERSION_REG (0x08 + BASE_CONTROL)
/* Fix pattern register */
#define FIX_PATT_REG (0x0C + BASE_CONTROL)
#define FIX_PATT_VAL (0xACDC2019)
/* Status register */
#define STATUS_REG (0x10 + BASE_CONTROL)
#ifdef VIRTUAL // until firmware is ready ----------------------------------
/* Status register */
#define STATUS_REG (0x01 << MEM_MAP_SHIFT)
#define RUN_BUSY_OFST (0)
#define RUN_BUSY_MSK (0x00000001 << RUN_BUSY_OFST)
#endif
/* Set Cycles 64 bit register */
#define SET_CYCLES_LSB_REG (0x02 << MEM_MAP_SHIFT)
#define SET_CYCLES_MSB_REG (0x03 << MEM_MAP_SHIFT)
/* Look at me register */
#define LOOK_AT_ME_REG (0x14 + BASE_CONTROL) //Not used in firmware or software, good to play with
/* Set Frames 64 bit register */
#define SET_FRAMES_LSB_REG (0x04 << MEM_MAP_SHIFT)
#define SET_FRAMES_MSB_REG (0x05 << MEM_MAP_SHIFT)
/* Set Period 64 bit register tT = T x 50 ns */
#define SET_PERIOD_LSB_REG (0x06 << MEM_MAP_SHIFT)
#define SET_PERIOD_MSB_REG (0x07 << MEM_MAP_SHIFT)
/* Pattern Control FPGA registers --------------------------------------------------*/
/* Pattern status Register*/
#define PAT_STATUS_REG (0x00 + BASE_PATTERN_CONTROL)
/* Set Exptime 64 bit register eEXP = Exp x 25 ns */
#define SET_EXPTIME_LSB_REG (0x08 << MEM_MAP_SHIFT)
#define SET_EXPTIME_MSB_REG (0x09 << MEM_MAP_SHIFT)
/* Delay left 64bit Register */
#define GET_DELAY_LSB_REG (0x08 + BASE_PATTERN_CONTROL)
#define GET_DELAY_MSB_REG (0x0C + BASE_PATTERN_CONTROL)
/* Get Cycles 64 bit register */
#define GET_CYCLES_LSB_REG (0x0A << MEM_MAP_SHIFT)
#define GET_CYCLES_MSB_REG (0x0B << MEM_MAP_SHIFT)
/* Cycles left 64bit Register */
#define GET_CYCLES_LSB_REG (0x10 + BASE_PATTERN_CONTROL)
#define GET_CYCLES_MSB_REG (0x14 + BASE_PATTERN_CONTROL)
/* Get Frames 64 bit register */
#define GET_FRAMES_LSB_REG (0x0C << MEM_MAP_SHIFT)
#define GET_FRAMES_MSB_REG (0x0D << MEM_MAP_SHIFT)
#endif
/* Frames left 64bit Register */
#define GET_FRAMES_LSB_REG (0x18 + BASE_PATTERN_CONTROL)
#define GET_FRAMES_MSB_REG (0x1C + BASE_PATTERN_CONTROL)
/* Period left 64bit Register */
#define GET_PERIOD_LSB_REG (0x20 + BASE_PATTERN_CONTROL)
#define GET_PERIOD_MSB_REG (0x24 + BASE_PATTERN_CONTROL)
/* Delay 64bit Write-register */
#define SET_DELAY_LSB_REG (0x88 + BASE_PATTERN_CONTROL)
#define SET_DELAY_MSB_REG (0x8C + BASE_PATTERN_CONTROL)
/* Cylces 64bit Write-register */
#define SET_CYCLES_LSB_REG (0x90 + BASE_PATTERN_CONTROL)
#define SET_CYCLES_MSB_REG (0x94 + BASE_PATTERN_CONTROL)
/* Frames 64bit Write-register */
#define SET_FRAMES_LSB_REG (0x98 + BASE_PATTERN_CONTROL)
#define SET_FRAMES_MSB_REG (0x9C + BASE_PATTERN_CONTROL)
/* Period 64bit Write-register */
#define SET_PERIOD_LSB_REG (0xA0 + BASE_PATTERN_CONTROL)
#define SET_PERIOD_MSB_REG (0xA4 + BASE_PATTERN_CONTROL)
/* Pattern Control FPGA registers --------------------------------------------------*/
// /* Pattern IO Control 64 bit RW Register
// * Each bit configured as output(1)/ input(0) */
// #define PATTERN_IO_CNTRL_LSB_REG (0x88 + BASE_CONTROL)
// #define PATTERN_IO_CNTRL_MSB_REG (0x8C + BASE_CONTROL)
/* Pattern Limit RW Register */
#define PATTERN_LIMIT_REG (0x100 + BASE_PATTERN_CONTROL)
#define PATTERN_LIMIT_STRT_OFST (0)
#define PATTERN_LIMIT_STRT_MSK (0x00001FFF << PATTERN_LIMIT_STRT_OFST)
#define PATTERN_LIMIT_STP_OFST (16)
#define PATTERN_LIMIT_STP_MSK (0x00001FFF << PATTERN_LIMIT_STP_OFST)
/* Pattern Wait 0 RW Register*/
#define PATTERN_WAIT_0_ADDR_REG (0x188 + BASE_PATTERN_CONTROL)
#define PATTERN_WAIT_0_ADDR_OFST (0)
#define PATTERN_WAIT_0_ADDR_MSK (0x00001FFF << PATTERN_WAIT_0_ADDR_OFST)
/* Pattern Wait 1 RW Register*/
#define PATTERN_WAIT_1_ADDR_REG (0x19C + BASE_PATTERN_CONTROL)
#define PATTERN_WAIT_1_ADDR_OFST (0)
#define PATTERN_WAIT_1_ADDR_MSK (0x00001FFF << PATTERN_WAIT_1_ADDR_OFST)
/* Pattern Wait 2 RW Register*/
#define PATTERN_WAIT_2_ADDR_REG (0x1B0 + BASE_PATTERN_CONTROL)
#define PATTERN_WAIT_2_ADDR_OFST (0)
#define PATTERN_WAIT_2_ADDR_MSK (0x00001FFF << PATTERN_WAIT_2_ADDR_OFST)
/* Pattern Wait Timer 0 64bit RW Register */
#define PATTERN_WAIT_TIMER_0_LSB_REG (0x180 + BASE_PATTERN_CONTROL)
#define PATTERN_WAIT_TIMER_0_MSB_REG (0x184 + BASE_PATTERN_CONTROL)
/* Pattern Wait Timer 1 64bit RW Register */
#define PATTERN_WAIT_TIMER_1_LSB_REG (0x194 + BASE_PATTERN_CONTROL)
#define PATTERN_WAIT_TIMER_1_MSB_REG (0x198 + BASE_PATTERN_CONTROL)
/* Pattern Wait Timer 2 64bit RW Register */
#define PATTERN_WAIT_TIMER_2_LSB_REG (0x1A8 + BASE_PATTERN_CONTROL)
#define PATTERN_WAIT_TIMER_2_MSB_REG (0x1AC + BASE_PATTERN_CONTROL)
/* Pattern Loop 0 Address RW Register */
#define PATTERN_LOOP_0_ADDR_REG (0x190 + BASE_PATTERN_CONTROL)
#define PATTERN_LOOP_0_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_0_ADDR_STRT_MSK (0x00001FFF << PATTERN_LOOP_0_ADDR_STRT_OFST)
#define PATTERN_LOOP_0_ADDR_STP_OFST (16)
#define PATTERN_LOOP_0_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_0_ADDR_STP_OFST)
/* Pattern Loop 1 Address RW Register */
#define PATTERN_LOOP_1_ADDR_REG (0x1A4 + BASE_PATTERN_CONTROL)
#define PATTERN_LOOP_1_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_1_ADDR_STRT_MSK (0x00001FFF << PATTERN_LOOP_1_ADDR_STRT_OFST)
#define PATTERN_LOOP_1_ADDR_STP_OFST (16)
#define PATTERN_LOOP_1_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_1_ADDR_STP_OFST)
/* Pattern Loop 0 Address RW Register */
#define PATTERN_LOOP_2_ADDR_REG (0x1B8 + BASE_PATTERN_CONTROL)
#define PATTERN_LOOP_2_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_2_ADDR_STRT_MSK (0x00001FFF << PATTERN_LOOP_2_ADDR_STRT_OFST)
#define PATTERN_LOOP_2_ADDR_STP_OFST (16)
#define PATTERN_LOOP_2_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_2_ADDR_STP_OFST)
/* Pattern Loop 0 Iteration RW Register */
#define PATTERN_LOOP_0_ITERATION_REG (0x18C + BASE_PATTERN_CONTROL) // patnloop
/* Pattern Loop 1 Iteration RW Register */
#define PATTERN_LOOP_1_ITERATION_REG (0x1A0 + BASE_PATTERN_CONTROL) // patnloop
/* Pattern Loop 2 Iteration RW Register */
#define PATTERN_LOOP_2_ITERATION_REG (0x1B4 + BASE_PATTERN_CONTROL) // patnloop
/* Register of first word */
#define PATTERN_STEP0_LSB_REG (0x0 + BASE_PATTERN_RAM)
#define PATTERN_STEP0_MSB_REG (0x4 + BASE_PATTERN_RAM)