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ctb: added altchip_id read register
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@ -223,6 +223,9 @@
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#define DBIT_INJECT_COUNTER_CLKDIV_OFST (8) // Additional clock divider for fake-data injection
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#define DBIT_INJECT_COUNTER_CLKDIV_OFST (8) // Additional clock divider for fake-data injection
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#define DBIT_INJECT_COUNTER_CLKDIV_MSK (0x000000FF << DBIT_INJECT_COUNTER_CLKDIV_OFST)
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#define DBIT_INJECT_COUNTER_CLKDIV_MSK (0x000000FF << DBIT_INJECT_COUNTER_CLKDIV_OFST)
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/* 64-bit FPGA chip ID. Unique for every device. read-only */
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#define FPGA_chipID_0_REG (0x48 << MEM_MAP_SHIFT)
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#define FPGA_chipID_1_REG (0x49 << MEM_MAP_SHIFT)
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/* FIFO Transceiver In 64 bit RO register */
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/* FIFO Transceiver In 64 bit RO register */
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#define FIFO_TIN_LSB_REG (0x31 << MEM_MAP_SHIFT)
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#define FIFO_TIN_LSB_REG (0x31 << MEM_MAP_SHIFT)
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