detectors/slsDetectorPackage
25
0
Fork 0
mirror of https://github.com/slsdetectorgroup/slsDetectorPackage.git synced 2025-06-23 01:58:00 +02:00
Code Issues Actions Packages Releases Activity

Merge branch 'developer' into esrfchanges

Browse Source
This commit is contained in:
maliakal_d
2018-05-02 16:57:03 +02:00
parent d3a0319863 516336963e
commit 5b01b4cbd8
45 changed files with 2716 additions and 1467 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
slsDetectorSoftware/gitInfo.txt
View File

@ -1,9 +1,18 @@
Path: slsDetectorsPackage/slsDetectorSoftware
URL: origin git@github.com:slsdetectorgroup/slsDetectorPackage.git
Repository Root: origin git@github.com:slsdetectorgroup/slsDetectorPackage.git
<<<<<<< HEAD
Repsitory UUID: ab06c33107ecfeb4741d49407903ff80286cf75b
Revision: 1846
Branch: developer
Last Changed Author: Anna_Bergamaschi
Last Changed Rev: 3731
Last Changed Date: 2018-03-15 12:30:34.000000002 +0100 ./threadFiles/ThreadPool.o
=======
Repsitory UUID: b8bdbf4da61f95b88893b02ddabc2491b16fa10f
Revision: 1852
Branch: developer
Last Changed Author: Dhanya_Thattil
Last Changed Rev: 3746
Last Changed Date: 2018-03-27 10:47:02.000000002 +0200 ./slsDetector/slsDetector.o
>>>>>>> 7cd35f24b87501374fbaf45693a2adf16dfae3e3

4
slsDetectorSoftware/jctbDetectorServer/blackfin.h
View File

@ -3,8 +3,10 @@
#define CSP0 0x20200000
#define MEM_SIZE 0x100000
#define MEM_MAP_SHIFT 1
#include <sys/types.h>
#include <sys/types.h>
int mapCSP0(void);
u_int16_t bus_r16(u_int32_t offset);

1
slsDetectorSoftware/jctbDetectorServer/firmware_funcs.c
View File

@ -1289,6 +1289,7 @@ int64_t setExposureTime(int64_t value){
/* time is in ns */
if (value!=-1)
value*=(1E-3*clkDivider[0]);//(1E-9*CLK_FREQ);
setPatternWaitTime(0,value);
return set64BitReg(value,SET_EXPTIME_LSB_REG, SET_EXPTIME_MSB_REG)/(1E-3*clkDivider[0]);//(1E-9*CLK_FREQ);
}

10
slsDetectorSoftware/jctbDetectorServer/gitInfo.txt
View File

@ -1,9 +1,9 @@
Path: slsDetectorsPackage/slsDetectorSoftware/jctbDetectorServer
URL: origin git@github.com:slsdetectorgroup/slsDetectorPackage.git
Repository Root: origin git@github.com:slsdetectorgroup/slsDetectorPackage.git
Repsitory UUID: 3da6a6df6556312f7467407a8b5691bdc478424e
Revision: 21
Repsitory UUID: c35203ebfb35ba605eaff601ce46e4d29c1f5690
Revision: 24
Branch: developer
Last Changed Author: Dhanya_Thattil
Last Changed Rev: 3597
Last Changed Date: 2018-02-07 10:44:13.000000002 +0100 ./server_funcs.h
Last Changed Author: Anna_Bergamaschi
Last Changed Rev: 3761
Last Changed Date: 2018-04-27 14:46:10.176661554 +0200 ./server_funcs.h

8
slsDetectorSoftware/jctbDetectorServer/gitInfoMoench.h
View File

@ -1,6 +1,6 @@
#define GITURL "git@github.com:slsdetectorgroup/slsDetectorPackage.git"
#define GITREPUUID "3da6a6df6556312f7467407a8b5691bdc478424e"
#define GITAUTH "Dhanya_Thattil"
#define GITREV 0x3597
#define GITDATE 0x20180207
#define GITREPUUID "c35203ebfb35ba605eaff601ce46e4d29c1f5690"
#define GITAUTH "Anna_Bergamaschi"
#define GITREV 0x3761
#define GITDATE 0x20180427
#define GITBRANCH "developer"

BIN
slsDetectorSoftware/jctbDetectorServer/jctbDetectorServer_developer
View File

Binary file not shown.

282
slsDetectorSoftware/jctbDetectorServer/registers_m.h Executable file → Normal file
View File

@ -20,7 +20,7 @@
#define FPGA_INIT_ADDR 0xb0000000
//#ifdef JUNGFRAU_DHANYA
#define POWER_ON_REG 0x5e<<11
#define POWER_ON_REG 0x5e << MEM_MAP_SHIFT
// Pwr_I2C_SDA <= PowerReg_s(1) when PowerReg_s(3)='1' else 'Z';
// Pwr_I2C_SCL <= PowerReg_s(0) when PowerReg_s(2)='1' else 'Z';
@ -29,71 +29,71 @@
#define PWR_I2C_SCL_EN_BIT 2
#define PWR_I2C_SDA_EN_BIT 3
#define POWER_STATUS_REG 41<<11
#define POWER_STATUS_REG 41 << MEM_MAP_SHIFT
#define ADCREG1 0x08
#define ADCREG2 0x14//20
#define ADCREG3 0x4
#define ADCREG4 0x5
#define ADCREG_VREFS 24
#define DBIT_PIPELINE_REG 89<<11 //0x59 same PATTERN_N_LOOP2_REG
#define MEM_MACHINE_FIFOS_REG 79<<11 //from gotthard
#define CONFGAIN_REG 93<<11 //from gotthard
#define ADC_PIPELINE_REG 66<<11 //0x42 same as ADC_OFFSET_REG
#define DBIT_PIPELINE_REG 89 << MEM_MAP_SHIFT //0x59 same PATTERN_N_LOOP2_REG
#define MEM_MACHINE_FIFOS_REG 79 << MEM_MAP_SHIFT //from gotthard
#define CONFGAIN_REG 93 << MEM_MAP_SHIFT //from gotthard
#define ADC_PIPELINE_REG 66 << MEM_MAP_SHIFT //0x42 same as ADC_OFFSET_REG
//#endif
//#define ADC_OFFSET_REG 93<<11 //same as DAQ_REG
#define ADC_INVERSION_REG 67<<11
//#define ADC_OFFSET_REG 93 << MEM_MAP_SHIFT //same as DAQ_REG
#define ADC_INVERSION_REG 67 << MEM_MAP_SHIFT
#define DAC_REG 64<<11//0x17<<11// control the dacs
#define DAC_REG 64 << MEM_MAP_SHIFT//0x17 << MEM_MAP_SHIFT// control the dacs
//ADC
#define ADC_WRITE_REG 65<<11//0x18<<11
//#define ADC_SYNC_REG 66<<11//0x19<<11
//#define HV_REG 67<<11//0x20<<11
#define ADC_WRITE_REG 65 << MEM_MAP_SHIFT//0x18 << MEM_MAP_SHIFT
//#define ADC_SYNC_REG 66 << MEM_MAP_SHIFT//0x19 << MEM_MAP_SHIFT
//#define HV_REG 67 << MEM_MAP_SHIFT//0x20 << MEM_MAP_SHIFT
//#define MUTIME_REG 0x1a<<11
//#define MUTIME_REG 0x1a << MEM_MAP_SHIFT
//temperature
#define TEMP_IN_REG 0x1b<<11
#define TEMP_OUT_REG 0x1c<<11
#define TEMP_IN_REG 0x1b << MEM_MAP_SHIFT
#define TEMP_OUT_REG 0x1c << MEM_MAP_SHIFT
//configure MAC
#define TSE_CONF_REG 0x1d<<11
#define ENET_CONF_REG 0x1e<<11
//#define WRTSE_SHAD_REG 0x1f<<11
#define TSE_CONF_REG 0x1d << MEM_MAP_SHIFT
#define ENET_CONF_REG 0x1e << MEM_MAP_SHIFT
//#define WRTSE_SHAD_REG 0x1f << MEM_MAP_SHIFT
//HV
#define DUMMY_REG 68<<11//0x21<<11
#define FPGA_VERSION_REG 0<<11 //0x22<<11
#define PCB_REV_REG 0<<11
#define FIX_PATT_REG 1<<11 //0x23<<11
#define CONTROL_REG 79<<11//0x24<<11
#define STATUS_REG 2<<11 //0x25<<11
#define CONFIG_REG 77<<11//0x26<<11
#define EXT_SIGNAL_REG 78<<11// 0x27<<11
//#define FPGA_SVN_REG 0x29<<11
#define DUMMY_REG 68 << MEM_MAP_SHIFT//0x21 << MEM_MAP_SHIFT
#define FPGA_VERSION_REG 0 << MEM_MAP_SHIFT //0x22 << MEM_MAP_SHIFT
#define PCB_REV_REG 0 << MEM_MAP_SHIFT
#define FIX_PATT_REG 1 << MEM_MAP_SHIFT //0x23 << MEM_MAP_SHIFT
#define CONTROL_REG 79 << MEM_MAP_SHIFT//0x24 << MEM_MAP_SHIFT
#define STATUS_REG 2 << MEM_MAP_SHIFT //0x25 << MEM_MAP_SHIFT
#define CONFIG_REG 77 << MEM_MAP_SHIFT//0x26 << MEM_MAP_SHIFT
#define EXT_SIGNAL_REG 78 << MEM_MAP_SHIFT// 0x27 << MEM_MAP_SHIFT
//#define FPGA_SVN_REG 0x29 << MEM_MAP_SHIFT
#define CHIP_OF_INTRST_REG 0x2A<<11
#define CHIP_OF_INTRST_REG 0x2A << MEM_MAP_SHIFT
//FIFO
#define LOOK_AT_ME_REG 3<<11 //0x28<<11
#define SYSTEM_STATUS_REG 4<<11
#define LOOK_AT_ME_REG 3 << MEM_MAP_SHIFT //0x28 << MEM_MAP_SHIFT
#define SYSTEM_STATUS_REG 4 << MEM_MAP_SHIFT
#define FIFO_DATA_REG 6<<11
#define FIFO_STATUS_REG 7<<11
#define FIFO_DATA_REG 6 << MEM_MAP_SHIFT
#define FIFO_STATUS_REG 7 << MEM_MAP_SHIFT
// constant FifoDigitalInReg_c : integer := 60;
#define FIFO_DIGITAL_DATA_LSB_REG 60<<11
#define FIFO_DIGITAL_DATA_MSB_REG 61<<11
#define FIFO_DIGITAL_DATA_LSB_REG 60 << MEM_MAP_SHIFT
#define FIFO_DIGITAL_DATA_MSB_REG 61 << MEM_MAP_SHIFT
#define FIFO_DATA_REG_OFF 0x50<<11 ///////
#define FIFO_DATA_REG_OFF 0x50 << MEM_MAP_SHIFT ///////
//to read back dac registers
//#define MOD_DACS1_REG 0x65<<11
//#define MOD_DACS2_REG 0x66<<11
//#define MOD_DACS3_REG 0x67<<11
//#define MOD_DACS1_REG 0x65 << MEM_MAP_SHIFT
//#define MOD_DACS2_REG 0x66 << MEM_MAP_SHIFT
//#define MOD_DACS3_REG 0x67 << MEM_MAP_SHIFT
//user entered
@ -102,135 +102,135 @@
#define GET_ACTUAL_TIME_LSB_REG 16<<11
#define GET_ACTUAL_TIME_MSB_REG 17<<11
#define GET_ACTUAL_TIME_LSB_REG 16 << MEM_MAP_SHIFT
#define GET_ACTUAL_TIME_MSB_REG 17 << MEM_MAP_SHIFT
#define GET_MEASUREMENT_TIME_LSB_REG 38<<11
#define GET_MEASUREMENT_TIME_MSB_REG 39<<11
#define GET_MEASUREMENT_TIME_LSB_REG 38 << MEM_MAP_SHIFT
#define GET_MEASUREMENT_TIME_MSB_REG 39 << MEM_MAP_SHIFT
#define SET_DELAY_LSB_REG 96<<11 //0x68<<11
#define SET_DELAY_MSB_REG 97<<11 //0x69<<11
#define GET_DELAY_LSB_REG 18<<11//0x6a<<11
#define GET_DELAY_MSB_REG 19<<11//0x6b<<11
#define SET_DELAY_LSB_REG 96 << MEM_MAP_SHIFT //0x68 << MEM_MAP_SHIFT
#define SET_DELAY_MSB_REG 97 << MEM_MAP_SHIFT //0x69 << MEM_MAP_SHIFT
#define GET_DELAY_LSB_REG 18 << MEM_MAP_SHIFT//0x6a << MEM_MAP_SHIFT
#define GET_DELAY_MSB_REG 19 << MEM_MAP_SHIFT//0x6b << MEM_MAP_SHIFT
#define SET_CYCLES_LSB_REG 98<<11//0x6c<<11
#define SET_CYCLES_MSB_REG 99<<11//0x6d<<11
#define GET_CYCLES_LSB_REG 20<<11//0x6e<<11
#define GET_CYCLES_MSB_REG 21<<11//0x6f<<11
#define SET_CYCLES_LSB_REG 98 << MEM_MAP_SHIFT//0x6c << MEM_MAP_SHIFT
#define SET_CYCLES_MSB_REG 99 << MEM_MAP_SHIFT//0x6d << MEM_MAP_SHIFT
#define GET_CYCLES_LSB_REG 20 << MEM_MAP_SHIFT//0x6e << MEM_MAP_SHIFT
#define GET_CYCLES_MSB_REG 21 << MEM_MAP_SHIFT//0x6f << MEM_MAP_SHIFT
#define SET_FRAMES_LSB_REG 100<<11//0x70<<11
#define SET_FRAMES_MSB_REG 101<<11//0x71<<11
#define GET_FRAMES_LSB_REG 22<<11//0x72<<11
#define GET_FRAMES_MSB_REG 23<<11//0x73<<11
#define SET_FRAMES_LSB_REG 100 << MEM_MAP_SHIFT//0x70 << MEM_MAP_SHIFT
#define SET_FRAMES_MSB_REG 101 << MEM_MAP_SHIFT//0x71 << MEM_MAP_SHIFT
#define GET_FRAMES_LSB_REG 22 << MEM_MAP_SHIFT//0x72 << MEM_MAP_SHIFT
#define GET_FRAMES_MSB_REG 23 << MEM_MAP_SHIFT//0x73 << MEM_MAP_SHIFT
#define SET_PERIOD_LSB_REG 102<<11//0x74<<11
#define SET_PERIOD_MSB_REG 103<<11//0x75<<11
#define GET_PERIOD_LSB_REG 24<<11//0x76<<11
#define GET_PERIOD_MSB_REG 25<<11//0x77<<11
#define SET_PERIOD_LSB_REG 102 << MEM_MAP_SHIFT//0x74 << MEM_MAP_SHIFT
#define SET_PERIOD_MSB_REG 103 << MEM_MAP_SHIFT//0x75 << MEM_MAP_SHIFT
#define GET_PERIOD_LSB_REG 24 << MEM_MAP_SHIFT//0x76 << MEM_MAP_SHIFT
#define GET_PERIOD_MSB_REG 25 << MEM_MAP_SHIFT//0x77 << MEM_MAP_SHIFT
//#define PATTERN_WAIT0_TIME_REG_LSB 114<<11
//#define PATTERN_WAIT0_TIME_REG_MSB 115<<11
#define SET_EXPTIME_LSB_REG 114<<11//0x78<<11
#define SET_EXPTIME_MSB_REG 115<<11//0x79<<11
#define GET_EXPTIME_LSB_REG 26<<11//0x7a<<11
#define GET_EXPTIME_MSB_REG 27<<11//0x7b<<11
//#define PATTERN_WAIT0_TIME_REG_LSB 114 << MEM_MAP_SHIFT
//#define PATTERN_WAIT0_TIME_REG_MSB 115 << MEM_MAP_SHIFT
#define SET_EXPTIME_LSB_REG 114 << MEM_MAP_SHIFT//0x78 << MEM_MAP_SHIFT
#define SET_EXPTIME_MSB_REG 115 << MEM_MAP_SHIFT//0x79 << MEM_MAP_SHIFT
#define GET_EXPTIME_LSB_REG 26 << MEM_MAP_SHIFT//0x7a << MEM_MAP_SHIFT
#define GET_EXPTIME_MSB_REG 27 << MEM_MAP_SHIFT//0x7b << MEM_MAP_SHIFT
#define SET_GATES_LSB_REG 106<<11//0x7c<<11
#define SET_GATES_MSB_REG 107<<11//0x7d<<11
#define GET_GATES_LSB_REG 28<<11//0x7e<<11
#define GET_GATES_MSB_REG 29<<11//0x7f<<11
#define SET_GATES_LSB_REG 106 << MEM_MAP_SHIFT//0x7c << MEM_MAP_SHIFT
#define SET_GATES_MSB_REG 107 << MEM_MAP_SHIFT//0x7d << MEM_MAP_SHIFT
#define GET_GATES_LSB_REG 28 << MEM_MAP_SHIFT//0x7e << MEM_MAP_SHIFT
#define GET_GATES_MSB_REG 29 << MEM_MAP_SHIFT//0x7f << MEM_MAP_SHIFT
#define DATA_IN_LSB_REG 30<<11
#define DATA_IN_MSB_REG 31<<11
#define DATA_IN_LSB_REG 30 << MEM_MAP_SHIFT
#define DATA_IN_MSB_REG 31 << MEM_MAP_SHIFT
#define PATTERN_OUT_LSB_REG 32<<11
#define PATTERN_OUT_MSB_REG 33<<11
#define PATTERN_OUT_LSB_REG 32 << MEM_MAP_SHIFT
#define PATTERN_OUT_MSB_REG 33 << MEM_MAP_SHIFT
#define FRAMES_FROM_START_LSB_REG 34<<11
#define FRAMES_FROM_START_MSB_REG 35<<11
#define FRAMES_FROM_START_LSB_REG 34 << MEM_MAP_SHIFT
#define FRAMES_FROM_START_MSB_REG 35 << MEM_MAP_SHIFT
#define FRAMES_FROM_START_PG_LSB_REG 36<<11
#define FRAMES_FROM_START_PG_MSB_REG 37<<11
#define FRAMES_FROM_START_PG_LSB_REG 36 << MEM_MAP_SHIFT
#define FRAMES_FROM_START_PG_MSB_REG 37 << MEM_MAP_SHIFT
#define SLOW_ADC_REG 43<<11
#define SLOW_ADC_REG 43 << MEM_MAP_SHIFT
#define PLL_PARAM_REG 80<<11//0x37<<11
#define PLL_PARAM_OUT_REG 5<<11 //0x38<<11
#define PLL_CNTRL_REG 81<<11//0x34<<11
#define PLL_PARAM_REG 80 << MEM_MAP_SHIFT//0x37 << MEM_MAP_SHIFT
#define PLL_PARAM_OUT_REG 5 << MEM_MAP_SHIFT //0x38 << MEM_MAP_SHIFT
#define PLL_CNTRL_REG 81 << MEM_MAP_SHIFT//0x34 << MEM_MAP_SHIFT
#ifdef NEW_GBE_INTERFACE
#define GBE_PARAM_OUT_REG 40<<11
#define GBE_PARAM_REG 69<<11
#define GBE_CNTRL_REG 70<<11
#define GBE_PARAM_OUT_REG 40 << MEM_MAP_SHIFT
#define GBE_PARAM_REG 69 << MEM_MAP_SHIFT
#define GBE_CNTRL_REG 70 << MEM_MAP_SHIFT
#else
#define RX_UDP_AREG 69<<11 //rx_udpip_AReg_c : integer:= 69; *\/
#define UDPPORTS_AREG 70<<11// udpports_AReg_c : integer:= 70; *\/
#define RX_UDPMACL_AREG 71<<11//rx_udpmacL_AReg_c : integer:= 71; *\/
#define RX_UDPMACH_AREG 72<<11//rx_udpmacH_AReg_c : integer:= 72; *\/
#define DETECTORMACL_AREG 73<<11//detectormacL_AReg_c : integer:= 73; *\/
#define DETECTORMACH_AREG 74<<11//detectormacH_AReg_c : integer:= 74; *\/
#define DETECTORIP_AREG 75<<11//detectorip_AReg_c : integer:= 75; *\/
#define IPCHKSUM_AREG 76<<11//ipchksum_AReg_c : integer:= 76; *\/ */
#define RX_UDP_AREG 69 << MEM_MAP_SHIFT //rx_udpip_AReg_c : integer:= 69; *\/
#define UDPPORTS_AREG 70 << MEM_MAP_SHIFT// udpports_AReg_c : integer:= 70; *\/
#define RX_UDPMACL_AREG 71 << MEM_MAP_SHIFT//rx_udpmacL_AReg_c : integer:= 71; *\/
#define RX_UDPMACH_AREG 72 << MEM_MAP_SHIFT//rx_udpmacH_AReg_c : integer:= 72; *\/
#define DETECTORMACL_AREG 73 << MEM_MAP_SHIFT//detectormacL_AReg_c : integer:= 73; *\/
#define DETECTORMACH_AREG 74 << MEM_MAP_SHIFT//detectormacH_AReg_c : integer:= 74; *\/
#define DETECTORIP_AREG 75 << MEM_MAP_SHIFT//detectorip_AReg_c : integer:= 75; *\/
#define IPCHKSUM_AREG 76 << MEM_MAP_SHIFT//ipchksum_AReg_c : integer:= 76; *\/ */
#endif
#define PATTERN_CNTRL_REG 82<<11
#define PATTERN_LIMITS_AREG 83<<11
#define PATTERN_CNTRL_REG 82 << MEM_MAP_SHIFT
#define PATTERN_LIMITS_AREG 83 << MEM_MAP_SHIFT
#define PATTERN_LOOP0_AREG 84<<11
#define PATTERN_N_LOOP0_REG 85<<11
#define PATTERN_LOOP0_AREG 84 << MEM_MAP_SHIFT
#define PATTERN_N_LOOP0_REG 85 << MEM_MAP_SHIFT
#define PATTERN_LOOP1_AREG 86<<11
#define PATTERN_N_LOOP1_REG 87<<11
#define PATTERN_LOOP1_AREG 86 << MEM_MAP_SHIFT
#define PATTERN_N_LOOP1_REG 87 << MEM_MAP_SHIFT
#define PATTERN_LOOP2_AREG 88<<11
#define PATTERN_N_LOOP2_REG 89<<11
#define PATTERN_LOOP2_AREG 88 << MEM_MAP_SHIFT
#define PATTERN_N_LOOP2_REG 89 << MEM_MAP_SHIFT
#define PATTERN_WAIT0_AREG 90<<11
#define PATTERN_WAIT1_AREG 91<<11
#define PATTERN_WAIT2_AREG 92<<11
#define PATTERN_WAIT0_AREG 90 << MEM_MAP_SHIFT
#define PATTERN_WAIT1_AREG 91 << MEM_MAP_SHIFT
#define PATTERN_WAIT2_AREG 92 << MEM_MAP_SHIFT
//#define DAQ_REG 93<<11 //unused
#define NSAMPLES_REG 93<<11
//#define DAQ_REG 93 << MEM_MAP_SHIFT //unused
#define NSAMPLES_REG 93 << MEM_MAP_SHIFT
#define HV_REG 95<<11
#define HV_REG 95 << MEM_MAP_SHIFT
#define PATTERN_IOCTRL_REG_LSB 108<<11
#define PATTERN_IOCTRL_REG_MSB 109<<11
#define PATTERN_IOCTRL_REG_LSB 108 << MEM_MAP_SHIFT
#define PATTERN_IOCTRL_REG_MSB 109 << MEM_MAP_SHIFT
#define PATTERN_IOCLKCTRL_REG_LSB 110<<11
#define PATTERN_IOCLKCTRL_REG_MSB 111<<11
#define PATTERN_IN_REG_LSB 112<<11
#define PATTERN_IN_REG_MSB 113<<11
#define PATTERN_WAIT0_TIME_REG_LSB 114<<11
#define PATTERN_WAIT0_TIME_REG_MSB 115<<11
#define PATTERN_WAIT1_TIME_REG_LSB 116<<11
#define PATTERN_WAIT1_TIME_REG_MSB 117<<11
#define PATTERN_WAIT2_TIME_REG_LSB 118<<11
#define PATTERN_WAIT2_TIME_REG_MSB 119<<11
#define PATTERN_IOCLKCTRL_REG_LSB 110 << MEM_MAP_SHIFT
#define PATTERN_IOCLKCTRL_REG_MSB 111 << MEM_MAP_SHIFT
#define PATTERN_IN_REG_LSB 112 << MEM_MAP_SHIFT
#define PATTERN_IN_REG_MSB 113 << MEM_MAP_SHIFT
#define PATTERN_WAIT0_TIME_REG_LSB 114 << MEM_MAP_SHIFT
#define PATTERN_WAIT0_TIME_REG_MSB 115 << MEM_MAP_SHIFT
#define PATTERN_WAIT1_TIME_REG_LSB 116 << MEM_MAP_SHIFT
#define PATTERN_WAIT1_TIME_REG_MSB 117 << MEM_MAP_SHIFT
#define PATTERN_WAIT2_TIME_REG_LSB 118 << MEM_MAP_SHIFT
#define PATTERN_WAIT2_TIME_REG_MSB 119 << MEM_MAP_SHIFT
//#define DAC_REG_OFF 120
//#define DAC_0_1_VAL_REG 120<<11
//#define DAC_2_3_VAL_REG 121<<11
//#define DAC_4_5_VAL_REG 122<<11
//#define DAC_6_7_VAL_REG 123<<11
//#define DAC_8_9_VAL_REG 124<<11
//#define DAC_10_11_VAL_REG 125<<11
//#define DAC_12_13_VAL_REG 126<<11
//#define DAC_14_15_VAL_REG 127<<11
#define DAC_VAL_REG 121<<11
#define DAC_NUM_REG 122<<11
#define DAC_VAL_OUT_REG 42<<11
#define ADC_LATCH_DISABLE_REG 120<<11
//#define DAC_0_1_VAL_REG 120 << MEM_MAP_SHIFT
//#define DAC_2_3_VAL_REG 121 << MEM_MAP_SHIFT
//#define DAC_4_5_VAL_REG 122 << MEM_MAP_SHIFT
//#define DAC_6_7_VAL_REG 123 << MEM_MAP_SHIFT
//#define DAC_8_9_VAL_REG 124 << MEM_MAP_SHIFT
//#define DAC_10_11_VAL_REG 125 << MEM_MAP_SHIFT
//#define DAC_12_13_VAL_REG 126 << MEM_MAP_SHIFT
//#define DAC_14_15_VAL_REG 127 << MEM_MAP_SHIFT
#define DAC_VAL_REG 121 << MEM_MAP_SHIFT
#define DAC_NUM_REG 122 << MEM_MAP_SHIFT
#define DAC_VAL_OUT_REG 42 << MEM_MAP_SHIFT
#define ADC_LATCH_DISABLE_REG 120 << MEM_MAP_SHIFT
@ -241,27 +241,27 @@
/* registers defined in FPGA */
#define GAIN_REG 0
//#define FLOW_CONTROL_REG 0x11<<11
//#define FLOW_STATUS_REG 0x12<<11
//#define FRAME_REG 0x13<<11
//#define FLOW_CONTROL_REG 0x11 << MEM_MAP_SHIFT
//#define FLOW_STATUS_REG 0x12 << MEM_MAP_SHIFT
//#define FRAME_REG 0x13 << MEM_MAP_SHIFT
#define MULTI_PURPOSE_REG 0
//#define TIME_FROM_START_REG 0x16<<11
//#define TIME_FROM_START_REG 0x16 << MEM_MAP_SHIFT
#define ROI_REG 0 // 0x35<<11
#define OVERSAMPLING_REG 0 // 0x36<<11
#define MOENCH_CNTR_REG 0 // 0x31<<11
#define MOENCH_CNTR_OUT_REG 0 // 0x33<<11
#define MOENCH_CNTR_CONF_REG 0 // 0x32<<11
#define ROI_REG 0 // 0x35 << MEM_MAP_SHIFT
#define OVERSAMPLING_REG 0 // 0x36 << MEM_MAP_SHIFT
#define MOENCH_CNTR_REG 0 // 0x31 << MEM_MAP_SHIFT
#define MOENCH_CNTR_OUT_REG 0 // 0x33 << MEM_MAP_SHIFT
#define MOENCH_CNTR_CONF_REG 0 // 0x32 << MEM_MAP_SHIFT
//image
#define DARK_IMAGE_REG 0 // 0x81<<11
#define GAIN_IMAGE_REG 0 // 0x82<<11
#define DARK_IMAGE_REG 0 // 0x81 << MEM_MAP_SHIFT
#define GAIN_IMAGE_REG 0 // 0x82 << MEM_MAP_SHIFT
//counter block memory
#define COUNTER_MEMORY_REG 0 // 0x85<<11
#define COUNTER_MEMORY_REG 0 // 0x85 << MEM_MAP_SHIFT
//not used

7
slsDetectorSoftware/jctbDetectorServer/server_funcs.c Executable file → Normal file
View File

@ -7,8 +7,9 @@
#include "slow_adc.h"
#include "registers_m.h"
#include "gitInfoMoench.h"
#include "blackfin.h"
#define FIFO_DATA_REG_OFF 0x50<<11
#define FIFO_DATA_REG_OFF 0x50 << MEM_MAP_SHIFT
// Global variables
@ -866,7 +867,7 @@ int write_register(int file_des) {
if(ret!=FAIL){
address=(addr<<11);
address=(addr << MEM_MAP_SHIFT);
if((address==FIFO_DATA_REG_OFF)||(address==CONTROL_REG))
ret = bus_w16(address,val);
else
@ -932,7 +933,7 @@ int read_register(int file_des) {
//#endif
if(ret!=FAIL){
address=(addr<<11);
address=(addr << MEM_MAP_SHIFT);
if((address==FIFO_DATA_REG_OFF)||(address==CONTROL_REG))
retval=bus_r16(address);
else

1
slsDetectorSoftware/jctbDetectorServer/slow_adc.c
View File

@ -1,6 +1,7 @@
#include "firmware_funcs.h"
#include "registers_m.h"
#include "server_defs.h"
#include "blackfin.h"
int prepareSlowADCSeq() {

4
slsDetectorSoftware/mythenDetectorServer/Makefile
View File

@ -13,7 +13,7 @@ INSTMODE= 0777
SRCS= server.c server_funcs.c communication_funcs.c firmware_funcs.c mcb_funcs.c trimming_funcs.c sharedmemory.c
OBJS= $(SRCS:%.c=%.o)
VFLAGS=
VFLAGS=
#-DVERBOSE
#-DVERYVERBOSE
CFLAGS+= -Wall -DC_ONLY -DMCB_FUNCS -DDACS_INT $(VFLAGS)
@ -32,7 +32,7 @@ versioning:
$(PROGS): $(OBJS)
echo $(OBJS)
$(CC) $(LDFLAGS) $^ $(LDLIBS) $(CFLAGS) -o $@
$(CC) $(LDFLAGS) $^ $(LDLIBS) $(CFLAGS) -o $@ -DVERBOSE
install: $(PROGS)
$(INSTALL) -d $(INSTDIR)

17
slsDetectorSoftware/mythenDetectorServer/firmware_funcs.c
View File

@ -17,6 +17,7 @@
#include <sys/stat.h>
#include <stdlib.h>
//#define VERBOSE
//for memory mapping
u_int64_t CSP0BASE;
@ -702,9 +703,9 @@ int setNMod(int n) {
shiftfifo=SHIFTFIFO;
#ifdef VERBOSE
//#ifdef VERBOSE
printf("SetNMod called arg %d -- dr %d shiftfifo %d\n",n,dynamicRange,shiftfifo);
#endif
//#endif
if (n>=0 && n<=ntot) {
nModX=n;
@ -713,12 +714,16 @@ int setNMod(int n) {
reg=bus_r(FIFO_COUNTR_REG_OFF+(ififo<<shiftfifo));
if (ififo<n*NCHIP) {
if (reg&FIFO_DISABLED_BIT) {
bus_w(FIFO_CNTRL_REG_OFF+(ififo<<shiftfifo), FIFO_DISABLE_TOGGLE_BIT);
#ifdef VERBOSE
if (bus_r(FIFO_COUNTR_REG_OFF+(ififo<<shiftfifo))&FIFO_DISABLED_BIT) {
// if (bus_r(FIFO_COUNTR_REG_OFF+(ififo<<shiftfifo))&FIFO_DISABLED_BIT) {
printf("Fifo %d is %x (nm %d nc %d addr %08x)",ififo,reg, (reg&FIFO_NM_MASK)>>FIFO_NM_OFF, (reg&FIFO_NC_MASK)>>FIFO_NC_OFF, FIFO_COUNTR_REG_OFF+(ififo<<shiftfifo));
printf(" enabling %08x\n",bus_r(FIFO_COUNTR_REG_OFF+(ififo<<shiftfifo)));
}
// }
#endif
}
//#ifdef VERBOSE
@ -729,10 +734,10 @@ int setNMod(int n) {
if ((reg&FIFO_ENABLED_BIT)) {
bus_w(FIFO_CNTRL_REG_OFF+(ififo<<shiftfifo), FIFO_DISABLE_TOGGLE_BIT);
#ifdef VERBOSE
if ((bus_r(FIFO_COUNTR_REG_OFF+(ififo<<shiftfifo))&FIFO_ENABLED_BIT)) {
// if ((bus_r(FIFO_COUNTR_REG_OFF+(ififo<<shiftfifo))&FIFO_ENABLED_BIT)) {
printf("Fifo %d is %x (nm %d nc %d addr %08x)",ififo,reg, (reg&FIFO_NM_MASK)>>FIFO_NM_OFF, (reg&FIFO_NC_MASK)>>FIFO_NC_OFF, FIFO_COUNTR_REG_OFF+(ififo<<shiftfifo));
printf(" disabling %08x\n",bus_r(FIFO_COUNTR_REG_OFF+(ififo<<shiftfifo)));
}
// }
#endif
}
//#ifdef VERBOSE

16
slsDetectorSoftware/mythenDetectorServer/gitInfo.txt
View File

@ -1,9 +1,9 @@
Path: slsDetectorsPackage/slsDetectorSoftware/mythenDetectorServer
URL: origin git@git.psi.ch:sls_detectors_software/sls_detector_software.git/mythenDetectorServer
Repository Root: origin git@git.psi.ch:sls_detectors_software/sls_detector_software.git
Repsitory UUID: 8aceb5d4b0ca6bd95a11b53e7a799b463b92d51b
Revision: 106
Branch: developer
Last Changed Author: Dhanya_Maliakal
Last Changed Rev: 334
Last Changed Date: 2016-08-12 11:08:03 +0200
URL:
Repository Root:
Repsitory UUID:
Revision: 0
Branch:
Last Changed Author: _
Last Changed Rev: 0
Last Changed Date: 2018-01-30 10:42:45.000000000 +0100 ./Makefile

12
slsDetectorSoftware/mythenDetectorServer/gitInfoMythen.h
View File

@ -1,6 +1,6 @@
#define GITURL "git@git.psi.ch:sls_detectors_software/sls_detector_software.git/mythenDetectorServer"
#define GITREPUUID "8aceb5d4b0ca6bd95a11b53e7a799b463b92d51b"
#define GITAUTH "Dhanya_Maliakal"
#define GITREV 0x334
#define GITDATE 0x20160812
#define GITBRANCH "blabla"
#define GITURL "URL:"
#define GITREPUUID "UUID:"
#define GITAUTH "_"
#define GITREV 0x0
#define GITDATE 0x20180130
#define GITBRANCH "Branch:"

BIN
slsDetectorSoftware/mythenDetectorServer/mythenDetectorServer
View File

Binary file not shown.

2
slsDetectorSoftware/slsDetector/gitInfoLib.h
View File

@ -1,6 +1,8 @@
#define GITURL "git@github.com:slsdetectorgroup/slsDetectorPackage.git"
#define GITREPUUID "b8bdbf4da61f95b88893b02ddabc2491b16fa10f"
#define GITAUTH "Dhanya_Thattil"
#define GITREV 0x3746
#define GITDATE 0x20180327
#define GITBRANCH "developer"