mirror of
https://github.com/slsdetectorgroup/slsDetectorPackage.git
synced 2025-04-28 01:00:02 +02:00
[CTB] - Modified memory map address shift for the interface between FPGA and Blackfin SOM. Shift has to be set to 1 since the basic AMC data transfers is 8-bit and not 16-bit.
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@ -3,8 +3,10 @@
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#define CSP0 0x20200000
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#define MEM_SIZE 0x100000
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#define MEM_MAP_SHIFT 1
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#include <sys/types.h>
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#include <sys/types.h>
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int mapCSP0(void);
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u_int16_t bus_r16(u_int32_t offset);
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@ -1,9 +1,9 @@
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Path: slsDetectorsPackage/slsDetectorSoftware/jctbDetectorServer
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URL: origin git@github.com:slsdetectorgroup/slsDetectorPackage.git
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Repository Root: origin git@github.com:slsdetectorgroup/slsDetectorPackage.git
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Repsitory UUID: 807189a4923dc257d812c9974f1a4a4d143c2f70
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Revision: 23
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Repsitory UUID: c35203ebfb35ba605eaff601ce46e4d29c1f5690
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Revision: 24
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Branch: developer
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Last Changed Author: Anna_Bergamaschi
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Last Changed Rev: 3734
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Last Changed Date: 2018-04-17 12:35:10.000000002 +0200 ./firmware_funcs.c
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Last Changed Rev: 3761
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Last Changed Date: 2018-04-27 14:46:10.176661554 +0200 ./server_funcs.h
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@ -1,6 +1,6 @@
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#define GITURL "git@github.com:slsdetectorgroup/slsDetectorPackage.git"
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#define GITREPUUID "807189a4923dc257d812c9974f1a4a4d143c2f70"
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#define GITREPUUID "c35203ebfb35ba605eaff601ce46e4d29c1f5690"
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#define GITAUTH "Anna_Bergamaschi"
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#define GITREV 0x3734
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#define GITDATE 0x20180417
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#define GITREV 0x3761
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#define GITDATE 0x20180427
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#define GITBRANCH "developer"
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Binary file not shown.
282
slsDetectorSoftware/jctbDetectorServer/registers_m.h
Executable file → Normal file
282
slsDetectorSoftware/jctbDetectorServer/registers_m.h
Executable file → Normal file
@ -20,7 +20,7 @@
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#define FPGA_INIT_ADDR 0xb0000000
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//#ifdef JUNGFRAU_DHANYA
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#define POWER_ON_REG 0x5e<<11
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#define POWER_ON_REG 0x5e << MEM_MAP_SHIFT
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// Pwr_I2C_SDA <= PowerReg_s(1) when PowerReg_s(3)='1' else 'Z';
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// Pwr_I2C_SCL <= PowerReg_s(0) when PowerReg_s(2)='1' else 'Z';
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@ -29,71 +29,71 @@
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#define PWR_I2C_SCL_EN_BIT 2
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#define PWR_I2C_SDA_EN_BIT 3
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#define POWER_STATUS_REG 41<<11
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#define POWER_STATUS_REG 41 << MEM_MAP_SHIFT
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#define ADCREG1 0x08
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#define ADCREG2 0x14//20
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#define ADCREG3 0x4
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#define ADCREG4 0x5
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#define ADCREG_VREFS 24
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#define DBIT_PIPELINE_REG 89<<11 //0x59 same PATTERN_N_LOOP2_REG
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#define MEM_MACHINE_FIFOS_REG 79<<11 //from gotthard
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#define CONFGAIN_REG 93<<11 //from gotthard
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#define ADC_PIPELINE_REG 66<<11 //0x42 same as ADC_OFFSET_REG
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#define DBIT_PIPELINE_REG 89 << MEM_MAP_SHIFT //0x59 same PATTERN_N_LOOP2_REG
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#define MEM_MACHINE_FIFOS_REG 79 << MEM_MAP_SHIFT //from gotthard
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#define CONFGAIN_REG 93 << MEM_MAP_SHIFT //from gotthard
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#define ADC_PIPELINE_REG 66 << MEM_MAP_SHIFT //0x42 same as ADC_OFFSET_REG
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//#endif
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//#define ADC_OFFSET_REG 93<<11 //same as DAQ_REG
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#define ADC_INVERSION_REG 67<<11
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//#define ADC_OFFSET_REG 93 << MEM_MAP_SHIFT //same as DAQ_REG
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#define ADC_INVERSION_REG 67 << MEM_MAP_SHIFT
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#define DAC_REG 64<<11//0x17<<11// control the dacs
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#define DAC_REG 64 << MEM_MAP_SHIFT//0x17 << MEM_MAP_SHIFT// control the dacs
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//ADC
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#define ADC_WRITE_REG 65<<11//0x18<<11
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//#define ADC_SYNC_REG 66<<11//0x19<<11
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//#define HV_REG 67<<11//0x20<<11
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#define ADC_WRITE_REG 65 << MEM_MAP_SHIFT//0x18 << MEM_MAP_SHIFT
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//#define ADC_SYNC_REG 66 << MEM_MAP_SHIFT//0x19 << MEM_MAP_SHIFT
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//#define HV_REG 67 << MEM_MAP_SHIFT//0x20 << MEM_MAP_SHIFT
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//#define MUTIME_REG 0x1a<<11
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//#define MUTIME_REG 0x1a << MEM_MAP_SHIFT
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//temperature
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#define TEMP_IN_REG 0x1b<<11
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#define TEMP_OUT_REG 0x1c<<11
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#define TEMP_IN_REG 0x1b << MEM_MAP_SHIFT
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#define TEMP_OUT_REG 0x1c << MEM_MAP_SHIFT
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//configure MAC
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#define TSE_CONF_REG 0x1d<<11
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#define ENET_CONF_REG 0x1e<<11
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//#define WRTSE_SHAD_REG 0x1f<<11
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#define TSE_CONF_REG 0x1d << MEM_MAP_SHIFT
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#define ENET_CONF_REG 0x1e << MEM_MAP_SHIFT
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//#define WRTSE_SHAD_REG 0x1f << MEM_MAP_SHIFT
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//HV
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#define DUMMY_REG 68<<11//0x21<<11
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#define FPGA_VERSION_REG 0<<11 //0x22<<11
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#define PCB_REV_REG 0<<11
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#define FIX_PATT_REG 1<<11 //0x23<<11
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#define CONTROL_REG 79<<11//0x24<<11
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#define STATUS_REG 2<<11 //0x25<<11
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#define CONFIG_REG 77<<11//0x26<<11
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#define EXT_SIGNAL_REG 78<<11// 0x27<<11
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//#define FPGA_SVN_REG 0x29<<11
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#define DUMMY_REG 68 << MEM_MAP_SHIFT//0x21 << MEM_MAP_SHIFT
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#define FPGA_VERSION_REG 0 << MEM_MAP_SHIFT //0x22 << MEM_MAP_SHIFT
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#define PCB_REV_REG 0 << MEM_MAP_SHIFT
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#define FIX_PATT_REG 1 << MEM_MAP_SHIFT //0x23 << MEM_MAP_SHIFT
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#define CONTROL_REG 79 << MEM_MAP_SHIFT//0x24 << MEM_MAP_SHIFT
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#define STATUS_REG 2 << MEM_MAP_SHIFT //0x25 << MEM_MAP_SHIFT
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#define CONFIG_REG 77 << MEM_MAP_SHIFT//0x26 << MEM_MAP_SHIFT
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#define EXT_SIGNAL_REG 78 << MEM_MAP_SHIFT// 0x27 << MEM_MAP_SHIFT
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//#define FPGA_SVN_REG 0x29 << MEM_MAP_SHIFT
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#define CHIP_OF_INTRST_REG 0x2A<<11
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#define CHIP_OF_INTRST_REG 0x2A << MEM_MAP_SHIFT
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//FIFO
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#define LOOK_AT_ME_REG 3<<11 //0x28<<11
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#define SYSTEM_STATUS_REG 4<<11
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#define LOOK_AT_ME_REG 3 << MEM_MAP_SHIFT //0x28 << MEM_MAP_SHIFT
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#define SYSTEM_STATUS_REG 4 << MEM_MAP_SHIFT
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#define FIFO_DATA_REG 6<<11
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#define FIFO_STATUS_REG 7<<11
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#define FIFO_DATA_REG 6 << MEM_MAP_SHIFT
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#define FIFO_STATUS_REG 7 << MEM_MAP_SHIFT
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// constant FifoDigitalInReg_c : integer := 60;
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#define FIFO_DIGITAL_DATA_LSB_REG 60<<11
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#define FIFO_DIGITAL_DATA_MSB_REG 61<<11
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#define FIFO_DIGITAL_DATA_LSB_REG 60 << MEM_MAP_SHIFT
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#define FIFO_DIGITAL_DATA_MSB_REG 61 << MEM_MAP_SHIFT
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#define FIFO_DATA_REG_OFF 0x50<<11 ///////
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#define FIFO_DATA_REG_OFF 0x50 << MEM_MAP_SHIFT ///////
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//to read back dac registers
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//#define MOD_DACS1_REG 0x65<<11
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//#define MOD_DACS2_REG 0x66<<11
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//#define MOD_DACS3_REG 0x67<<11
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//#define MOD_DACS1_REG 0x65 << MEM_MAP_SHIFT
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//#define MOD_DACS2_REG 0x66 << MEM_MAP_SHIFT
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//#define MOD_DACS3_REG 0x67 << MEM_MAP_SHIFT
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//user entered
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@ -102,135 +102,135 @@
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#define GET_ACTUAL_TIME_LSB_REG 16<<11
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#define GET_ACTUAL_TIME_MSB_REG 17<<11
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#define GET_ACTUAL_TIME_LSB_REG 16 << MEM_MAP_SHIFT
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#define GET_ACTUAL_TIME_MSB_REG 17 << MEM_MAP_SHIFT
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#define GET_MEASUREMENT_TIME_LSB_REG 38<<11
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#define GET_MEASUREMENT_TIME_MSB_REG 39<<11
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#define GET_MEASUREMENT_TIME_LSB_REG 38 << MEM_MAP_SHIFT
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#define GET_MEASUREMENT_TIME_MSB_REG 39 << MEM_MAP_SHIFT
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#define SET_DELAY_LSB_REG 96<<11 //0x68<<11
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#define SET_DELAY_MSB_REG 97<<11 //0x69<<11
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#define GET_DELAY_LSB_REG 18<<11//0x6a<<11
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#define GET_DELAY_MSB_REG 19<<11//0x6b<<11
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#define SET_DELAY_LSB_REG 96 << MEM_MAP_SHIFT //0x68 << MEM_MAP_SHIFT
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#define SET_DELAY_MSB_REG 97 << MEM_MAP_SHIFT //0x69 << MEM_MAP_SHIFT
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#define GET_DELAY_LSB_REG 18 << MEM_MAP_SHIFT//0x6a << MEM_MAP_SHIFT
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#define GET_DELAY_MSB_REG 19 << MEM_MAP_SHIFT//0x6b << MEM_MAP_SHIFT
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#define SET_CYCLES_LSB_REG 98<<11//0x6c<<11
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#define SET_CYCLES_MSB_REG 99<<11//0x6d<<11
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#define GET_CYCLES_LSB_REG 20<<11//0x6e<<11
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#define GET_CYCLES_MSB_REG 21<<11//0x6f<<11
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#define SET_CYCLES_LSB_REG 98 << MEM_MAP_SHIFT//0x6c << MEM_MAP_SHIFT
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#define SET_CYCLES_MSB_REG 99 << MEM_MAP_SHIFT//0x6d << MEM_MAP_SHIFT
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#define GET_CYCLES_LSB_REG 20 << MEM_MAP_SHIFT//0x6e << MEM_MAP_SHIFT
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#define GET_CYCLES_MSB_REG 21 << MEM_MAP_SHIFT//0x6f << MEM_MAP_SHIFT
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#define SET_FRAMES_LSB_REG 100<<11//0x70<<11
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#define SET_FRAMES_MSB_REG 101<<11//0x71<<11
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#define GET_FRAMES_LSB_REG 22<<11//0x72<<11
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#define GET_FRAMES_MSB_REG 23<<11//0x73<<11
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#define SET_FRAMES_LSB_REG 100 << MEM_MAP_SHIFT//0x70 << MEM_MAP_SHIFT
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#define SET_FRAMES_MSB_REG 101 << MEM_MAP_SHIFT//0x71 << MEM_MAP_SHIFT
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#define GET_FRAMES_LSB_REG 22 << MEM_MAP_SHIFT//0x72 << MEM_MAP_SHIFT
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#define GET_FRAMES_MSB_REG 23 << MEM_MAP_SHIFT//0x73 << MEM_MAP_SHIFT
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#define SET_PERIOD_LSB_REG 102<<11//0x74<<11
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#define SET_PERIOD_MSB_REG 103<<11//0x75<<11
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#define GET_PERIOD_LSB_REG 24<<11//0x76<<11
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#define GET_PERIOD_MSB_REG 25<<11//0x77<<11
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#define SET_PERIOD_LSB_REG 102 << MEM_MAP_SHIFT//0x74 << MEM_MAP_SHIFT
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#define SET_PERIOD_MSB_REG 103 << MEM_MAP_SHIFT//0x75 << MEM_MAP_SHIFT
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#define GET_PERIOD_LSB_REG 24 << MEM_MAP_SHIFT//0x76 << MEM_MAP_SHIFT
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#define GET_PERIOD_MSB_REG 25 << MEM_MAP_SHIFT//0x77 << MEM_MAP_SHIFT
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//#define PATTERN_WAIT0_TIME_REG_LSB 114<<11
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//#define PATTERN_WAIT0_TIME_REG_MSB 115<<11
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#define SET_EXPTIME_LSB_REG 114<<11//0x78<<11
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#define SET_EXPTIME_MSB_REG 115<<11//0x79<<11
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#define GET_EXPTIME_LSB_REG 26<<11//0x7a<<11
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#define GET_EXPTIME_MSB_REG 27<<11//0x7b<<11
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//#define PATTERN_WAIT0_TIME_REG_LSB 114 << MEM_MAP_SHIFT
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//#define PATTERN_WAIT0_TIME_REG_MSB 115 << MEM_MAP_SHIFT
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#define SET_EXPTIME_LSB_REG 114 << MEM_MAP_SHIFT//0x78 << MEM_MAP_SHIFT
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#define SET_EXPTIME_MSB_REG 115 << MEM_MAP_SHIFT//0x79 << MEM_MAP_SHIFT
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#define GET_EXPTIME_LSB_REG 26 << MEM_MAP_SHIFT//0x7a << MEM_MAP_SHIFT
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#define GET_EXPTIME_MSB_REG 27 << MEM_MAP_SHIFT//0x7b << MEM_MAP_SHIFT
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#define SET_GATES_LSB_REG 106<<11//0x7c<<11
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#define SET_GATES_MSB_REG 107<<11//0x7d<<11
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#define GET_GATES_LSB_REG 28<<11//0x7e<<11
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#define GET_GATES_MSB_REG 29<<11//0x7f<<11
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#define SET_GATES_LSB_REG 106 << MEM_MAP_SHIFT//0x7c << MEM_MAP_SHIFT
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#define SET_GATES_MSB_REG 107 << MEM_MAP_SHIFT//0x7d << MEM_MAP_SHIFT
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#define GET_GATES_LSB_REG 28 << MEM_MAP_SHIFT//0x7e << MEM_MAP_SHIFT
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#define GET_GATES_MSB_REG 29 << MEM_MAP_SHIFT//0x7f << MEM_MAP_SHIFT
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#define DATA_IN_LSB_REG 30<<11
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#define DATA_IN_MSB_REG 31<<11
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#define DATA_IN_LSB_REG 30 << MEM_MAP_SHIFT
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#define DATA_IN_MSB_REG 31 << MEM_MAP_SHIFT
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#define PATTERN_OUT_LSB_REG 32<<11
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#define PATTERN_OUT_MSB_REG 33<<11
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#define PATTERN_OUT_LSB_REG 32 << MEM_MAP_SHIFT
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#define PATTERN_OUT_MSB_REG 33 << MEM_MAP_SHIFT
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#define FRAMES_FROM_START_LSB_REG 34<<11
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#define FRAMES_FROM_START_MSB_REG 35<<11
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#define FRAMES_FROM_START_LSB_REG 34 << MEM_MAP_SHIFT
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#define FRAMES_FROM_START_MSB_REG 35 << MEM_MAP_SHIFT
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#define FRAMES_FROM_START_PG_LSB_REG 36<<11
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#define FRAMES_FROM_START_PG_MSB_REG 37<<11
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#define FRAMES_FROM_START_PG_LSB_REG 36 << MEM_MAP_SHIFT
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#define FRAMES_FROM_START_PG_MSB_REG 37 << MEM_MAP_SHIFT
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#define SLOW_ADC_REG 43<<11
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#define SLOW_ADC_REG 43 << MEM_MAP_SHIFT
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#define PLL_PARAM_REG 80<<11//0x37<<11
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#define PLL_PARAM_OUT_REG 5<<11 //0x38<<11
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#define PLL_CNTRL_REG 81<<11//0x34<<11
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#define PLL_PARAM_REG 80 << MEM_MAP_SHIFT//0x37 << MEM_MAP_SHIFT
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#define PLL_PARAM_OUT_REG 5 << MEM_MAP_SHIFT //0x38 << MEM_MAP_SHIFT
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#define PLL_CNTRL_REG 81 << MEM_MAP_SHIFT//0x34 << MEM_MAP_SHIFT
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#ifdef NEW_GBE_INTERFACE
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#define GBE_PARAM_OUT_REG 40<<11
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#define GBE_PARAM_REG 69<<11
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#define GBE_CNTRL_REG 70<<11
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#define GBE_PARAM_OUT_REG 40 << MEM_MAP_SHIFT
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#define GBE_PARAM_REG 69 << MEM_MAP_SHIFT
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#define GBE_CNTRL_REG 70 << MEM_MAP_SHIFT
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#else
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#define RX_UDP_AREG 69<<11 //rx_udpip_AReg_c : integer:= 69; *\/
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#define UDPPORTS_AREG 70<<11// udpports_AReg_c : integer:= 70; *\/
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#define RX_UDPMACL_AREG 71<<11//rx_udpmacL_AReg_c : integer:= 71; *\/
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#define RX_UDPMACH_AREG 72<<11//rx_udpmacH_AReg_c : integer:= 72; *\/
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#define DETECTORMACL_AREG 73<<11//detectormacL_AReg_c : integer:= 73; *\/
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#define DETECTORMACH_AREG 74<<11//detectormacH_AReg_c : integer:= 74; *\/
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#define DETECTORIP_AREG 75<<11//detectorip_AReg_c : integer:= 75; *\/
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#define IPCHKSUM_AREG 76<<11//ipchksum_AReg_c : integer:= 76; *\/ */
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#define RX_UDP_AREG 69 << MEM_MAP_SHIFT //rx_udpip_AReg_c : integer:= 69; *\/
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#define UDPPORTS_AREG 70 << MEM_MAP_SHIFT// udpports_AReg_c : integer:= 70; *\/
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#define RX_UDPMACL_AREG 71 << MEM_MAP_SHIFT//rx_udpmacL_AReg_c : integer:= 71; *\/
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#define RX_UDPMACH_AREG 72 << MEM_MAP_SHIFT//rx_udpmacH_AReg_c : integer:= 72; *\/
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#define DETECTORMACL_AREG 73 << MEM_MAP_SHIFT//detectormacL_AReg_c : integer:= 73; *\/
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#define DETECTORMACH_AREG 74 << MEM_MAP_SHIFT//detectormacH_AReg_c : integer:= 74; *\/
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#define DETECTORIP_AREG 75 << MEM_MAP_SHIFT//detectorip_AReg_c : integer:= 75; *\/
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#define IPCHKSUM_AREG 76 << MEM_MAP_SHIFT//ipchksum_AReg_c : integer:= 76; *\/ */
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#endif
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#define PATTERN_CNTRL_REG 82<<11
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#define PATTERN_LIMITS_AREG 83<<11
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#define PATTERN_CNTRL_REG 82 << MEM_MAP_SHIFT
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#define PATTERN_LIMITS_AREG 83 << MEM_MAP_SHIFT
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#define PATTERN_LOOP0_AREG 84<<11
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#define PATTERN_N_LOOP0_REG 85<<11
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#define PATTERN_LOOP0_AREG 84 << MEM_MAP_SHIFT
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#define PATTERN_N_LOOP0_REG 85 << MEM_MAP_SHIFT
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#define PATTERN_LOOP1_AREG 86<<11
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#define PATTERN_N_LOOP1_REG 87<<11
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#define PATTERN_LOOP1_AREG 86 << MEM_MAP_SHIFT
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#define PATTERN_N_LOOP1_REG 87 << MEM_MAP_SHIFT
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#define PATTERN_LOOP2_AREG 88<<11
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#define PATTERN_N_LOOP2_REG 89<<11
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#define PATTERN_LOOP2_AREG 88 << MEM_MAP_SHIFT
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#define PATTERN_N_LOOP2_REG 89 << MEM_MAP_SHIFT
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#define PATTERN_WAIT0_AREG 90<<11
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#define PATTERN_WAIT1_AREG 91<<11
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#define PATTERN_WAIT2_AREG 92<<11
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#define PATTERN_WAIT0_AREG 90 << MEM_MAP_SHIFT
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#define PATTERN_WAIT1_AREG 91 << MEM_MAP_SHIFT
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#define PATTERN_WAIT2_AREG 92 << MEM_MAP_SHIFT
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//#define DAQ_REG 93<<11 //unused
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#define NSAMPLES_REG 93<<11
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//#define DAQ_REG 93 << MEM_MAP_SHIFT //unused
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#define NSAMPLES_REG 93 << MEM_MAP_SHIFT
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#define HV_REG 95<<11
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#define HV_REG 95 << MEM_MAP_SHIFT
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#define PATTERN_IOCTRL_REG_LSB 108<<11
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#define PATTERN_IOCTRL_REG_MSB 109<<11
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#define PATTERN_IOCTRL_REG_LSB 108 << MEM_MAP_SHIFT
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#define PATTERN_IOCTRL_REG_MSB 109 << MEM_MAP_SHIFT
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#define PATTERN_IOCLKCTRL_REG_LSB 110<<11
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#define PATTERN_IOCLKCTRL_REG_MSB 111<<11
|
||||
#define PATTERN_IN_REG_LSB 112<<11
|
||||
#define PATTERN_IN_REG_MSB 113<<11
|
||||
#define PATTERN_WAIT0_TIME_REG_LSB 114<<11
|
||||
#define PATTERN_WAIT0_TIME_REG_MSB 115<<11
|
||||
#define PATTERN_WAIT1_TIME_REG_LSB 116<<11
|
||||
#define PATTERN_WAIT1_TIME_REG_MSB 117<<11
|
||||
#define PATTERN_WAIT2_TIME_REG_LSB 118<<11
|
||||
#define PATTERN_WAIT2_TIME_REG_MSB 119<<11
|
||||
#define PATTERN_IOCLKCTRL_REG_LSB 110 << MEM_MAP_SHIFT
|
||||
#define PATTERN_IOCLKCTRL_REG_MSB 111 << MEM_MAP_SHIFT
|
||||
#define PATTERN_IN_REG_LSB 112 << MEM_MAP_SHIFT
|
||||
#define PATTERN_IN_REG_MSB 113 << MEM_MAP_SHIFT
|
||||
#define PATTERN_WAIT0_TIME_REG_LSB 114 << MEM_MAP_SHIFT
|
||||
#define PATTERN_WAIT0_TIME_REG_MSB 115 << MEM_MAP_SHIFT
|
||||
#define PATTERN_WAIT1_TIME_REG_LSB 116 << MEM_MAP_SHIFT
|
||||
#define PATTERN_WAIT1_TIME_REG_MSB 117 << MEM_MAP_SHIFT
|
||||
#define PATTERN_WAIT2_TIME_REG_LSB 118 << MEM_MAP_SHIFT
|
||||
#define PATTERN_WAIT2_TIME_REG_MSB 119 << MEM_MAP_SHIFT
|
||||
|
||||
//#define DAC_REG_OFF 120
|
||||
//#define DAC_0_1_VAL_REG 120<<11
|
||||
//#define DAC_2_3_VAL_REG 121<<11
|
||||
//#define DAC_4_5_VAL_REG 122<<11
|
||||
//#define DAC_6_7_VAL_REG 123<<11
|
||||
//#define DAC_8_9_VAL_REG 124<<11
|
||||
//#define DAC_10_11_VAL_REG 125<<11
|
||||
//#define DAC_12_13_VAL_REG 126<<11
|
||||
//#define DAC_14_15_VAL_REG 127<<11
|
||||
#define DAC_VAL_REG 121<<11
|
||||
#define DAC_NUM_REG 122<<11
|
||||
#define DAC_VAL_OUT_REG 42<<11
|
||||
#define ADC_LATCH_DISABLE_REG 120<<11
|
||||
//#define DAC_0_1_VAL_REG 120 << MEM_MAP_SHIFT
|
||||
//#define DAC_2_3_VAL_REG 121 << MEM_MAP_SHIFT
|
||||
//#define DAC_4_5_VAL_REG 122 << MEM_MAP_SHIFT
|
||||
//#define DAC_6_7_VAL_REG 123 << MEM_MAP_SHIFT
|
||||
//#define DAC_8_9_VAL_REG 124 << MEM_MAP_SHIFT
|
||||
//#define DAC_10_11_VAL_REG 125 << MEM_MAP_SHIFT
|
||||
//#define DAC_12_13_VAL_REG 126 << MEM_MAP_SHIFT
|
||||
//#define DAC_14_15_VAL_REG 127 << MEM_MAP_SHIFT
|
||||
#define DAC_VAL_REG 121 << MEM_MAP_SHIFT
|
||||
#define DAC_NUM_REG 122 << MEM_MAP_SHIFT
|
||||
#define DAC_VAL_OUT_REG 42 << MEM_MAP_SHIFT
|
||||
#define ADC_LATCH_DISABLE_REG 120 << MEM_MAP_SHIFT
|
||||
|
||||
|
||||
|
||||
@ -241,27 +241,27 @@
|
||||
|
||||
/* registers defined in FPGA */
|
||||
#define GAIN_REG 0
|
||||
//#define FLOW_CONTROL_REG 0x11<<11
|
||||
//#define FLOW_STATUS_REG 0x12<<11
|
||||
//#define FRAME_REG 0x13<<11
|
||||
//#define FLOW_CONTROL_REG 0x11 << MEM_MAP_SHIFT
|
||||
//#define FLOW_STATUS_REG 0x12 << MEM_MAP_SHIFT
|
||||
//#define FRAME_REG 0x13 << MEM_MAP_SHIFT
|
||||
#define MULTI_PURPOSE_REG 0
|
||||
//#define TIME_FROM_START_REG 0x16<<11
|
||||
//#define TIME_FROM_START_REG 0x16 << MEM_MAP_SHIFT
|
||||
|
||||
|
||||
#define ROI_REG 0 // 0x35<<11
|
||||
#define OVERSAMPLING_REG 0 // 0x36<<11
|
||||
#define MOENCH_CNTR_REG 0 // 0x31<<11
|
||||
#define MOENCH_CNTR_OUT_REG 0 // 0x33<<11
|
||||
#define MOENCH_CNTR_CONF_REG 0 // 0x32<<11
|
||||
#define ROI_REG 0 // 0x35 << MEM_MAP_SHIFT
|
||||
#define OVERSAMPLING_REG 0 // 0x36 << MEM_MAP_SHIFT
|
||||
#define MOENCH_CNTR_REG 0 // 0x31 << MEM_MAP_SHIFT
|
||||
#define MOENCH_CNTR_OUT_REG 0 // 0x33 << MEM_MAP_SHIFT
|
||||
#define MOENCH_CNTR_CONF_REG 0 // 0x32 << MEM_MAP_SHIFT
|
||||
|
||||
|
||||
|
||||
//image
|
||||
#define DARK_IMAGE_REG 0 // 0x81<<11
|
||||
#define GAIN_IMAGE_REG 0 // 0x82<<11
|
||||
#define DARK_IMAGE_REG 0 // 0x81 << MEM_MAP_SHIFT
|
||||
#define GAIN_IMAGE_REG 0 // 0x82 << MEM_MAP_SHIFT
|
||||
|
||||
//counter block memory
|
||||
#define COUNTER_MEMORY_REG 0 // 0x85<<11
|
||||
#define COUNTER_MEMORY_REG 0 // 0x85 << MEM_MAP_SHIFT
|
||||
|
||||
|
||||
//not used
|
||||
|
||||
7
slsDetectorSoftware/jctbDetectorServer/server_funcs.c
Executable file → Normal file
7
slsDetectorSoftware/jctbDetectorServer/server_funcs.c
Executable file → Normal file
@ -7,8 +7,9 @@
|
||||
#include "slow_adc.h"
|
||||
#include "registers_m.h"
|
||||
#include "gitInfoMoench.h"
|
||||
#include "blackfin.h"
|
||||
|
||||
#define FIFO_DATA_REG_OFF 0x50<<11
|
||||
#define FIFO_DATA_REG_OFF 0x50 << MEM_MAP_SHIFT
|
||||
// Global variables
|
||||
|
||||
|
||||
@ -866,7 +867,7 @@ int write_register(int file_des) {
|
||||
|
||||
|
||||
if(ret!=FAIL){
|
||||
address=(addr<<11);
|
||||
address=(addr << MEM_MAP_SHIFT);
|
||||
if((address==FIFO_DATA_REG_OFF)||(address==CONTROL_REG))
|
||||
ret = bus_w16(address,val);
|
||||
else
|
||||
@ -932,7 +933,7 @@ int read_register(int file_des) {
|
||||
//#endif
|
||||
|
||||
if(ret!=FAIL){
|
||||
address=(addr<<11);
|
||||
address=(addr << MEM_MAP_SHIFT);
|
||||
if((address==FIFO_DATA_REG_OFF)||(address==CONTROL_REG))
|
||||
retval=bus_r16(address);
|
||||
else
|
||||
|
||||
@ -1,6 +1,7 @@
|
||||
#include "firmware_funcs.h"
|
||||
#include "registers_m.h"
|
||||
#include "server_defs.h"
|
||||
#include "blackfin.h"
|
||||
|
||||
int prepareSlowADCSeq() {
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user