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ctb server: sync clk get added

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This commit is contained in:
maliakal_d 2019-06-19 16:55:24 +02:00
parent 6c33f7de7b
commit 4b69c01357
5 changed files with 26 additions and 6 deletions
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BIN
slsDetectorServers/ctbDetectorServer/bin/ctbDetectorServer_developer
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2
slsDetectorServers/ctbDetectorServer/slsDetectorFunctionList.c
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@ -799,6 +799,8 @@ int getSpeed(enum speedVariable ind, int mode) {
return getFrequency(ADC_CLK);
case DBIT_CLOCK:
return getFrequency(DBIT_CLK);
case SYNC_CLOCK:
return getFrequency(SYNC_CLK);
case CLOCK_DIVIDER:
return getFrequency(RUN_CLK);
case ADC_PIPELINE:

3
slsDetectorServers/slsDetectorServer/slsDetectorServer_funcs.c
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@ -146,6 +146,7 @@ const char* getSpeedName(enum speedVariable ind) {
case DBIT_PIPELINE: return "dbit_pipeline";
case MAX_ADC_PHASE_SHIFT: return "max_adc_phase_shift";
case MAX_DBIT_PHASE_SHIFT: return "max_dbit_phase_shift";
case SYNC_CLOCK: return "sync_clock";
default: return "unknown_speed";
}
}
@ -1976,6 +1977,7 @@ int set_speed(int file_des) {
case MAX_DBIT_PHASE_SHIFT:
case ADC_CLOCK:
case DBIT_CLOCK:
case SYNC_CLOCK:
case CLOCK_DIVIDER:
case ADC_PIPELINE:
case DBIT_PIPELINE:
@ -1986,6 +1988,7 @@ int set_speed(int file_des) {
case MAX_DBIT_PHASE_SHIFT:
case ADC_CLOCK:
case DBIT_CLOCK:
case SYNC_CLOCK:
case CLOCK_DIVIDER:
case ADC_PIPELINE:
case DBIT_PIPELINE:

26
slsDetectorSoftware/src/slsDetectorCommand.cpp
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@ -752,19 +752,26 @@ slsDetectorCommand::slsDetectorCommand(multiSlsDetector *det) {
++i;
/*! \page config
- <b>adcclk [i]</b> sets/gets the ADC clock frequency in MHz. CTB & Moench only. It also resets adcphase. \c Returns \c (int)
- <b>adcclk [i]</b> sets/gets the ADC clock frequency in MHz. CTB & Moench only. \c Returns \c (int)
*/
descrToFuncMap[i].m_pFuncName = "adcclk";
descrToFuncMap[i].m_pFuncPtr = &slsDetectorCommand::cmdSpeed;
++i;
/*! \page config
- <b>dbitclk [i]</b> Sets/gets the clock frequency of the latching of the digital bits in MHz. CTB & Moench only. It also resets dbit phase. \c Returns \c (int)
- <b>dbitclk [i]</b> Sets/gets the clock frequency of the latching of the digital bits in MHz. CTB & Moench only. \c Returns \c (int)
*/
descrToFuncMap[i].m_pFuncName = "dbitclk";
descrToFuncMap[i].m_pFuncPtr = &slsDetectorCommand::cmdSpeed;
++i;
/*! \page config
- <b>syncclk </b> Gets the clock frequency of the sync clock in MHz. CTB & Moench only. Get only. \c Returns \c (int)
*/
descrToFuncMap[i].m_pFuncName = "syncclk";
descrToFuncMap[i].m_pFuncPtr = &slsDetectorCommand::cmdSpeed;
++i;
/*! \page config
- <b>adcphase [i] [deg]</b> Sets/gets phase of the ADC clock to i. i is the shift or in degrees if deg is used. deg is optional & only for CTB, Moench and Jungfrau. For CTB & Moench, adcphase is reset if adcclk is changed. For Jungfrau, adcphase changed to defaults if clkdivider changed. Jungfrau, CTB & Moench, these are absolute values with limits. Gotthard, relative phase shift. Not for Eiger. \c Returns \c (int)
*/
@ -4680,6 +4687,12 @@ std::string slsDetectorCommand::cmdSpeed(int narg, const char * const args[], in
else if (cmd == "dbitclk") {
index = DBIT_CLOCK;
}
else if (cmd == "syncclk") {
index = SYNC_CLOCK;
if (action == PUT_ACTION) {
return std::string("cannot put");
}
}
else if (cmd == "adcphase") {
index = ADC_PHASE;
if ((action == PUT_ACTION && narg > 2 && std::string(args[2]) == "deg") ||
@ -4735,8 +4748,8 @@ std::string slsDetectorCommand::helpSpeed(int action) {
std::ostringstream os;
if (action == PUT_ACTION || action == HELP_ACTION) {
os << "clkdivider c \t sets readout clock divider. EIGER, JUNGFRAU [0(fast speed), 1(half speed), 2(quarter speed)]. Jungfrau, full speed is not implemented and overwrites adcphase to recommended default. Not for Gotthard." << std::endl;
os << "adcclk c \tSets ADC clock frequency in MHz. CTB & Moench only. It also resets adcphase." << std::endl;
os << "dbitclk c \tSets the clock frequency of the latching of the digital bits in MHz. CTB & Moench only. It also resets dbit phase." << std::endl;
os << "adcclk c \tSets ADC clock frequency in MHz. CTB & Moench only. " << std::endl;
os << "dbitclk c \tSets the clock frequency of the latching of the digital bits in MHz. CTB & Moench only. " << std::endl;
os << "adcphase c [deg]\t Sets phase of the ADC clock to i. i is the shift or in degrees if deg is used. deg is optional & only for CTB, Moench & Jungfrau. For CTB & Moench, adcphase is reset if adcclk is changed. For Jungfrau, adcphase changed to defaults if clkdivider changed. Jungfrau, CTB & Moench, these are absolute values with limits. Gotthard, relative phase shift. Not for Eiger." << std::endl;
os << "dbitphase c [deg]\t Sets the phase of the clock for latching of the digital bits to i. i is the shift or in degrees if deg is used. deg is optional. dbitphase is also reset if dbitclk is changed. These are absolute values with limits. for CTB & Moench only." << std::endl;
os << "adcpipeline c \t Sets the pipeline of the ADC. For CTB & Moench only." << std::endl;
@ -4745,8 +4758,9 @@ std::string slsDetectorCommand::helpSpeed(int action) {
}
if (action == GET_ACTION || action == HELP_ACTION) {
os << "clkdivider \t Gets readout clock divider. EIGER, JUNGFRAU [0(fast speed), 1(half speed), 2(quarter speed)]. Jungfrau, full speed is not implemented and overwrites adcphase to recommended default. Not for Gotthard." << std::endl;
os << "adcclk \tGets ADC clock frequency in MHz. CTB & Moench only. It also resets adcphase." << std::endl;
os << "dbitclk \tGets the clock frequency of the latching of the digital bits in MHz. CTB & Moench only. It also resets dbit phase." << std::endl;
os << "adcclk \tGets ADC clock frequency in MHz. CTB & Moench only. " << std::endl;
os << "dbitclk \tGets the clock frequency of the latching of the digital bits in MHz. CTB & Moench only. " << std::endl;
os << "syncclk \t Gets the clock frequency of the sync clock in MHz. CTB & Moench only." << std::endl;
os << "adcphase [deg]\t Gets phase of the ADC clock. unit is number of shifts or in degrees if deg is used. deg is optional & only for CTB, Moench & Jungfrau. For CTB & Moench, adcphase is reset if adcclk is changed. For Jungfrau, adcphase changed to defaults if clkdivider changed. Jungfrau, CTB & Moench, these are absolute values with limits. Gotthard, relative phase shift. Not for Eiger." << std::endl;
os << "dbitphase [deg]\t Gets the phase of the clock for latching of the digital bits. unit is number of shifts or in degrees if deg is used. deg is optional. dbitphase is also reset if dbitclk is changed. These are absolute values with limits. for CTB & Moench only." << std::endl;
os << "adcpipeline \t Gets the pipeline of the ADC. For CTB & Moench only." << std::endl;

1
slsSupportLib/include/sls_detector_defs.h
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@ -497,6 +497,7 @@ format
DBIT_PIPELINE, /**< adc pipeline */
MAX_ADC_PHASE_SHIFT, /** max adc phase shift */
MAX_DBIT_PHASE_SHIFT, /** max adc phase shift */
SYNC_CLOCK,
};
/**