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fixed testfpga, fixed pattern reg etc

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git-svn-id: file:///afs/psi.ch/project/sls_det_software/svn/slsDetectorSoftware@110 951219d9-93cf-4727-9268-0efd64621fa3
This commit is contained in:
l_maliakal_d 2012-01-19 11:05:37 +00:00
parent b7bb5a961b
commit 41fea1fbcf
3 changed files with 41 additions and 118 deletions
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139
slsDetectorSoftware/gotthardDetectorServer/firmware_funcs.c
View File

@ -169,7 +169,7 @@ int mapCSP0(void) {
printf("CSPObase is 0x%x \n",CSP0BASE); printf("CSPObase is 0x%x \n",CSP0BASE);
printf("CSPOBASE=from %08x to %x\n",CSP0BASE,CSP0BASE+MEM_SIZE); printf("CSPOBASE=from %08x to %x\n",CSP0BASE,CSP0BASE+MEM_SIZE);
/* must b uncommented later//////////////////////////////////////////////////////// /* must b uncommentedlater////////////////////////////////////////////////////////
values=(u_int32_t*)(CSP0BASE+FIFO_DATA_REG_OFF); values=(u_int32_t*)(CSP0BASE+FIFO_DATA_REG_OFF);
printf("values=%08x\n",values); printf("values=%08x\n",values);
fifocntrl=(u_int32_t*)(CSP0BASE+FIFO_CNTRL_REG_OFF); fifocntrl=(u_int32_t*)(CSP0BASE+FIFO_CNTRL_REG_OFF);
@ -210,50 +210,6 @@ u_int32_t bus_r(u_int32_t offset) {
} }
int setDummyRegister() {
int result = OK;
volatile u_int32_t val,addr;
addr = DUMMY_REG;
int i;
for(i=0;i<100;i++)
{
//dummy register
val=0x5A5A5A5A-i;
bus_w(addr, val);
val=bus_r(addr);
if (val!=0x5A5A5A5A-i) {
printf("ATTEMPT:%d:\tFPGA dummy register wrong!! %x instead of %x \n",i,val,0x5A5A5A5A-i);
result=FAIL;
}
//dummy register
val=0x0F0F0F0F;
bus_w(addr, val);
val=bus_r(addr);
if (val!=0x0F0F0F0F) {
printf("ATTEMPT:%d:\tFPGA dummy register wrong!! %x instead of 0x0F0F0F0F \n",i,val);
result=FAIL;
}
//dummy register
val=0xF0F0F0F0;
bus_w(DUMMY_REG, val);
val=bus_r(DUMMY_REG);
if (val!=0xF0F0F0F0) {
printf("ATTEMPT:%d:\tFPGA dummy register wrong!! %x instead of 0xF0F0F0F0 \n\n",i,val);
result=FAIL;
}
}
if(result==OK)
{
printf("\n\n----------------------------------------------------------------------------------------------");
printf("\nATTEMPT 100: FPGA DUMMY REGISTER OK!!\n");
printf("----------------------------------------------------------------------------------------------\n");
}
return result;
}
int setPhaseShiftOnce(){ int setPhaseShiftOnce(){
u_int32_t addr, reg; u_int32_t addr, reg;
int result=OK, i,val; int result=OK, i,val;
@ -311,38 +267,6 @@ int setDAQRegister()
} }
/*
u_int32_t bus_write(int addr, u_int32_t data) {
u_int32_t *ptr1,offset;
switch(addr){
case ADC_WRITE:
offset=ADC_WRITE_REG;
break;
default:
return FAIL;
}
ptr1=(u_int32_t*)(CSP0BASE+offset*2);
*ptr1=data;
return OK;
}
u_int32_t bus_read(int addr) {
u_int32_t *ptr1,offset;
switch(addr){
case ADC_WRITE:
offset=ADC_WRITE_REG;
break;
default:
offset=ADC_WRITE_REG;
}
ptr1=(u_int32_t*)(CSP0BASE+offset*2);
return *ptr1;
}
*/
// direct pattern output // direct pattern output
u_int32_t putout(char *s, int modnum) { u_int32_t putout(char *s, int modnum) {
int i; int i;
@ -587,18 +511,15 @@ u_int32_t getMcsVersion() {
// for fpga test // for fpga test
u_int32_t testFpga(void) { u_int32_t testFpga(void) {
u_int32_t val; u_int32_t val,addr;
int result=OK; int result=OK,i;
//while (1) {
//fixed pattern //fixed pattern
val=bus_r(FIX_PATT_REG); val=bus_r(FIX_PATT_REG);
if (val==FIXED_PATT_VAL) { if (val==FIXED_PATT_VAL) {
printf("fixed pattern ok!! %08x\n",val); printf("fixed pattern ok!! %08x\n",val);
} else { } else {
printf("fixed pattern wrong!! %08x\n",val); printf("fixed pattern wrong!! %08x\n",val);
result=FAIL; result=FAIL;
// return FAIL;
} }
//FPGA code version //FPGA code version
val=bus_r(FPGA_VERSION_REG)&0x00ffffff; val=bus_r(FPGA_VERSION_REG)&0x00ffffff;
@ -606,32 +527,40 @@ u_int32_t testFpga(void) {
printf("FPGA version ok!! %06x\n",val); printf("FPGA version ok!! %06x\n",val);
} else { } else {
printf("FPGA version too old! %06x\n",val); printf("FPGA version too old! %06x\n",val);
return FAIL; result= FAIL;
} }
//dummy register //dummy register
addr = DUMMY_REG;
for(i=0;i<100;i++)
{
val=0x5A5A5A5A-i;
bus_w(addr, val);
val=bus_r(addr);
if (val!=0x5A5A5A5A-i) {
printf("ATTEMPT:%d:\tFPGA dummy register wrong!! %x instead of %x \n",i,val,0x5A5A5A5A-i);
result=FAIL;
}
val=0x0F0F0F0F;
bus_w(addr, val);
val=bus_r(addr);
if (val!=0x0F0F0F0F) {
printf("ATTEMPT:%d:\tFPGA dummy register wrong!! %x instead of 0x0F0F0F0F \n",i,val);
result=FAIL;
}
val=0xF0F0F0F0; val=0xF0F0F0F0;
bus_w(DUMMY_REG, val); bus_w(DUMMY_REG, val);
val=bus_r(DUMMY_REG); val=bus_r(DUMMY_REG);
if (val==0xF0F0F0F0) { if (val!=0xF0F0F0F0) {
printf("FPGA dummy register ok!! %x\n",val); printf("ATTEMPT:%d:\tFPGA dummy register wrong!! %x instead of 0xF0F0F0F0 \n\n",i,val);
} else {
printf("FPGA dummy register wrong!! %x instead of 0xF0F0F0F0 \n",val);
result=FAIL; result=FAIL;
// return FAIL;
} }
//dummy register
val=0x0F0F0F0F;
bus_w(DUMMY_REG, val);
val=bus_r(DUMMY_REG);
if (val==0x0F0F0F0F) {
printf("FPGA dummy register ok!! %x\n",val);
} else {
printf("FPGA dummy register wrong!! %x instead of 0x0F0F0F0F \n",val);
result=FAIL;
// return FAIL;
} }
// } if(result==OK)
{
printf("----------------------------------------------------------------------------------------------");
printf("\nATTEMPT 100: FPGA DUMMY REGISTER OK!!\n");
printf("----------------------------------------------------------------------------------------------\n");
}
return result; return result;
} }
@ -652,15 +581,11 @@ int getNModBoard() {
int nmodboard; int nmodboard;
u_int32_t val; u_int32_t val;
val=bus_r(FPGA_VERSION_REG)&0xff000000; val=bus_r(FPGA_VERSION_REG)&0xff000000;
nmodboard=val >> 24;
printf("version register %08x\n",val); #ifdef VERY_VERBOSE
nmodboard = 1;//val >> 24;
//#ifdef VERY_VERBOSE
printf("The board hosts %d modules\n",nmodboard); printf("The board hosts %d modules\n",nmodboard);
nmodboard=1;//edited by dhanya #endif
//#endif
nModBoard=nmodboard; nModBoard=nmodboard;
//getNModBoard()=nmodboard;
return nmodboard; return nmodboard;
} }

3
slsDetectorSoftware/gotthardDetectorServer/firmware_funcs.h
View File

@ -24,11 +24,8 @@ u_int16_t bus_w16(u_int32_t offset, u_int16_t data);//aldos function
u_int32_t bus_w(u_int32_t offset, u_int32_t data); u_int32_t bus_w(u_int32_t offset, u_int32_t data);
u_int32_t bus_r(u_int32_t offset); u_int32_t bus_r(u_int32_t offset);
int setDummyRegister();
int setPhaseShiftOnce(); int setPhaseShiftOnce();
int setDAQRegister(); int setDAQRegister();
//u_int32_t bus_write(int addr, u_int32_t data);
//u_int32_t bus_read(int addr);
u_int32_t putout(char *s, int modnum); u_int32_t putout(char *s, int modnum);
u_int32_t readin(int modnum); u_int32_t readin(int modnum);

3
slsDetectorSoftware/gotthardDetectorServer/server_funcs.c
View File

@ -71,7 +71,8 @@ int init_detector( int b) {
initDetector(); initDetector();
printf("\ninitdetector done! \n"); printf("\ninitdetector done! \n");
testFpga(); testFpga();
setDummyRegister();
//gotthard specific
setPhaseShiftOnce(); setPhaseShiftOnce();
setDAQRegister(); setDAQRegister();
setSettings(GET_SETTINGS,-1); setSettings(GET_SETTINGS,-1);