mirror of
https://github.com/slsdetectorgroup/slsDetectorPackage.git
synced 2026-01-16 21:24:39 +01:00
PR minor changes
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@@ -32,12 +32,12 @@ int virtual_status = 0;
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int virtual_stop = 0;
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#endif
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int32_t clkPhase[NUM_CLOCKS] = {0, 0, 0, 0, 0};
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uint32_t clkFrequency[NUM_CLOCKS] = {0, 0, 0, 0, 0};
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int32_t clkPhase[NUM_CLOCKS] = {};
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uint32_t clkFrequency[NUM_CLOCKS] = {};
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int highvoltage = 0;
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int dacValues[NDAC] = {0};
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int detPos[2] = {0, 0};
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int detPos[2] = {};
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uint32_t countermask = 0; // will be removed later when in firmware converted to mask
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int isInitCheckDone() {
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@@ -158,7 +158,7 @@ int checkType() {
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#ifdef VIRTUAL
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return OK;
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#endif
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volatile u_int32_t type = ((bus_r(FPGA_VERSION_REG) & DETECTOR_TYPE_MSK) >> DETECTOR_TYPE_OFST);
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u_int32_t type = ((bus_r(FPGA_VERSION_REG) & DETECTOR_TYPE_MSK) >> DETECTOR_TYPE_OFST);
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if (type != MYTHEN3){
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FILE_LOG(logERROR, ("This is not a Mythen3 Server (read %d, expected %d)\n", type, MYTHEN3));
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return FAIL;
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@@ -703,7 +703,7 @@ int setHighVoltage(int val){
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/* parameters - timing */
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void setTiming( enum timingMode arg){
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if(arg != GET_TIMING_MODE){
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switch((int)arg){
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switch (arg) {
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case AUTO_TIMING:
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FILE_LOG(logINFO, ("Set Timing: Auto\n"));
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bus_w(EXT_SIGNAL_REG, bus_r(EXT_SIGNAL_REG) & ~EXT_SIGNAL_MSK);
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@@ -714,7 +714,6 @@ void setTiming( enum timingMode arg){
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break;
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default:
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FILE_LOG(logERROR, ("Unknown timing mode %d\n", arg));
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return;
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}
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}
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}
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@@ -1146,8 +1145,8 @@ int setPhase(enum CLKINDEX ind, int val, int degrees) {
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relativePhase *= -1;
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direction = 0;
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}
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int pllIndex = ind >= SYSTEM_C0 ? SYSTEM_PLL : READOUT_PLL;
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int clkIndex = ind >= SYSTEM_C0 ? ind - SYSTEM_C0 : ind;
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int pllIndex = (int)(ind >= SYSTEM_C0 ? SYSTEM_PLL : READOUT_PLL);
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int clkIndex = (int)(ind >= SYSTEM_C0 ? ind - SYSTEM_C0 : ind);
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ALTERA_PLL_C10_SetPhaseShift(pllIndex, clkIndex, relativePhase, direction);
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clkPhase[ind] = valShift;
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@@ -1219,7 +1218,7 @@ int getVCOFrequency(enum CLKINDEX ind) {
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FILE_LOG(logERROR, ("Unknown clock index %d to get vco frequency\n", ind));
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return -1;
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}
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int pllIndex = ind >= SYSTEM_C0 ? SYSTEM_PLL : READOUT_PLL;
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int pllIndex = (int)(ind >= SYSTEM_C0 ? SYSTEM_PLL : READOUT_PLL);
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return ALTERA_PLL_C10_GetVCOFrequency(pllIndex);
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}
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@@ -1237,7 +1236,7 @@ int setClockDivider(enum CLKINDEX ind, int val) {
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}
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char* clock_names[] = {CLK_NAMES};
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int vcofreq = getVCOFrequency(ind);
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int currentdiv = vcofreq / clkFrequency[ind];
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int currentdiv = vcofreq / (int)clkFrequency[ind];
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int newfreq = vcofreq / val;
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FILE_LOG(logINFO, ("\tSetting %s clock (%d) divider from %d (%d Hz) to %d (%d Hz). \n\t(Vcofreq: %d Hz)\n", clock_names[ind], ind, currentdiv, clkFrequency[ind], val, newfreq, vcofreq));
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@@ -1252,8 +1251,8 @@ int setClockDivider(enum CLKINDEX ind, int val) {
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}
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// Calculate and set output frequency
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int pllIndex = ind >= SYSTEM_C0 ? SYSTEM_PLL : READOUT_PLL;
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int clkIndex = ind >= SYSTEM_C0 ? ind - SYSTEM_C0 : ind;
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int pllIndex = (int)(ind >= SYSTEM_C0 ? SYSTEM_PLL : READOUT_PLL);
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int clkIndex = (int)(ind >= SYSTEM_C0 ? ind - SYSTEM_C0 : ind);
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ALTERA_PLL_C10_SetOuputFrequency (pllIndex, clkIndex, newfreq);
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clkFrequency[ind] = newfreq;
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FILE_LOG(logINFO, ("\t%s clock (%d) divider set to %d (%d Hz)\n", clock_names[ind], ind, val, clkFrequency[ind]));
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@@ -1287,7 +1286,7 @@ int getClockDivider(enum CLKINDEX ind) {
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FILE_LOG(logERROR, ("Unknown clock index %d to get clock divider\n", ind));
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return -1;
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}
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return (getVCOFrequency(ind) / clkFrequency[ind]);
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return (getVCOFrequency(ind) / (int)clkFrequency[ind]);
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}
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/* aquisition */
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@@ -1479,7 +1478,7 @@ int calculateDataBytes() {
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return 0;
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}
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int getTotalNumberOfChannels() {return ((int)getNumberOfChannelsPerChip() * (int)getNumberOfChips());}
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int getTotalNumberOfChannels() {return (getNumberOfChannelsPerChip() * getNumberOfChips());}
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int getNumberOfChips() {return NCHIP;}
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int getNumberOfDACs() {return NDAC;}
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int getNumberOfChannelsPerChip() {return NCHAN;}
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