PR minor changes

This commit is contained in:
2020-01-22 13:55:10 +01:00
parent d8fccdcefa
commit 3ea2520615
15 changed files with 54 additions and 55 deletions

View File

@@ -37,8 +37,8 @@ int virtual_stop = 0;
#endif
enum detectorSettings thisSettings = UNINITIALIZED;
int32_t clkPhase[NUM_CLOCKS] = {0, 0, 0, 0, 0, 0};
uint32_t clkFrequency[NUM_CLOCKS] = {0, 0, 0, 0, 0, 0};
int32_t clkPhase[NUM_CLOCKS] = {};
uint32_t clkFrequency[NUM_CLOCKS] = {};
int highvoltage = 0;
int dacValues[NDAC] = {0};
int onChipdacValues[ONCHIP_NDAC][NCHIP] = {0};
@@ -51,7 +51,7 @@ enum burstModeType burstType = INTERNAL;
int64_t exptime_ns = 0;
int64_t period_ns = 0;
int64_t nframes = 0;
int detPos[2] = {0, 0};
int detPos[2] = {};
int isInitCheckDone() {
return initCheckDone;
@@ -171,7 +171,7 @@ int checkType() {
#ifdef VIRTUAL
return OK;
#endif
volatile u_int32_t type = ((bus_r(FPGA_VERSION_REG) & DETECTOR_TYPE_MSK) >> DETECTOR_TYPE_OFST);
u_int32_t type = ((bus_r(FPGA_VERSION_REG) & DETECTOR_TYPE_MSK) >> DETECTOR_TYPE_OFST);
if (type != GOTTHARD2){
FILE_LOG(logERROR, ("This is not a Gotthard2 Server (read %d, expected %d)\n", type, GOTTHARD2));
return FAIL;
@@ -1092,7 +1092,7 @@ int setHighVoltage(int val){
/* parameters - timing */
void setTiming( enum timingMode arg){
if(arg != GET_TIMING_MODE){
switch((int)arg){
switch(arg){
case AUTO_TIMING:
FILE_LOG(logINFO, ("Set Timing: Auto\n"));
bus_w(EXT_SIGNAL_REG, bus_r(EXT_SIGNAL_REG) & ~EXT_SIGNAL_MSK);
@@ -1356,8 +1356,8 @@ int setPhase(enum CLKINDEX ind, int val, int degrees) {
relativePhase *= -1;
direction = 0;
}
int pllIndex = ind >= SYSTEM_C0 ? SYSTEM_PLL : READOUT_PLL;
int clkIndex = ind >= SYSTEM_C0 ? ind - SYSTEM_C0 : ind;
int pllIndex = (int)(ind >= SYSTEM_C0 ? SYSTEM_PLL : READOUT_PLL);
int clkIndex = (int)(ind >= SYSTEM_C0 ? ind - SYSTEM_C0 : ind);
ALTERA_PLL_C10_SetPhaseShift(pllIndex, clkIndex, relativePhase, direction);
clkPhase[ind] = valShift;
@@ -1429,7 +1429,7 @@ int getVCOFrequency(enum CLKINDEX ind) {
FILE_LOG(logERROR, ("Unknown clock index %d to get vco frequency\n", ind));
return -1;
}
int pllIndex = ind >= SYSTEM_C0 ? SYSTEM_PLL : READOUT_PLL;
int pllIndex = (int)(ind >= SYSTEM_C0 ? SYSTEM_PLL : READOUT_PLL);
return ALTERA_PLL_C10_GetVCOFrequency(pllIndex);
}
@@ -1447,7 +1447,7 @@ int setClockDivider(enum CLKINDEX ind, int val) {
}
char* clock_names[] = {CLK_NAMES};
int vcofreq = getVCOFrequency(ind);
int currentdiv = vcofreq / clkFrequency[ind];
int currentdiv = vcofreq / (int)clkFrequency[ind];
int newfreq = vcofreq / val;
FILE_LOG(logINFO, ("\tSetting %s clock (%d) divider from %d (%d Hz) to %d (%d Hz). \n\t(Vcofreq: %d Hz)\n", clock_names[ind], ind, currentdiv, clkFrequency[ind], val, newfreq, vcofreq));
@@ -1463,8 +1463,8 @@ int setClockDivider(enum CLKINDEX ind, int val) {
}
// Calculate and set output frequency
int pllIndex = ind >= SYSTEM_C0 ? SYSTEM_PLL : READOUT_PLL;
int clkIndex = ind >= SYSTEM_C0 ? ind - SYSTEM_C0 : ind;
int pllIndex = (int)(ind >= SYSTEM_C0 ? SYSTEM_PLL : READOUT_PLL);
int clkIndex = (int)(ind >= SYSTEM_C0 ? ind - SYSTEM_C0 : ind);
ALTERA_PLL_C10_SetOuputFrequency (pllIndex, clkIndex, newfreq);
clkFrequency[ind] = newfreq;
FILE_LOG(logINFO, ("\t%s clock (%d) divider set to %d (%d Hz)\n", clock_names[ind], ind, val, clkFrequency[ind]));
@@ -1499,7 +1499,7 @@ int getClockDivider(enum CLKINDEX ind) {
FILE_LOG(logERROR, ("Unknown clock index %d to get clock divider\n", ind));
return -1;
}
return (getVCOFrequency(ind) / clkFrequency[ind]);
return (getVCOFrequency(ind) / (int)clkFrequency[ind]);
}
int setInjectChannel(int offset, int increment) {
@@ -2106,7 +2106,7 @@ int calculateDataBytes() {
return getTotalNumberOfChannels() * DYNAMIC_RANGE;
}
int getTotalNumberOfChannels() {return ((int)getNumberOfChannelsPerChip() * (int)getNumberOfChips());}
int getTotalNumberOfChannels() {return (getNumberOfChannelsPerChip() * getNumberOfChips());}
int getNumberOfChips() {return NCHIP;}
int getNumberOfDACs() {return NDAC;}
int getNumberOfChannelsPerChip() {return NCHAN;}