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gotthard2: bug fix from previosu commit

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This commit is contained in:
maliakal_d 2020-02-04 12:32:37 +01:00
parent d3dc9a7690
commit 37c3048c2a
3 changed files with 6 additions and 1 deletions
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BIN
slsDetectorServers/gotthard2DetectorServer/bin/gotthard2DetectorServer_developer
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5
slsDetectorServers/gotthard2DetectorServer/slsDetectorFunctionList.c
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@ -860,6 +860,7 @@ int setPeriodBurst(int64_t val) {
} }
int64_t getPeriodBurst() { int64_t getPeriodBurst() {
FILE_LOG(logDEBUG, ("Getting period [Burst mode]\n"));
return get64BitReg(ASIC_INT_PERIOD_LSB_REG, ASIC_INT_PERIOD_MSB_REG)/ (1E-9 * clkFrequency[SYSTEM_C0]); return get64BitReg(ASIC_INT_PERIOD_LSB_REG, ASIC_INT_PERIOD_MSB_REG)/ (1E-9 * clkFrequency[SYSTEM_C0]);
} }
@ -878,6 +879,7 @@ int setPeriodCont(int64_t val) {
} }
int64_t getPeriodCont() { int64_t getPeriodCont() {
FILE_LOG(logDEBUG, ("Getting period [Continuous mode]\n"));
return get64BitReg(SET_PERIOD_LSB_REG, SET_PERIOD_MSB_REG)/ (1E-9 * FIXED_PLL_FREQUENCY); return get64BitReg(SET_PERIOD_LSB_REG, SET_PERIOD_MSB_REG)/ (1E-9 * FIXED_PLL_FREQUENCY);
} }
@ -1849,10 +1851,13 @@ enum burstMode getBurstMode() {
switch (runmode) { switch (runmode) {
case ASIC_CONFIG_RUN_MODE_CONT_VAL: case ASIC_CONFIG_RUN_MODE_CONT_VAL:
burstMode = BURST_OFF; burstMode = BURST_OFF;
break;
case ASIC_CONFIG_RUN_MODE_INT_BURST_VAL: case ASIC_CONFIG_RUN_MODE_INT_BURST_VAL:
burstMode = BURST_INTERNAL; burstMode = BURST_INTERNAL;
break;
case ASIC_CONFIG_RUN_MODE_EXT_BURST_VAL: case ASIC_CONFIG_RUN_MODE_EXT_BURST_VAL:
burstMode = BURST_EXTERNAL; burstMode = BURST_EXTERNAL;
break;
default: default:
FILE_LOG(logERROR, ("Unknown run mode read from FPGA %d\n", runmode)); FILE_LOG(logERROR, ("Unknown run mode read from FPGA %d\n", runmode));
return -1; return -1;

2
slsDetectorServers/gotthard2DetectorServer/slsDetectorServer_defs.h
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@ -34,7 +34,7 @@
#define DEFAULT_NUM_FRAMES (1) #define DEFAULT_NUM_FRAMES (1)
#define DEFAULT_NUM_CYCLES (1) #define DEFAULT_NUM_CYCLES (1)
#define DEFAULT_EXPTIME (0) // 0 ms (220ns in firmware) #define DEFAULT_EXPTIME (0) // 0 ms (220ns in firmware)
#define DEFAULT_PERIOD (0) // 1 ms #define DEFAULT_PERIOD (0) // 0 ms
#define DEFAULT_DELAY_AFTER_TRIGGER (0) #define DEFAULT_DELAY_AFTER_TRIGGER (0)
#define DEFAULT_HIGH_VOLTAGE (0) #define DEFAULT_HIGH_VOLTAGE (0)
#define DEFAULT_TIMING_MODE (AUTO_TIMING) #define DEFAULT_TIMING_MODE (AUTO_TIMING)